3 * Copyright (c) Fuzhou Rockchip Electronics Co.Ltd
5 * Mark Yao <yzq@rock-chips.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
15 #ifndef _UAPI_ROCKCHIP_DRM_H
16 #define _UAPI_ROCKCHIP_DRM_H
20 /* memory type definitions. */
21 enum drm_rockchip_gem_mem_type {
22 /* Physically Continuous memory and used as default. */
23 ROCKCHIP_BO_CONTIG = 0 << 0,
24 /* Physically Non-Continuous memory. */
25 ROCKCHIP_BO_NONCONTIG = 1 << 0,
26 /* non-cachable mapping and used as default. */
27 ROCKCHIP_BO_NONCACHABLE = 0 << 1,
28 /* cachable mapping. */
29 ROCKCHIP_BO_CACHABLE = 1 << 1,
30 /* write-combine mapping. */
31 ROCKCHIP_BO_WC = 1 << 2,
32 ROCKCHIP_BO_MASK = ROCKCHIP_BO_NONCONTIG | ROCKCHIP_BO_CACHABLE |
37 * User-desired buffer creation information structure.
39 * @size: user-desired memory allocation size.
40 * @flags: user request for setting memory type or cache attributes.
41 * @handle: returned a handle to created gem object.
42 * - this handle will be set by gem module of kernel side.
44 struct drm_rockchip_gem_create {
51 * A structure for getting buffer offset.
53 * @handle: a pointer to gem object created.
54 * @pad: just padding to be 64-bit aligned.
55 * @offset: relatived offset value of the memory region allocated.
56 * - this value should be set by user.
58 struct drm_rockchip_gem_map_off {
64 /* acquire type definitions. */
65 enum drm_rockchip_gem_cpu_acquire_type {
66 DRM_ROCKCHIP_GEM_CPU_ACQUIRE_SHARED = 0x0,
67 DRM_ROCKCHIP_GEM_CPU_ACQUIRE_EXCLUSIVE = 0x1,
71 * A structure for acquiring buffer for CPU access.
73 * @handle: a handle to gem object created.
74 * @flags: acquire flag
76 struct drm_rockchip_gem_cpu_acquire {
82 * A structure for releasing buffer for GPU access.
84 * @handle: a handle to gem object created.
86 struct drm_rockchip_gem_cpu_release {
90 struct drm_rockchip_rga_get_ver {
95 struct drm_rockchip_rga_cmd {
100 enum drm_rockchip_rga_buf_type {
101 RGA_BUF_TYPE_USERPTR = 1 << 31,
102 RGA_BUF_TYPE_GEMFD = 1 << 30,
103 RGA_BUF_TYPE_FLUSH = 1 << 29,
106 struct drm_rockchip_rga_set_cmdlist {
114 struct drm_rockchip_rga_exec {
118 enum rockchip_plane_feture {
119 ROCKCHIP_DRM_PLANE_FEATURE_SCALE,
120 ROCKCHIP_DRM_PLANE_FEATURE_ALPHA,
121 ROCKCHIP_DRM_PLANE_FEATURE_MAX,
124 enum rockchip_crtc_feture {
125 ROCKCHIP_DRM_CRTC_FEATURE_AFBDC,
128 #define DRM_ROCKCHIP_GEM_CREATE 0x00
129 #define DRM_ROCKCHIP_GEM_MAP_OFFSET 0x01
130 #define DRM_ROCKCHIP_GEM_CPU_ACQUIRE 0x02
131 #define DRM_ROCKCHIP_GEM_CPU_RELEASE 0x03
133 #define DRM_ROCKCHIP_RGA_GET_VER 0x20
134 #define DRM_ROCKCHIP_RGA_SET_CMDLIST 0x21
135 #define DRM_ROCKCHIP_RGA_EXEC 0x22
137 #define DRM_IOCTL_ROCKCHIP_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
138 DRM_ROCKCHIP_GEM_CREATE, struct drm_rockchip_gem_create)
140 #define DRM_IOCTL_ROCKCHIP_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \
141 DRM_ROCKCHIP_GEM_MAP_OFFSET, struct drm_rockchip_gem_map_off)
143 #define DRM_IOCTL_ROCKCHIP_GEM_CPU_ACQUIRE DRM_IOWR(DRM_COMMAND_BASE + \
144 DRM_ROCKCHIP_GEM_CPU_ACQUIRE, struct drm_rockchip_gem_cpu_acquire)
146 #define DRM_IOCTL_ROCKCHIP_GEM_CPU_RELEASE DRM_IOWR(DRM_COMMAND_BASE + \
147 DRM_ROCKCHIP_GEM_CPU_RELEASE, struct drm_rockchip_gem_cpu_release)
149 #define DRM_IOCTL_ROCKCHIP_RGA_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
150 DRM_ROCKCHIP_RGA_GET_VER, struct drm_rockchip_rga_get_ver)
152 #define DRM_IOCTL_ROCKCHIP_RGA_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
153 DRM_ROCKCHIP_RGA_SET_CMDLIST, struct drm_rockchip_rga_set_cmdlist)
155 #define DRM_IOCTL_ROCKCHIP_RGA_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
156 DRM_ROCKCHIP_RGA_EXEC, struct drm_rockchip_rga_exec)
158 #endif /* _UAPI_ROCKCHIP_DRM_H */