3 * Copyright (c) Fuzhou Rockchip Electronics Co.Ltd
5 * Mark Yao <yzq@rock-chips.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
15 #ifndef _UAPI_ROCKCHIP_DRM_H
16 #define _UAPI_ROCKCHIP_DRM_H
20 /* memory type definitions. */
21 enum drm_rockchip_gem_mem_type {
22 /* Physically Continuous memory. */
23 ROCKCHIP_BO_CONTIG = 1 << 0,
24 /* cachable mapping. */
25 ROCKCHIP_BO_CACHABLE = 1 << 1,
26 /* write-combine mapping. */
27 ROCKCHIP_BO_WC = 1 << 2,
28 ROCKCHIP_BO_SECURE = 1 << 3,
29 ROCKCHIP_BO_MASK = ROCKCHIP_BO_CONTIG | ROCKCHIP_BO_CACHABLE |
34 * User-desired buffer creation information structure.
36 * @size: user-desired memory allocation size.
37 * @flags: user request for setting memory type or cache attributes.
38 * @handle: returned a handle to created gem object.
39 * - this handle will be set by gem module of kernel side.
41 struct drm_rockchip_gem_create {
47 struct drm_rockchip_gem_phys {
53 * A structure for getting buffer offset.
55 * @handle: a pointer to gem object created.
56 * @pad: just padding to be 64-bit aligned.
57 * @offset: relatived offset value of the memory region allocated.
58 * - this value should be set by user.
60 struct drm_rockchip_gem_map_off {
66 /* acquire type definitions. */
67 enum drm_rockchip_gem_cpu_acquire_type {
68 DRM_ROCKCHIP_GEM_CPU_ACQUIRE_SHARED = 0x0,
69 DRM_ROCKCHIP_GEM_CPU_ACQUIRE_EXCLUSIVE = 0x1,
73 * A structure for acquiring buffer for CPU access.
75 * @handle: a handle to gem object created.
76 * @flags: acquire flag
78 struct drm_rockchip_gem_cpu_acquire {
84 * A structure for releasing buffer for GPU access.
86 * @handle: a handle to gem object created.
88 struct drm_rockchip_gem_cpu_release {
92 struct drm_rockchip_rga_get_ver {
97 struct drm_rockchip_rga_cmd {
102 enum drm_rockchip_rga_buf_type {
103 RGA_BUF_TYPE_USERPTR = 1 << 31,
104 RGA_BUF_TYPE_GEMFD = 1 << 30,
105 RGA_BUF_TYPE_FLUSH = 1 << 29,
108 struct drm_rockchip_rga_set_cmdlist {
116 struct drm_rockchip_rga_exec {
120 enum rockchip_plane_feture {
121 ROCKCHIP_DRM_PLANE_FEATURE_SCALE,
122 ROCKCHIP_DRM_PLANE_FEATURE_ALPHA,
123 ROCKCHIP_DRM_PLANE_FEATURE_MAX,
126 enum rockchip_crtc_feture {
127 ROCKCHIP_DRM_CRTC_FEATURE_AFBDC,
130 enum rockchip_cabc_mode {
131 ROCKCHIP_DRM_CABC_MODE_DISABLE,
132 ROCKCHIP_DRM_CABC_MODE_NORMAL,
133 ROCKCHIP_DRM_CABC_MODE_LOWPOWER,
134 ROCKCHIP_DRM_CABC_MODE_USERSPACE,
137 #define DRM_ROCKCHIP_GEM_CREATE 0x00
138 #define DRM_ROCKCHIP_GEM_MAP_OFFSET 0x01
139 #define DRM_ROCKCHIP_GEM_CPU_ACQUIRE 0x02
140 #define DRM_ROCKCHIP_GEM_CPU_RELEASE 0x03
141 #define DRM_ROCKCHIP_GEM_GET_PHYS 0x04
143 #define DRM_ROCKCHIP_RGA_GET_VER 0x20
144 #define DRM_ROCKCHIP_RGA_SET_CMDLIST 0x21
145 #define DRM_ROCKCHIP_RGA_EXEC 0x22
147 #define DRM_IOCTL_ROCKCHIP_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
148 DRM_ROCKCHIP_GEM_CREATE, struct drm_rockchip_gem_create)
150 #define DRM_IOCTL_ROCKCHIP_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \
151 DRM_ROCKCHIP_GEM_MAP_OFFSET, struct drm_rockchip_gem_map_off)
153 #define DRM_IOCTL_ROCKCHIP_GEM_CPU_ACQUIRE DRM_IOWR(DRM_COMMAND_BASE + \
154 DRM_ROCKCHIP_GEM_CPU_ACQUIRE, struct drm_rockchip_gem_cpu_acquire)
156 #define DRM_IOCTL_ROCKCHIP_GEM_CPU_RELEASE DRM_IOWR(DRM_COMMAND_BASE + \
157 DRM_ROCKCHIP_GEM_CPU_RELEASE, struct drm_rockchip_gem_cpu_release)
159 #define DRM_IOCTL_ROCKCHIP_GEM_GET_PHYS DRM_IOWR(DRM_COMMAND_BASE + \
160 DRM_ROCKCHIP_GEM_GET_PHYS, struct drm_rockchip_gem_phys)
162 #define DRM_IOCTL_ROCKCHIP_RGA_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
163 DRM_ROCKCHIP_RGA_GET_VER, struct drm_rockchip_rga_get_ver)
165 #define DRM_IOCTL_ROCKCHIP_RGA_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
166 DRM_ROCKCHIP_RGA_SET_CMDLIST, struct drm_rockchip_rga_set_cmdlist)
168 #define DRM_IOCTL_ROCKCHIP_RGA_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
169 DRM_ROCKCHIP_RGA_EXEC, struct drm_rockchip_rga_exec)
171 #endif /* _UAPI_ROCKCHIP_DRM_H */