2 * Copyright 2005-2009 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU Lesser General
5 * Public License. You may obtain a copy of the GNU Lesser General
6 * Public License Version 2.1 or later at the following locations:
8 * http://www.opensource.org/licenses/lgpl-license.html
9 * http://www.gnu.org/copyleft/lgpl.html
15 #include <linux/types.h>
16 #include <linux/videodev2.h>
17 #include <linux/bitmap.h>
28 #define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
31 * Bitfield of Display Interface signal polarities.
33 struct ipu_di_signal_cfg {
34 unsigned datamask_en:1;
35 unsigned interlaced:1;
36 unsigned odd_field_first:1;
38 unsigned clkidle_en:1;
39 unsigned data_pol:1; /* true = inverted */
40 unsigned clk_pol:1; /* true = rising edge */
41 unsigned enable_pol:1;
42 unsigned Hsync_pol:1; /* true = active high */
55 unsigned long pixelclock;
56 #define IPU_DI_CLKMODE_SYNC (1 << 0)
57 #define IPU_DI_CLKMODE_EXT (1 << 1)
58 unsigned long clkflags;
64 enum ipu_color_space {
67 IPUV3_COLORSPACE_UNKNOWN,
72 enum ipu_channel_irq {
75 IPU_IRQ_NFB4EOF = 128,
79 int ipu_map_irq(struct ipu_soc *ipu, int irq);
80 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
81 enum ipu_channel_irq irq);
83 #define IPU_IRQ_DP_SF_START (448 + 2)
84 #define IPU_IRQ_DP_SF_END (448 + 3)
85 #define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
86 #define IPU_IRQ_DC_FC_0 (448 + 8)
87 #define IPU_IRQ_DC_FC_1 (448 + 9)
88 #define IPU_IRQ_DC_FC_2 (448 + 10)
89 #define IPU_IRQ_DC_FC_3 (448 + 11)
90 #define IPU_IRQ_DC_FC_4 (448 + 12)
91 #define IPU_IRQ_DC_FC_6 (448 + 13)
92 #define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
93 #define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
96 * IPU Image DMA Controller (idmac) functions
98 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
99 void ipu_idmac_put(struct ipuv3_channel *);
101 int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
102 int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
103 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
105 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
107 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
108 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
111 * IPU Channel Parameter Memory (cpmem) functions
114 struct fb_bitfield red;
115 struct fb_bitfield green;
116 struct fb_bitfield blue;
117 struct fb_bitfield transp;
122 struct v4l2_pix_format pix;
123 struct v4l2_rect rect;
127 void ipu_cpmem_zero(struct ipuv3_channel *ch);
128 void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
129 void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
130 void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
131 void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
132 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
133 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
134 int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
135 const struct ipu_rgb *rgb);
136 int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
137 void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
138 void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
139 u32 pixel_format, int stride,
140 int u_offset, int v_offset);
141 void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
142 u32 pixel_format, int stride, int height);
143 int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
144 int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
147 * IPU Display Controller (dc) functions
151 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
152 void ipu_dc_put(struct ipu_dc *dc);
153 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
154 u32 pixel_fmt, u32 width);
155 void ipu_dc_enable(struct ipu_soc *ipu);
156 void ipu_dc_enable_channel(struct ipu_dc *dc);
157 void ipu_dc_disable_channel(struct ipu_dc *dc);
158 void ipu_dc_disable(struct ipu_soc *ipu);
161 * IPU Display Interface (di) functions
163 struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
164 void ipu_di_put(struct ipu_di *);
165 int ipu_di_disable(struct ipu_di *);
166 int ipu_di_enable(struct ipu_di *);
167 int ipu_di_get_num(struct ipu_di *);
168 int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
171 * IPU Display Multi FIFO Controller (dmfc) functions
174 int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
175 void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
176 int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
177 unsigned long bandwidth_mbs, int burstsize);
178 void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc);
179 int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width);
180 struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
181 void ipu_dmfc_put(struct dmfc_channel *dmfc);
184 * IPU Display Processor (dp) functions
186 #define IPU_DP_FLOW_SYNC_BG 0
187 #define IPU_DP_FLOW_SYNC_FG 1
188 #define IPU_DP_FLOW_ASYNC0_BG 2
189 #define IPU_DP_FLOW_ASYNC0_FG 3
190 #define IPU_DP_FLOW_ASYNC1_BG 4
191 #define IPU_DP_FLOW_ASYNC1_FG 5
193 struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
194 void ipu_dp_put(struct ipu_dp *);
195 int ipu_dp_enable(struct ipu_soc *ipu);
196 int ipu_dp_enable_channel(struct ipu_dp *dp);
197 void ipu_dp_disable_channel(struct ipu_dp *dp);
198 void ipu_dp_disable(struct ipu_soc *ipu);
199 int ipu_dp_setup_channel(struct ipu_dp *dp,
200 enum ipu_color_space in, enum ipu_color_space out);
201 int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
202 int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
206 * IPU CMOS Sensor Interface (csi) functions
208 int ipu_csi_enable(struct ipu_soc *ipu, int csi);
209 int ipu_csi_disable(struct ipu_soc *ipu, int csi);
212 * IPU Sensor Multiple FIFO Controller (SMFC) functions
214 int ipu_smfc_enable(struct ipu_soc *ipu);
215 int ipu_smfc_disable(struct ipu_soc *ipu);
216 int ipu_smfc_map_channel(struct ipu_soc *ipu, int channel, int csi_id, int mipi_id);
217 int ipu_smfc_set_burstsize(struct ipu_soc *ipu, int channel, int burstsize);
219 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
220 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
222 struct ipu_client_platformdata {
231 #endif /* __DRM_IPU_H__ */