2 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __OMAP_OMAPDSS_H
19 #define __OMAP_OMAPDSS_H
21 #include <linux/list.h>
22 #include <linux/kobject.h>
23 #include <linux/device.h>
25 #define DISPC_IRQ_FRAMEDONE (1 << 0)
26 #define DISPC_IRQ_VSYNC (1 << 1)
27 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
28 #define DISPC_IRQ_EVSYNC_ODD (1 << 3)
29 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
30 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
31 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
32 #define DISPC_IRQ_GFX_END_WIN (1 << 7)
33 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
34 #define DISPC_IRQ_OCP_ERR (1 << 9)
35 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
36 #define DISPC_IRQ_VID1_END_WIN (1 << 11)
37 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
38 #define DISPC_IRQ_VID2_END_WIN (1 << 13)
39 #define DISPC_IRQ_SYNC_LOST (1 << 14)
40 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
41 #define DISPC_IRQ_WAKEUP (1 << 16)
42 #define DISPC_IRQ_SYNC_LOST2 (1 << 17)
43 #define DISPC_IRQ_VSYNC2 (1 << 18)
44 #define DISPC_IRQ_VID3_END_WIN (1 << 19)
45 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
46 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
47 #define DISPC_IRQ_FRAMEDONE2 (1 << 22)
48 #define DISPC_IRQ_FRAMEDONEWB (1 << 23)
49 #define DISPC_IRQ_FRAMEDONETV (1 << 24)
50 #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
51 #define DISPC_IRQ_FRAMEDONE3 (1 << 26)
52 #define DISPC_IRQ_VSYNC3 (1 << 27)
53 #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 28)
54 #define DISPC_IRQ_SYNC_LOST3 (1 << 29)
56 struct omap_dss_device;
57 struct omap_overlay_manager;
58 struct snd_aes_iec958;
59 struct snd_cea_861_aud_if;
61 enum omap_display_type {
62 OMAP_DISPLAY_TYPE_NONE = 0,
63 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
64 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
65 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
66 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
67 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
68 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
79 OMAP_DSS_CHANNEL_LCD = 0,
80 OMAP_DSS_CHANNEL_DIGIT = 1,
81 OMAP_DSS_CHANNEL_LCD2 = 2,
82 OMAP_DSS_CHANNEL_LCD3 = 3,
85 enum omap_color_mode {
86 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
87 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
88 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
89 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
90 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
91 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
92 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
93 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
94 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
95 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
96 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
97 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
98 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
99 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
100 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
101 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
102 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
103 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
104 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
107 enum omap_dss_load_mode {
108 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
109 OMAP_DSS_LOAD_CLUT_ONLY = 1,
110 OMAP_DSS_LOAD_FRAME_ONLY = 2,
111 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
114 enum omap_dss_trans_key_type {
115 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
116 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
119 enum omap_rfbi_te_mode {
120 OMAP_DSS_RFBI_TE_MODE_1 = 1,
121 OMAP_DSS_RFBI_TE_MODE_2 = 2,
124 enum omap_panel_config {
125 OMAP_DSS_LCD_IVS = 1<<0,
126 OMAP_DSS_LCD_IHS = 1<<1,
127 OMAP_DSS_LCD_IPC = 1<<2,
128 OMAP_DSS_LCD_IEO = 1<<3,
129 OMAP_DSS_LCD_RF = 1<<4,
130 OMAP_DSS_LCD_ONOFF = 1<<5,
133 enum omap_dss_signal_level {
134 OMAPDSS_SIG_ACTIVE_HIGH = 0,
135 OMAPDSS_SIG_ACTIVE_LOW = 1,
138 enum omap_dss_signal_edge {
139 OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
140 OMAPDSS_DRIVE_SIG_RISING_EDGE,
141 OMAPDSS_DRIVE_SIG_FALLING_EDGE,
144 enum omap_dss_venc_type {
145 OMAP_DSS_VENC_TYPE_COMPOSITE,
146 OMAP_DSS_VENC_TYPE_SVIDEO,
149 enum omap_dss_dsi_pixel_format {
150 OMAP_DSS_DSI_FMT_RGB888,
151 OMAP_DSS_DSI_FMT_RGB666,
152 OMAP_DSS_DSI_FMT_RGB666_PACKED,
153 OMAP_DSS_DSI_FMT_RGB565,
156 enum omap_dss_dsi_mode {
157 OMAP_DSS_DSI_CMD_MODE = 0,
158 OMAP_DSS_DSI_VIDEO_MODE,
161 enum omap_display_caps {
162 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
163 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
166 enum omap_dss_display_state {
167 OMAP_DSS_DISPLAY_DISABLED = 0,
168 OMAP_DSS_DISPLAY_ACTIVE,
169 OMAP_DSS_DISPLAY_SUSPENDED,
172 enum omap_dss_audio_state {
173 OMAP_DSS_AUDIO_DISABLED = 0,
174 OMAP_DSS_AUDIO_ENABLED,
175 OMAP_DSS_AUDIO_CONFIGURED,
176 OMAP_DSS_AUDIO_PLAYING,
179 enum omap_dss_rotation_type {
180 OMAP_DSS_ROT_DMA = 1 << 0,
181 OMAP_DSS_ROT_VRFB = 1 << 1,
182 OMAP_DSS_ROT_TILER = 1 << 2,
185 /* clockwise rotation angle */
186 enum omap_dss_rotation_angle {
189 OMAP_DSS_ROT_180 = 2,
190 OMAP_DSS_ROT_270 = 3,
193 enum omap_overlay_caps {
194 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
195 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
196 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
197 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
200 enum omap_overlay_manager_caps {
201 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
204 enum omap_dss_clk_source {
205 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
207 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
208 * OMAP4: PLL1_CLK1 */
209 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
210 * OMAP4: PLL1_CLK2 */
211 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
212 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
215 enum omap_hdmi_flags {
216 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
221 struct rfbi_timings {
235 u32 tim[5]; /* set by rfbi_convert_timings() */
240 void omap_rfbi_write_command(const void *buf, u32 len);
241 void omap_rfbi_read_data(void *buf, u32 len);
242 void omap_rfbi_write_data(const void *buf, u32 len);
243 void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
246 int omap_rfbi_enable_te(bool enable, unsigned line);
247 int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
248 unsigned hs_pulse_time, unsigned vs_pulse_time,
249 int hs_pol_inv, int vs_pol_inv, int extif_div);
250 void rfbi_bus_lock(void);
251 void rfbi_bus_unlock(void);
255 struct omap_dss_dsi_videomode_data {
256 /* DSI video mode blanking data */
257 /* Unit: byte clock cycles */
261 /* Unit: line clocks */
266 /* DSI blanking modes */
268 int hsa_blanking_mode;
269 int hbp_blanking_mode;
270 int hfp_blanking_mode;
272 /* Video port sync events */
279 bool ddr_clk_always_on;
283 void dsi_bus_lock(struct omap_dss_device *dssdev);
284 void dsi_bus_unlock(struct omap_dss_device *dssdev);
285 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
287 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
289 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd);
290 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel);
291 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
293 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
295 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
296 u8 param1, u8 param2);
297 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
299 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
301 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
302 u8 *buf, int buflen);
303 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
305 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
306 u8 *buf, int buflen);
307 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
308 u8 param1, u8 param2, u8 *buf, int buflen);
309 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
311 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
312 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
313 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel);
314 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel);
316 /* Board specific data */
317 struct omap_dss_board_info {
318 int (*get_context_loss_count)(struct device *dev);
320 struct omap_dss_device **devices;
321 struct omap_dss_device *default_device;
322 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
323 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
324 int (*set_min_bus_tput)(struct device *dev, unsigned long r);
327 /* Init with the board info */
328 extern int omap_display_init(struct omap_dss_board_info *board_data);
330 extern int omap_hdmi_init(enum omap_hdmi_flags flags);
332 struct omap_video_timings {
339 /* Unit: pixel clocks */
340 u16 hsw; /* Horizontal synchronization pulse width */
341 /* Unit: pixel clocks */
342 u16 hfp; /* Horizontal front porch */
343 /* Unit: pixel clocks */
344 u16 hbp; /* Horizontal back porch */
345 /* Unit: line clocks */
346 u16 vsw; /* Vertical synchronization pulse width */
347 /* Unit: line clocks */
348 u16 vfp; /* Vertical front porch */
349 /* Unit: line clocks */
350 u16 vbp; /* Vertical back porch */
352 /* Vsync logic level */
353 enum omap_dss_signal_level vsync_level;
354 /* Hsync logic level */
355 enum omap_dss_signal_level hsync_level;
356 /* Pixel clock edge to drive LCD data */
357 enum omap_dss_signal_edge data_pclk_edge;
358 /* Data enable logic level */
359 enum omap_dss_signal_level de_level;
360 /* Pixel clock edges to drive HSYNC and VSYNC signals */
361 enum omap_dss_signal_edge sync_pclk_edge;
364 #ifdef CONFIG_OMAP2_DSS_VENC
365 /* Hardcoded timings for tv modes. Venc only uses these to
366 * identify the mode, and does not actually use the configs
367 * itself. However, the configs should be something that
368 * a normal monitor can also show */
369 extern const struct omap_video_timings omap_dss_pal_timings;
370 extern const struct omap_video_timings omap_dss_ntsc_timings;
373 struct omap_dss_cpr_coefs {
379 struct omap_overlay_info {
381 u32 p_uv_addr; /* for NV12 format */
385 enum omap_color_mode color_mode;
387 enum omap_dss_rotation_type rotation_type;
392 u16 out_width; /* if 0, out_width == width */
393 u16 out_height; /* if 0, out_height == height */
399 struct omap_overlay {
401 struct list_head list;
406 enum omap_color_mode supported_modes;
407 enum omap_overlay_caps caps;
410 struct omap_overlay_manager *manager;
413 * The following functions do not block:
419 * The rest of the functions may block and cannot be called from
423 int (*enable)(struct omap_overlay *ovl);
424 int (*disable)(struct omap_overlay *ovl);
425 bool (*is_enabled)(struct omap_overlay *ovl);
427 int (*set_manager)(struct omap_overlay *ovl,
428 struct omap_overlay_manager *mgr);
429 int (*unset_manager)(struct omap_overlay *ovl);
431 int (*set_overlay_info)(struct omap_overlay *ovl,
432 struct omap_overlay_info *info);
433 void (*get_overlay_info)(struct omap_overlay *ovl,
434 struct omap_overlay_info *info);
436 int (*wait_for_go)(struct omap_overlay *ovl);
439 struct omap_overlay_manager_info {
442 enum omap_dss_trans_key_type trans_key_type;
446 bool partial_alpha_enabled;
449 struct omap_dss_cpr_coefs cpr_coefs;
452 struct omap_overlay_manager {
457 enum omap_channel id;
458 enum omap_overlay_manager_caps caps;
459 struct list_head overlays;
460 enum omap_display_type supported_displays;
463 struct omap_dss_device *device;
466 * The following functions do not block:
472 * The rest of the functions may block and cannot be called from
476 int (*set_device)(struct omap_overlay_manager *mgr,
477 struct omap_dss_device *dssdev);
478 int (*unset_device)(struct omap_overlay_manager *mgr);
480 int (*set_manager_info)(struct omap_overlay_manager *mgr,
481 struct omap_overlay_manager_info *info);
482 void (*get_manager_info)(struct omap_overlay_manager *mgr,
483 struct omap_overlay_manager_info *info);
485 int (*apply)(struct omap_overlay_manager *mgr);
486 int (*wait_for_go)(struct omap_overlay_manager *mgr);
487 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
490 /* 22 pins means 1 clk lane and 10 data lanes */
491 #define OMAP_DSS_MAX_DSI_PINS 22
493 struct omap_dsi_pin_config {
496 * pin numbers in the following order:
502 int pins[OMAP_DSS_MAX_DSI_PINS];
505 struct omap_dss_device {
508 enum omap_display_type type;
510 enum omap_channel channel;
534 enum omap_dss_venc_type type;
535 bool invert_polarity;
544 enum omap_dss_clk_source lcd_clk_src;
547 enum omap_dss_clk_source dispc_fclk_src;
551 /* regn is one greater than TRM's REGN value */
558 enum omap_dss_clk_source dsi_fclk_src;
562 /* regn is one greater than TRM's REGN value */
569 struct omap_video_timings timings;
571 int acbi; /* ac-bias pin transitions per interrupt */
572 /* Unit: line clocks */
573 int acb; /* ac-bias pin frequency */
575 enum omap_panel_config config;
577 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
578 enum omap_dss_dsi_mode dsi_mode;
579 struct omap_dss_dsi_videomode_data dsi_vm_data;
584 struct rfbi_timings rfbi_timings;
589 int max_backlight_level;
593 /* used to match device to driver */
594 const char *driver_name;
598 struct omap_dss_driver *driver;
600 /* helper variable for driver suspend/resume */
601 bool activate_after_resume;
603 enum omap_display_caps caps;
605 struct omap_overlay_manager *manager;
607 enum omap_dss_display_state state;
609 enum omap_dss_audio_state audio_state;
611 /* platform specific */
612 int (*platform_enable)(struct omap_dss_device *dssdev);
613 void (*platform_disable)(struct omap_dss_device *dssdev);
614 int (*set_backlight)(struct omap_dss_device *dssdev, int level);
615 int (*get_backlight)(struct omap_dss_device *dssdev);
618 struct omap_dss_hdmi_data
623 struct omap_dss_audio {
624 struct snd_aes_iec958 *iec;
625 struct snd_cea_861_aud_if *cea;
628 struct omap_dss_driver {
629 struct device_driver driver;
631 int (*probe)(struct omap_dss_device *);
632 void (*remove)(struct omap_dss_device *);
634 int (*enable)(struct omap_dss_device *display);
635 void (*disable)(struct omap_dss_device *display);
636 int (*suspend)(struct omap_dss_device *display);
637 int (*resume)(struct omap_dss_device *display);
638 int (*run_test)(struct omap_dss_device *display, int test);
640 int (*update)(struct omap_dss_device *dssdev,
641 u16 x, u16 y, u16 w, u16 h);
642 int (*sync)(struct omap_dss_device *dssdev);
644 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
645 int (*get_te)(struct omap_dss_device *dssdev);
647 u8 (*get_rotate)(struct omap_dss_device *dssdev);
648 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
650 bool (*get_mirror)(struct omap_dss_device *dssdev);
651 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
653 int (*memory_read)(struct omap_dss_device *dssdev,
654 void *buf, size_t size,
655 u16 x, u16 y, u16 w, u16 h);
657 void (*get_resolution)(struct omap_dss_device *dssdev,
658 u16 *xres, u16 *yres);
659 void (*get_dimensions)(struct omap_dss_device *dssdev,
660 u32 *width, u32 *height);
661 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
663 int (*check_timings)(struct omap_dss_device *dssdev,
664 struct omap_video_timings *timings);
665 void (*set_timings)(struct omap_dss_device *dssdev,
666 struct omap_video_timings *timings);
667 void (*get_timings)(struct omap_dss_device *dssdev,
668 struct omap_video_timings *timings);
670 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
671 u32 (*get_wss)(struct omap_dss_device *dssdev);
673 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
674 bool (*detect)(struct omap_dss_device *dssdev);
677 * For display drivers that support audio. This encompasses
678 * HDMI and DisplayPort at the moment.
681 * Note: These functions might sleep. Do not call while
682 * holding a spinlock/readlock.
684 int (*audio_enable)(struct omap_dss_device *dssdev);
685 void (*audio_disable)(struct omap_dss_device *dssdev);
686 bool (*audio_supported)(struct omap_dss_device *dssdev);
687 int (*audio_config)(struct omap_dss_device *dssdev,
688 struct omap_dss_audio *audio);
689 /* Note: These functions may not sleep */
690 int (*audio_start)(struct omap_dss_device *dssdev);
691 void (*audio_stop)(struct omap_dss_device *dssdev);
695 int omap_dss_register_driver(struct omap_dss_driver *);
696 void omap_dss_unregister_driver(struct omap_dss_driver *);
698 void omap_dss_get_device(struct omap_dss_device *dssdev);
699 void omap_dss_put_device(struct omap_dss_device *dssdev);
700 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
701 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
702 struct omap_dss_device *omap_dss_find_device(void *data,
703 int (*match)(struct omap_dss_device *dssdev, void *data));
705 int omap_dss_start_device(struct omap_dss_device *dssdev);
706 void omap_dss_stop_device(struct omap_dss_device *dssdev);
708 int omap_dss_get_num_overlay_managers(void);
709 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
711 int omap_dss_get_num_overlays(void);
712 struct omap_overlay *omap_dss_get_overlay(int num);
714 void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
715 u16 *xres, u16 *yres);
716 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
717 void omapdss_default_get_timings(struct omap_dss_device *dssdev,
718 struct omap_video_timings *timings);
720 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
721 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
722 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
724 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
725 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
726 unsigned long timeout);
728 #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
729 #define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
731 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
733 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
735 int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
736 void (*callback)(int, void *), void *data);
737 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
738 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
739 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
740 int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
741 const struct omap_dsi_pin_config *pin_cfg);
743 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
744 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
745 bool disconnect_lanes, bool enter_ulps);
747 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
748 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
749 void dpi_set_timings(struct omap_dss_device *dssdev,
750 struct omap_video_timings *timings);
751 int dpi_check_timings(struct omap_dss_device *dssdev,
752 struct omap_video_timings *timings);
754 int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
755 void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
757 int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
758 void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
759 int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
760 u16 *x, u16 *y, u16 *w, u16 *h);
761 int omap_rfbi_update(struct omap_dss_device *dssdev,
762 u16 x, u16 y, u16 w, u16 h,
763 void (*callback)(void *), void *data);
764 int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,