1 /******************************************************************************
4 * Guest OS interface to Xen.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the
9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10 * sell copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
24 * Copyright (c) 2004, K A Fraser
27 #ifndef __XEN_PUBLIC_XEN_H__
28 #define __XEN_PUBLIC_XEN_H__
30 #include <asm/xen/interface.h>
33 * XEN "SYSTEM CALLS" (a.k.a. HYPERCALLS).
37 * x86_32: EAX = vector; EBX, ECX, EDX, ESI, EDI = args 1, 2, 3, 4, 5.
39 * (argument registers may be clobbered on return)
40 * x86_64: RAX = vector; RDI, RSI, RDX, R10, R8, R9 = args 1, 2, 3, 4, 5, 6.
42 * (argument registers not clobbered on return; RCX, R11 are)
44 #define __HYPERVISOR_set_trap_table 0
45 #define __HYPERVISOR_mmu_update 1
46 #define __HYPERVISOR_set_gdt 2
47 #define __HYPERVISOR_stack_switch 3
48 #define __HYPERVISOR_set_callbacks 4
49 #define __HYPERVISOR_fpu_taskswitch 5
50 #define __HYPERVISOR_sched_op_compat 6
51 #define __HYPERVISOR_dom0_op 7
52 #define __HYPERVISOR_set_debugreg 8
53 #define __HYPERVISOR_get_debugreg 9
54 #define __HYPERVISOR_update_descriptor 10
55 #define __HYPERVISOR_memory_op 12
56 #define __HYPERVISOR_multicall 13
57 #define __HYPERVISOR_update_va_mapping 14
58 #define __HYPERVISOR_set_timer_op 15
59 #define __HYPERVISOR_event_channel_op_compat 16
60 #define __HYPERVISOR_xen_version 17
61 #define __HYPERVISOR_console_io 18
62 #define __HYPERVISOR_physdev_op_compat 19
63 #define __HYPERVISOR_grant_table_op 20
64 #define __HYPERVISOR_vm_assist 21
65 #define __HYPERVISOR_update_va_mapping_otherdomain 22
66 #define __HYPERVISOR_iret 23 /* x86 only */
67 #define __HYPERVISOR_vcpu_op 24
68 #define __HYPERVISOR_set_segment_base 25 /* x86/64 only */
69 #define __HYPERVISOR_mmuext_op 26
70 #define __HYPERVISOR_acm_op 27
71 #define __HYPERVISOR_nmi_op 28
72 #define __HYPERVISOR_sched_op 29
73 #define __HYPERVISOR_callback_op 30
74 #define __HYPERVISOR_xenoprof_op 31
75 #define __HYPERVISOR_event_channel_op 32
76 #define __HYPERVISOR_physdev_op 33
77 #define __HYPERVISOR_hvm_op 34
78 #define __HYPERVISOR_tmem_op 38
80 /* Architecture-specific hypercall definitions. */
81 #define __HYPERVISOR_arch_0 48
82 #define __HYPERVISOR_arch_1 49
83 #define __HYPERVISOR_arch_2 50
84 #define __HYPERVISOR_arch_3 51
85 #define __HYPERVISOR_arch_4 52
86 #define __HYPERVISOR_arch_5 53
87 #define __HYPERVISOR_arch_6 54
88 #define __HYPERVISOR_arch_7 55
93 * Virtual interrupts that a guest OS may receive from Xen.
94 * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a
95 * global VIRQ. The former can be bound once per VCPU and cannot be re-bound.
96 * The latter can be allocated only once per guest: they must initially be
97 * allocated to VCPU0 but can subsequently be re-bound.
99 #define VIRQ_TIMER 0 /* V. Timebase update, and/or requested timeout. */
100 #define VIRQ_DEBUG 1 /* V. Request guest to dump debug info. */
101 #define VIRQ_CONSOLE 2 /* G. (DOM0) Bytes received on emergency console. */
102 #define VIRQ_DOM_EXC 3 /* G. (DOM0) Exceptional event for some domain. */
103 #define VIRQ_TBUF 4 /* G. (DOM0) Trace buffer has records available. */
104 #define VIRQ_DEBUGGER 6 /* G. (DOM0) A domain has paused for debugging. */
105 #define VIRQ_XENOPROF 7 /* V. XenOprofile interrupt: new sample available */
106 #define VIRQ_CON_RING 8 /* G. (DOM0) Bytes received on console */
107 #define VIRQ_PCPU_STATE 9 /* G. (DOM0) PCPU state changed */
108 #define VIRQ_MEM_EVENT 10 /* G. (DOM0) A memory event has occured */
109 #define VIRQ_XC_RESERVED 11 /* G. Reserved for XenClient */
110 #define VIRQ_ENOMEM 12 /* G. (DOM0) Low on heap memory */
112 /* Architecture-specific VIRQ definitions. */
113 #define VIRQ_ARCH_0 16
114 #define VIRQ_ARCH_1 17
115 #define VIRQ_ARCH_2 18
116 #define VIRQ_ARCH_3 19
117 #define VIRQ_ARCH_4 20
118 #define VIRQ_ARCH_5 21
119 #define VIRQ_ARCH_6 22
120 #define VIRQ_ARCH_7 23
125 * enum neg_errnoval HYPERVISOR_mmu_update(const struct mmu_update reqs[],
126 * unsigned count, unsigned *done_out,
127 * unsigned foreigndom)
128 * @reqs is an array of mmu_update_t structures ((ptr, val) pairs).
129 * @count is the length of the above array.
130 * @pdone is an output parameter indicating number of completed operations
131 * @foreigndom[15:0]: FD, the expected owner of data pages referenced in this
132 * hypercall invocation. Can be DOMID_SELF.
133 * @foreigndom[31:16]: PFD, the expected owner of pagetable pages referenced
134 * in this hypercall invocation. The value of this field
135 * (x) encodes the PFD as follows:
136 * x == 0 => PFD == DOMID_SELF
137 * x != 0 => PFD == x - 1
139 * Sub-commands: ptr[1:0] specifies the appropriate MMU_* command.
141 * ptr[1:0] == MMU_NORMAL_PT_UPDATE:
142 * Updates an entry in a page table belonging to PFD. If updating an L1 table,
143 * and the new table entry is valid/present, the mapped frame must belong to
144 * FD. If attempting to map an I/O page then the caller assumes the privilege
146 * FD == DOMID_IO: Permit /only/ I/O mappings, at the priv level of the caller.
147 * FD == DOMID_XEN: Map restricted areas of Xen's heap space.
148 * ptr[:2] -- Machine address of the page-table entry to modify.
149 * val -- Value to write.
151 * There also certain implicit requirements when using this hypercall. The
152 * pages that make up a pagetable must be mapped read-only in the guest.
153 * This prevents uncontrolled guest updates to the pagetable. Xen strictly
154 * enforces this, and will disallow any pagetable update which will end up
155 * mapping pagetable page RW, and will disallow using any writable page as a
156 * pagetable. In practice it means that when constructing a page table for a
157 * process, thread, etc, we MUST be very dilligient in following these rules:
158 * 1). Start with top-level page (PGD or in Xen language: L4). Fill out
160 * 2). Keep on going, filling out the upper (PUD or L3), and middle (PMD
162 * 3). Start filling out the PTE table (L1) with the PTE entries. Once
163 * done, make sure to set each of those entries to RO (so writeable bit
164 * is unset). Once that has been completed, set the PMD (L2) for this
166 * 4). When completed with all of the PMD (L2) entries, and all of them have
167 * been set to RO, make sure to set RO the PUD (L3). Do the same
168 * operation on PGD (L4) pagetable entries that have a PUD (L3) entry.
169 * 5). Now before you can use those pages (so setting the cr3), you MUST also
170 * pin them so that the hypervisor can verify the entries. This is done
171 * via the HYPERVISOR_mmuext_op(MMUEXT_PIN_L4_TABLE, guest physical frame
172 * number of the PGD (L4)). And this point the HYPERVISOR_mmuext_op(
173 * MMUEXT_NEW_BASEPTR, guest physical frame number of the PGD (L4)) can be
175 * For 32-bit guests, the L4 is not used (as there is less pagetables), so
177 * At this point the pagetables can be modified using the MMU_NORMAL_PT_UPDATE
178 * hypercall. Also if so desired the OS can also try to write to the PTE
179 * and be trapped by the hypervisor (as the PTE entry is RO).
181 * To deallocate the pages, the operations are the reverse of the steps
182 * mentioned above. The argument is MMUEXT_UNPIN_TABLE for all levels and the
183 * pagetable MUST not be in use (meaning that the cr3 is not set to it).
185 * ptr[1:0] == MMU_MACHPHYS_UPDATE:
186 * Updates an entry in the machine->pseudo-physical mapping table.
187 * ptr[:2] -- Machine address within the frame whose mapping to modify.
188 * The frame must belong to the FD, if one is specified.
189 * val -- Value to write into the mapping entry.
191 * ptr[1:0] == MMU_PT_UPDATE_PRESERVE_AD:
192 * As MMU_NORMAL_PT_UPDATE above, but A/D bits currently in the PTE are ORed
193 * with those in @val.
195 * @val is usually the machine frame number along with some attributes.
196 * The attributes by default follow the architecture defined bits. Meaning that
197 * if this is a X86_64 machine and four page table layout is used, the layout
199 * - 63 if set means No execute (NX)
200 * - 46-13 the machine frame number
201 * - 12 available for guest
202 * - 11 available for guest
203 * - 10 available for guest
204 * - 9 available for guest
206 * - 7 PAT (PSE is disabled, must use hypercall to make 4MB or 2MB pages)
209 * - 4 page cached disabled
210 * - 3 page write through
211 * - 2 userspace accessible
215 * The one bits that does not fit with the default layout is the PAGE_PSE
216 * also called PAGE_PAT). The MMUEXT_[UN]MARK_SUPER arguments to the
217 * HYPERVISOR_mmuext_op serve as mechanism to set a pagetable to be 4MB
218 * (or 2MB) instead of using the PAGE_PSE bit.
220 * The reason that the PAGE_PSE (bit 7) is not being utilized is due to Xen
221 * using it as the Page Attribute Table (PAT) bit - for details on it please
222 * refer to Intel SDM 10.12. The PAT allows to set the caching attributes of
223 * pages instead of using MTRRs.
225 * The PAT MSR is as follows (it is a 64-bit value, each entry is 8 bits):
227 * +-----+-----+----+----+----+-----+----+----+
228 * | UC | UC- | WC | WB | UC | UC- | WC | WB | <= Linux
229 * +-----+-----+----+----+----+-----+----+----+
230 * | UC | UC- | WT | WB | UC | UC- | WT | WB | <= BIOS (default when machine boots)
231 * +-----+-----+----+----+----+-----+----+----+
232 * | rsv | rsv | WP | WC | UC | UC- | WT | WB | <= Xen
233 * +-----+-----+----+----+----+-----+----+----+
235 * The lookup of this index table translates to looking up
236 * Bit 7, Bit 4, and Bit 3 of val entry:
238 * PAT/PSE (bit 7) ... PCD (bit 4) .. PWT (bit 3).
240 * If all bits are off, then we are using PAT0. If bit 3 turned on,
241 * then we are using PAT1, if bit 3 and bit 4, then PAT2..
243 * As you can see, the Linux PAT1 translates to PAT4 under Xen. Which means
244 * that if a guest that follows Linux's PAT setup and would like to set Write
245 * Combined on pages it MUST use PAT4 entry. Meaning that Bit 7 (PAGE_PAT) is
246 * set. For example, under Linux it only uses PAT0, PAT1, and PAT2 for the
249 * WB = none (so PAT0)
250 * WC = PWT (bit 3 on)
251 * UC = PWT | PCD (bit 3 and 4 are on).
253 * To make it work with Xen, it needs to translate the WC bit as so:
255 * PWT (so bit 3 on) --> PAT (so bit 7 is on) and clear bit 3
257 * And to translate back it would:
259 * PAT (bit 7 on) --> PWT (bit 3 on) and clear bit 7.
261 #define MMU_NORMAL_PT_UPDATE 0 /* checked '*ptr = val'. ptr is MA. */
262 #define MMU_MACHPHYS_UPDATE 1 /* ptr = MA of frame to modify entry for */
263 #define MMU_PT_UPDATE_PRESERVE_AD 2 /* atomically: *ptr = val | (*ptr&(A|D)) */
266 * MMU EXTENDED OPERATIONS
268 * enum neg_errnoval HYPERVISOR_mmuext_op(mmuext_op_t uops[],
269 * unsigned int count,
270 * unsigned int *pdone,
271 * unsigned int foreigndom)
273 /* HYPERVISOR_mmuext_op() accepts a list of mmuext_op structures.
274 * A foreigndom (FD) can be specified (or DOMID_SELF for none).
275 * Where the FD has some effect, it is described below.
277 * cmd: MMUEXT_(UN)PIN_*_TABLE
278 * mfn: Machine frame number to be (un)pinned as a p.t. page.
279 * The frame must belong to the FD, if one is specified.
281 * cmd: MMUEXT_NEW_BASEPTR
282 * mfn: Machine frame number of new page-table base to install in MMU.
284 * cmd: MMUEXT_NEW_USER_BASEPTR [x86/64 only]
285 * mfn: Machine frame number of new page-table base to install in MMU
286 * when in user space.
288 * cmd: MMUEXT_TLB_FLUSH_LOCAL
289 * No additional arguments. Flushes local TLB.
291 * cmd: MMUEXT_INVLPG_LOCAL
292 * linear_addr: Linear address to be flushed from the local TLB.
294 * cmd: MMUEXT_TLB_FLUSH_MULTI
295 * vcpumask: Pointer to bitmap of VCPUs to be flushed.
297 * cmd: MMUEXT_INVLPG_MULTI
298 * linear_addr: Linear address to be flushed.
299 * vcpumask: Pointer to bitmap of VCPUs to be flushed.
301 * cmd: MMUEXT_TLB_FLUSH_ALL
302 * No additional arguments. Flushes all VCPUs' TLBs.
304 * cmd: MMUEXT_INVLPG_ALL
305 * linear_addr: Linear address to be flushed from all VCPUs' TLBs.
307 * cmd: MMUEXT_FLUSH_CACHE
308 * No additional arguments. Writes back and flushes cache contents.
310 * cmd: MMUEXT_FLUSH_CACHE_GLOBAL
311 * No additional arguments. Writes back and flushes cache contents
312 * on all CPUs in the system.
314 * cmd: MMUEXT_SET_LDT
315 * linear_addr: Linear address of LDT base (NB. must be page-aligned).
316 * nr_ents: Number of entries in LDT.
318 * cmd: MMUEXT_CLEAR_PAGE
319 * mfn: Machine frame number to be cleared.
321 * cmd: MMUEXT_COPY_PAGE
322 * mfn: Machine frame number of the destination page.
323 * src_mfn: Machine frame number of the source page.
325 * cmd: MMUEXT_[UN]MARK_SUPER
326 * mfn: Machine frame number of head of superpage to be [un]marked.
328 #define MMUEXT_PIN_L1_TABLE 0
329 #define MMUEXT_PIN_L2_TABLE 1
330 #define MMUEXT_PIN_L3_TABLE 2
331 #define MMUEXT_PIN_L4_TABLE 3
332 #define MMUEXT_UNPIN_TABLE 4
333 #define MMUEXT_NEW_BASEPTR 5
334 #define MMUEXT_TLB_FLUSH_LOCAL 6
335 #define MMUEXT_INVLPG_LOCAL 7
336 #define MMUEXT_TLB_FLUSH_MULTI 8
337 #define MMUEXT_INVLPG_MULTI 9
338 #define MMUEXT_TLB_FLUSH_ALL 10
339 #define MMUEXT_INVLPG_ALL 11
340 #define MMUEXT_FLUSH_CACHE 12
341 #define MMUEXT_SET_LDT 13
342 #define MMUEXT_NEW_USER_BASEPTR 15
343 #define MMUEXT_CLEAR_PAGE 16
344 #define MMUEXT_COPY_PAGE 17
345 #define MMUEXT_FLUSH_CACHE_GLOBAL 18
346 #define MMUEXT_MARK_SUPER 19
347 #define MMUEXT_UNMARK_SUPER 20
353 /* [UN]PIN_TABLE, NEW_BASEPTR, NEW_USER_BASEPTR
354 * CLEAR_PAGE, COPY_PAGE, [UN]MARK_SUPER */
356 /* INVLPG_LOCAL, INVLPG_ALL, SET_LDT */
357 unsigned long linear_addr;
361 unsigned int nr_ents;
362 /* TLB_FLUSH_MULTI, INVLPG_MULTI */
368 DEFINE_GUEST_HANDLE_STRUCT(mmuext_op);
371 /* These are passed as 'flags' to update_va_mapping. They can be ORed. */
372 /* When specifying UVMF_MULTI, also OR in a pointer to a CPU bitmap. */
373 /* UVMF_LOCAL is merely UVMF_MULTI with a NULL bitmap pointer. */
374 #define UVMF_NONE (0UL<<0) /* No flushing at all. */
375 #define UVMF_TLB_FLUSH (1UL<<0) /* Flush entire TLB(s). */
376 #define UVMF_INVLPG (2UL<<0) /* Flush only one entry. */
377 #define UVMF_FLUSHTYPE_MASK (3UL<<0)
378 #define UVMF_MULTI (0UL<<2) /* Flush subset of TLBs. */
379 #define UVMF_LOCAL (0UL<<2) /* Flush local TLB. */
380 #define UVMF_ALL (1UL<<2) /* Flush all TLBs. */
383 * Commands to HYPERVISOR_console_io().
385 #define CONSOLEIO_write 0
386 #define CONSOLEIO_read 1
389 * Commands to HYPERVISOR_vm_assist().
391 #define VMASST_CMD_enable 0
392 #define VMASST_CMD_disable 1
394 /* x86/32 guests: simulate full 4GB segment limits. */
395 #define VMASST_TYPE_4gb_segments 0
397 /* x86/32 guests: trap (vector 15) whenever above vmassist is used. */
398 #define VMASST_TYPE_4gb_segments_notify 1
401 * x86 guests: support writes to bottom-level PTEs.
402 * NB1. Page-directory entries cannot be written.
403 * NB2. Guest must continue to remove all writable mappings of PTEs.
405 #define VMASST_TYPE_writable_pagetables 2
407 /* x86/PAE guests: support PDPTs above 4GB. */
408 #define VMASST_TYPE_pae_extended_cr3 3
410 #define MAX_VMASST_TYPE 3
414 typedef uint16_t domid_t;
416 /* Domain ids >= DOMID_FIRST_RESERVED cannot be used for ordinary domains. */
417 #define DOMID_FIRST_RESERVED (0x7FF0U)
419 /* DOMID_SELF is used in certain contexts to refer to oneself. */
420 #define DOMID_SELF (0x7FF0U)
423 * DOMID_IO is used to restrict page-table updates to mapping I/O memory.
424 * Although no Foreign Domain need be specified to map I/O pages, DOMID_IO
425 * is useful to ensure that no mappings to the OS's own heap are accidentally
426 * installed. (e.g., in Linux this could cause havoc as reference counts
427 * aren't adjusted on the I/O-mapping code path).
428 * This only makes sense in MMUEXT_SET_FOREIGNDOM, but in that context can
429 * be specified by any calling domain.
431 #define DOMID_IO (0x7FF1U)
434 * DOMID_XEN is used to allow privileged domains to map restricted parts of
435 * Xen's heap space (e.g., the machine_to_phys table).
436 * This only makes sense in MMUEXT_SET_FOREIGNDOM, and is only permitted if
437 * the caller is privileged.
439 #define DOMID_XEN (0x7FF2U)
441 /* DOMID_COW is used as the owner of sharable pages */
442 #define DOMID_COW (0x7FF3U)
444 /* DOMID_INVALID is used to identify pages with unknown owner. */
445 #define DOMID_INVALID (0x7FF4U)
448 #define DOMID_IDLE (0x7FFFU)
451 * Send an array of these to HYPERVISOR_mmu_update().
452 * NB. The fields are natural pointer/address size for this architecture.
455 uint64_t ptr; /* Machine address of PTE. */
456 uint64_t val; /* New contents of PTE. */
458 DEFINE_GUEST_HANDLE_STRUCT(mmu_update);
461 * Send an array of these to HYPERVISOR_multicall().
462 * NB. The fields are logically the natural register size for this
463 * architecture. In cases where xen_ulong_t is larger than this then
464 * any unused bits in the upper portion must be zero.
466 struct multicall_entry {
471 DEFINE_GUEST_HANDLE_STRUCT(multicall_entry);
473 struct vcpu_time_info {
475 * Updates to the following values are preceded and followed
476 * by an increment of 'version'. The guest can therefore
477 * detect updates by looking for changes to 'version'. If the
478 * least-significant bit of the version number is set then an
479 * update is in progress and the guest must wait to read a
480 * consistent set of values. The correct way to interact with
481 * the version number is similar to Linux's seqlock: see the
482 * implementations of read_seqbegin/read_seqretry.
486 uint64_t tsc_timestamp; /* TSC at last update of time vals. */
487 uint64_t system_time; /* Time, in nanosecs, since boot. */
489 * Current system time:
490 * system_time + ((tsc - tsc_timestamp) << tsc_shift) * tsc_to_system_mul
491 * CPU frequency (Hz):
492 * ((10^9 << 32) / tsc_to_system_mul) >> tsc_shift
494 uint32_t tsc_to_system_mul;
501 * 'evtchn_upcall_pending' is written non-zero by Xen to indicate
502 * a pending notification for a particular VCPU. It is then cleared
503 * by the guest OS /before/ checking for pending work, thus avoiding
504 * a set-and-check race. Note that the mask is only accessed by Xen
505 * on the CPU that is currently hosting the VCPU. This means that the
506 * pending and mask flags can be updated by the guest without special
507 * synchronisation (i.e., no need for the x86 LOCK prefix).
508 * This may seem suboptimal because if the pending flag is set by
509 * a different CPU then an IPI may be scheduled even when the mask
510 * is set. However, note:
511 * 1. The task of 'interrupt holdoff' is covered by the per-event-
512 * channel mask bits. A 'noisy' event that is continually being
513 * triggered can be masked at source at this very precise
515 * 2. The main purpose of the per-VCPU mask is therefore to restrict
516 * reentrant execution: whether for concurrency control, or to
517 * prevent unbounded stack usage. Whatever the purpose, we expect
518 * that the mask will be asserted only for short periods at a time,
519 * and so the likelihood of a 'spurious' IPI is suitably small.
520 * The mask is read before making an event upcall to the guest: a
521 * non-zero mask therefore guarantees that the VCPU will not receive
522 * an upcall activation. The mask is cleared when the VCPU requests
523 * to block: this avoids wakeup-waiting races.
525 uint8_t evtchn_upcall_pending;
526 uint8_t evtchn_upcall_mask;
527 xen_ulong_t evtchn_pending_sel;
528 struct arch_vcpu_info arch;
529 struct pvclock_vcpu_time_info time;
530 }; /* 64 bytes (x86) */
533 * Xen/kernel shared data -- pointer provided in start_info.
534 * NB. We expect that this struct is smaller than a page.
537 struct vcpu_info vcpu_info[MAX_VIRT_CPUS];
540 * A domain can create "event channels" on which it can send and receive
541 * asynchronous event notifications. There are three classes of event that
542 * are delivered by this mechanism:
543 * 1. Bi-directional inter- and intra-domain connections. Domains must
544 * arrange out-of-band to set up a connection (usually by allocating
545 * an unbound 'listener' port and avertising that via a storage service
547 * 2. Physical interrupts. A domain with suitable hardware-access
548 * privileges can bind an event-channel port to a physical interrupt
550 * 3. Virtual interrupts ('events'). A domain can bind an event-channel
551 * port to a virtual interrupt source, such as the virtual-timer
552 * device or the emergency console.
554 * Event channels are addressed by a "port index". Each channel is
555 * associated with two bits of information:
556 * 1. PENDING -- notifies the domain that there is a pending notification
557 * to be processed. This bit is cleared by the guest.
558 * 2. MASK -- if this bit is clear then a 0->1 transition of PENDING
559 * will cause an asynchronous upcall to be scheduled. This bit is only
560 * updated by the guest. It is read-only within Xen. If a channel
561 * becomes pending while the channel is masked then the 'edge' is lost
562 * (i.e., when the channel is unmasked, the guest must manually handle
563 * pending notifications as no upcall will be scheduled by Xen).
565 * To expedite scanning of pending notifications, any 0->1 pending
566 * transition on an unmasked channel causes a corresponding bit in a
567 * per-vcpu selector word to be set. Each bit in the selector covers a
568 * 'C long' in the PENDING bitfield array.
570 xen_ulong_t evtchn_pending[sizeof(xen_ulong_t) * 8];
571 xen_ulong_t evtchn_mask[sizeof(xen_ulong_t) * 8];
574 * Wallclock time: updated only by control software. Guests should base
575 * their gettimeofday() syscall on this wallclock-base value.
577 struct pvclock_wall_clock wc;
579 struct arch_shared_info arch;
584 * Start-of-day memory layout for the initial domain (DOM0):
585 * 1. The domain is started within contiguous virtual-memory region.
586 * 2. The contiguous region begins and ends on an aligned 4MB boundary.
587 * 3. The region start corresponds to the load address of the OS image.
588 * If the load address is not 4MB aligned then the address is rounded down.
589 * 4. This the order of bootstrap elements in the initial virtual region:
590 * a. relocated kernel image
591 * b. initial ram disk [mod_start, mod_len]
592 * c. list of allocated page frames [mfn_list, nr_pages]
593 * d. start_info_t structure [register ESI (x86)]
594 * e. bootstrap page tables [pt_base, CR3 (x86)]
595 * f. bootstrap stack [register ESP (x86)]
596 * 5. Bootstrap elements are packed together, but each is 4kB-aligned.
597 * 6. The initial ram disk may be omitted.
598 * 7. The list of page frames forms a contiguous 'pseudo-physical' memory
599 * layout for the domain. In particular, the bootstrap virtual-memory
600 * region is a 1:1 mapping to the first section of the pseudo-physical map.
601 * 8. All bootstrap elements are mapped read-writable for the guest OS. The
602 * only exception is the bootstrap page table, which is mapped read-only.
603 * 9. There is guaranteed to be at least 512kB padding after the final
604 * bootstrap element. If necessary, the bootstrap virtual region is
605 * extended by an extra 4MB to ensure this.
608 #define MAX_GUEST_CMDLINE 1024
610 /* THE FOLLOWING ARE FILLED IN BOTH ON INITIAL BOOT AND ON RESUME. */
611 char magic[32]; /* "xen-<version>-<platform>". */
612 unsigned long nr_pages; /* Total pages allocated to this domain. */
613 unsigned long shared_info; /* MACHINE address of shared info struct. */
614 uint32_t flags; /* SIF_xxx flags. */
615 xen_pfn_t store_mfn; /* MACHINE page number of shared page. */
616 uint32_t store_evtchn; /* Event channel for store communication. */
619 xen_pfn_t mfn; /* MACHINE page number of console page. */
620 uint32_t evtchn; /* Event channel for console page. */
623 uint32_t info_off; /* Offset of console_info struct. */
624 uint32_t info_size; /* Size of console_info struct from start.*/
627 /* THE FOLLOWING ARE ONLY FILLED IN ON INITIAL BOOT (NOT RESUME). */
628 unsigned long pt_base; /* VIRTUAL address of page directory. */
629 unsigned long nr_pt_frames; /* Number of bootstrap p.t. frames. */
630 unsigned long mfn_list; /* VIRTUAL address of page-frame list. */
631 unsigned long mod_start; /* VIRTUAL address of pre-loaded module. */
632 unsigned long mod_len; /* Size (bytes) of pre-loaded module. */
633 int8_t cmd_line[MAX_GUEST_CMDLINE];
634 /* The pfn range here covers both page table and p->m table frames. */
635 unsigned long first_p2m_pfn;/* 1st pfn forming initial P->M table. */
636 unsigned long nr_p2m_frames;/* # of pfns forming initial P->M table. */
639 /* These flags are passed in the 'flags' field of start_info_t. */
640 #define SIF_PRIVILEGED (1<<0) /* Is the domain privileged? */
641 #define SIF_INITDOMAIN (1<<1) /* Is this the initial control domain? */
642 #define SIF_MULTIBOOT_MOD (1<<2) /* Is mod_start a multiboot module? */
643 #define SIF_MOD_START_PFN (1<<3) /* Is mod_start a PFN? */
644 #define SIF_PM_MASK (0xFF<<8) /* reserve 1 byte for xen-pm options */
647 * A multiboot module is a package containing modules very similar to a
648 * multiboot module array. The only differences are:
649 * - the array of module descriptors is by convention simply at the beginning
650 * of the multiboot module,
651 * - addresses in the module descriptors are based on the beginning of the
653 * - the number of modules is determined by a termination descriptor that has
656 * This permits to both build it statically and reference it in a configuration
657 * file, and let the PV guest easily rebase the addresses to virtual addresses
658 * and at the same time count the number of modules.
660 struct xen_multiboot_mod_list {
661 /* Address of first byte of the module */
663 /* Address of last byte of the module (inclusive) */
665 /* Address of zero-terminated command line */
667 /* Unused, must be zero */
671 * The console structure in start_info.console.dom0
673 * This structure includes a variety of information required to
674 * have a working VGA/VESA console.
676 struct dom0_vga_console_info {
678 #define XEN_VGATYPE_TEXT_MODE_3 0x03
679 #define XEN_VGATYPE_VESA_LFB 0x23
680 #define XEN_VGATYPE_EFI_LFB 0x70
684 /* Font height, in pixels. */
685 uint16_t font_height;
686 /* Cursor location (column, row). */
687 uint16_t cursor_x, cursor_y;
688 /* Number of rows and columns (dimensions in characters). */
689 uint16_t rows, columns;
693 /* Width and height, in pixels. */
694 uint16_t width, height;
695 /* Bytes per scan line. */
696 uint16_t bytes_per_line;
697 /* Bits per pixel. */
698 uint16_t bits_per_pixel;
699 /* LFB physical address, and size (in units of 64kB). */
702 /* RGB mask offsets and sizes, as defined by VBE 1.2+ */
703 uint8_t red_pos, red_size;
704 uint8_t green_pos, green_size;
705 uint8_t blue_pos, blue_size;
706 uint8_t rsvd_pos, rsvd_size;
708 /* VESA capabilities (offset 0xa, VESA command 0x4f00). */
710 /* Mode attributes (offset 0x0, VESA command 0x4f01). */
716 typedef uint64_t cpumap_t;
718 typedef uint8_t xen_domain_handle_t[16];
720 /* Turn a plain number into a C unsigned long constant. */
721 #define __mk_unsigned_long(x) x ## UL
722 #define mk_unsigned_long(x) __mk_unsigned_long(x)
724 #define TMEM_SPEC_VERSION 1
730 struct { /* for cmd == TMEM_NEW_POOL */
737 uint32_t tmem_offset;
740 GUEST_HANDLE(void) gmfn; /* guest machine page frame */
745 DEFINE_GUEST_HANDLE(u64);
747 #else /* __ASSEMBLY__ */
749 /* In assembly code we cannot use C numeric constant suffixes. */
750 #define mk_unsigned_long(x) x
752 #endif /* !__ASSEMBLY__ */
754 #endif /* __XEN_PUBLIC_XEN_H__ */