2 * Library implementing the most common irq chip callback functions
4 * Copyright (C) 2011, Thomas Gleixner
8 #include <linux/slab.h>
9 #include <linux/export.h>
10 #include <linux/irqdomain.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/syscore_ops.h>
15 #include "internals.h"
17 static LIST_HEAD(gc_list);
18 static DEFINE_RAW_SPINLOCK(gc_lock);
21 * irq_gc_noop - NOOP function
24 void irq_gc_noop(struct irq_data *d)
29 * irq_gc_mask_disable_reg - Mask chip via disable register
32 * Chip has separate enable/disable registers instead of a single mask
35 void irq_gc_mask_disable_reg(struct irq_data *d)
37 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
38 struct irq_chip_type *ct = irq_data_get_chip_type(d);
42 irq_reg_writel(mask, gc->reg_base + ct->regs.disable);
43 *ct->mask_cache &= ~mask;
48 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
51 * Chip has a single mask register. Values of this register are cached
52 * and protected by gc->lock
54 void irq_gc_mask_set_bit(struct irq_data *d)
56 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
57 struct irq_chip_type *ct = irq_data_get_chip_type(d);
61 *ct->mask_cache |= mask;
62 irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
65 EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
68 * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
71 * Chip has a single mask register. Values of this register are cached
72 * and protected by gc->lock
74 void irq_gc_mask_clr_bit(struct irq_data *d)
76 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
77 struct irq_chip_type *ct = irq_data_get_chip_type(d);
81 *ct->mask_cache &= ~mask;
82 irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
85 EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
88 * irq_gc_unmask_enable_reg - Unmask chip via enable register
91 * Chip has separate enable/disable registers instead of a single mask
94 void irq_gc_unmask_enable_reg(struct irq_data *d)
96 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
97 struct irq_chip_type *ct = irq_data_get_chip_type(d);
101 irq_reg_writel(mask, gc->reg_base + ct->regs.enable);
102 *ct->mask_cache |= mask;
107 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
110 void irq_gc_ack_set_bit(struct irq_data *d)
112 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
113 struct irq_chip_type *ct = irq_data_get_chip_type(d);
117 irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
120 EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
123 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
126 void irq_gc_ack_clr_bit(struct irq_data *d)
128 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
129 struct irq_chip_type *ct = irq_data_get_chip_type(d);
133 irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
138 * irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt
141 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
143 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
144 struct irq_chip_type *ct = irq_data_get_chip_type(d);
148 irq_reg_writel(mask, gc->reg_base + ct->regs.mask);
149 irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
154 * irq_gc_eoi - EOI interrupt
157 void irq_gc_eoi(struct irq_data *d)
159 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
160 struct irq_chip_type *ct = irq_data_get_chip_type(d);
164 irq_reg_writel(mask, gc->reg_base + ct->regs.eoi);
169 * irq_gc_set_wake - Set/clr wake bit for an interrupt
171 * @on: Indicates whether the wake bit should be set or cleared
173 * For chips where the wake from suspend functionality is not
174 * configured in a separate register and the wakeup active state is
175 * just stored in a bitmask.
177 int irq_gc_set_wake(struct irq_data *d, unsigned int on)
179 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
182 if (!(mask & gc->wake_enabled))
187 gc->wake_active |= mask;
189 gc->wake_active &= ~mask;
195 irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
196 int num_ct, unsigned int irq_base,
197 void __iomem *reg_base, irq_flow_handler_t handler)
199 raw_spin_lock_init(&gc->lock);
201 gc->irq_base = irq_base;
202 gc->reg_base = reg_base;
203 gc->chip_types->chip.name = name;
204 gc->chip_types->handler = handler;
208 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
209 * @name: Name of the irq chip
210 * @num_ct: Number of irq_chip_type instances associated with this
211 * @irq_base: Interrupt base nr for this chip
212 * @reg_base: Register base address (virtual)
213 * @handler: Default flow handler associated with this chip
215 * Returns an initialized irq_chip_generic structure. The chip defaults
216 * to the primary (index 0) irq_chip_type and @handler
218 struct irq_chip_generic *
219 irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
220 void __iomem *reg_base, irq_flow_handler_t handler)
222 struct irq_chip_generic *gc;
223 unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
225 gc = kzalloc(sz, GFP_KERNEL);
227 irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
232 EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
235 irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
237 struct irq_chip_type *ct = gc->chip_types;
238 u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
241 for (i = 0; i < gc->num_ct; i++) {
242 if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
243 mskptr = &ct[i].mask_cache_priv;
244 mskreg = ct[i].regs.mask;
246 ct[i].mask_cache = mskptr;
247 if (flags & IRQ_GC_INIT_MASK_CACHE)
248 *mskptr = irq_reg_readl(gc->reg_base + mskreg);
253 * irq_alloc_domain_generic_chip - Allocate generic chips for an irq domain
254 * @d: irq domain for which to allocate chips
255 * @irqs_per_chip: Number of interrupts each chip handles
256 * @num_ct: Number of irq_chip_type instances associated with this
257 * @name: Name of the irq chip
258 * @handler: Default flow handler associated with these chips
259 * @clr: IRQ_* bits to clear in the mapping function
260 * @set: IRQ_* bits to set in the mapping function
261 * @gcflags: Generic chip specific setup flags
263 int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
264 int num_ct, const char *name,
265 irq_flow_handler_t handler,
266 unsigned int clr, unsigned int set,
267 enum irq_gc_flags gcflags)
269 struct irq_domain_chip_generic *dgc;
270 struct irq_chip_generic *gc;
278 if (d->revmap_type != IRQ_DOMAIN_MAP_LINEAR)
281 numchips = d->revmap_data.linear.size / irqs_per_chip;
285 /* Allocate a pointer, generic chip and chiptypes for each chip */
286 sz = sizeof(*dgc) + numchips * sizeof(gc);
287 sz += numchips * (sizeof(*gc) + num_ct * sizeof(struct irq_chip_type));
289 tmp = dgc = kzalloc(sz, GFP_KERNEL);
292 dgc->irqs_per_chip = irqs_per_chip;
293 dgc->num_chips = numchips;
294 dgc->irq_flags_to_set = set;
295 dgc->irq_flags_to_clear = clr;
296 dgc->gc_flags = gcflags;
299 /* Calc pointer to the first generic chip */
300 tmp += sizeof(*dgc) + numchips * sizeof(gc);
301 for (i = 0; i < numchips; i++) {
302 /* Store the pointer to the generic chip */
303 dgc->gc[i] = gc = tmp;
304 irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
307 raw_spin_lock_irqsave(&gc_lock, flags);
308 list_add_tail(&gc->list, &gc_list);
309 raw_spin_unlock_irqrestore(&gc_lock, flags);
310 /* Calc pointer to the next generic chip */
311 tmp += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
315 EXPORT_SYMBOL_GPL(irq_alloc_domain_generic_chips);
318 * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
319 * @d: irq domain pointer
320 * @hw_irq: Hardware interrupt number
322 struct irq_chip_generic *
323 irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
325 struct irq_domain_chip_generic *dgc = d->gc;
330 idx = hw_irq / dgc->irqs_per_chip;
331 if (idx >= dgc->num_chips)
335 EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
338 * Separate lockdep class for interrupt chip which can nest irq_desc
341 static struct lock_class_key irq_nested_lock_class;
344 * irq_map_generic_chip - Map a generic chip for an irq domain
346 static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
347 irq_hw_number_t hw_irq)
349 struct irq_data *data = irq_get_irq_data(virq);
350 struct irq_domain_chip_generic *dgc = d->gc;
351 struct irq_chip_generic *gc;
352 struct irq_chip_type *ct;
353 struct irq_chip *chip;
360 idx = hw_irq / dgc->irqs_per_chip;
361 if (idx >= dgc->num_chips)
365 idx = hw_irq % dgc->irqs_per_chip;
367 if (test_bit(idx, &gc->unused))
370 if (test_bit(idx, &gc->installed))
376 /* We only init the cache for the first mapping of a generic chip */
377 if (!gc->installed) {
378 raw_spin_lock_irqsave(&gc->lock, flags);
379 irq_gc_init_mask_cache(gc, dgc->gc_flags);
380 raw_spin_unlock_irqrestore(&gc->lock, flags);
383 /* Mark the interrupt as installed */
384 set_bit(idx, &gc->installed);
386 if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
387 irq_set_lockdep_class(virq, &irq_nested_lock_class);
389 if (chip->irq_calc_mask)
390 chip->irq_calc_mask(data);
392 data->mask = 1 << idx;
394 irq_set_chip_and_handler(virq, chip, ct->handler);
395 irq_set_chip_data(virq, gc);
396 irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
400 struct irq_domain_ops irq_generic_chip_ops = {
401 .map = irq_map_generic_chip,
402 .xlate = irq_domain_xlate_onetwocell,
404 EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
407 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
408 * @gc: Generic irq chip holding all data
409 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
410 * @flags: Flags for initialization
411 * @clr: IRQ_* bits to clear
412 * @set: IRQ_* bits to set
414 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
415 * initializes all interrupts to the primary irq_chip_type and its
416 * associated handler.
418 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
419 enum irq_gc_flags flags, unsigned int clr,
422 struct irq_chip_type *ct = gc->chip_types;
423 struct irq_chip *chip = &ct->chip;
426 raw_spin_lock(&gc_lock);
427 list_add_tail(&gc->list, &gc_list);
428 raw_spin_unlock(&gc_lock);
430 irq_gc_init_mask_cache(gc, flags);
432 for (i = gc->irq_base; msk; msk >>= 1, i++) {
436 if (flags & IRQ_GC_INIT_NESTED_LOCK)
437 irq_set_lockdep_class(i, &irq_nested_lock_class);
439 if (!(flags & IRQ_GC_NO_MASK)) {
440 struct irq_data *d = irq_get_irq_data(i);
442 if (chip->irq_calc_mask)
443 chip->irq_calc_mask(d);
445 d->mask = 1 << (i - gc->irq_base);
447 irq_set_chip_and_handler(i, chip, ct->handler);
448 irq_set_chip_data(i, gc);
449 irq_modify_status(i, clr, set);
451 gc->irq_cnt = i - gc->irq_base;
453 EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
456 * irq_setup_alt_chip - Switch to alternative chip
457 * @d: irq_data for this interrupt
458 * @type: Flow type to be initialized
460 * Only to be called from chip->irq_set_type() callbacks.
462 int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
464 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
465 struct irq_chip_type *ct = gc->chip_types;
468 for (i = 0; i < gc->num_ct; i++, ct++) {
469 if (ct->type & type) {
471 irq_data_to_desc(d)->handle_irq = ct->handler;
477 EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
480 * irq_remove_generic_chip - Remove a chip
481 * @gc: Generic irq chip holding all data
482 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
483 * @clr: IRQ_* bits to clear
484 * @set: IRQ_* bits to set
486 * Remove up to 32 interrupts starting from gc->irq_base.
488 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
489 unsigned int clr, unsigned int set)
491 unsigned int i = gc->irq_base;
493 raw_spin_lock(&gc_lock);
495 raw_spin_unlock(&gc_lock);
497 for (; msk; msk >>= 1, i++) {
501 /* Remove handler first. That will mask the irq line */
502 irq_set_handler(i, NULL);
503 irq_set_chip(i, &no_irq_chip);
504 irq_set_chip_data(i, NULL);
505 irq_modify_status(i, clr, set);
508 EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
510 static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
515 return irq_get_irq_data(gc->irq_base);
518 * We don't know which of the irqs has been actually
519 * installed. Use the first one.
524 virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
525 return virq ? irq_get_irq_data(virq) : NULL;
529 static int irq_gc_suspend(void)
531 struct irq_chip_generic *gc;
533 list_for_each_entry(gc, &gc_list, list) {
534 struct irq_chip_type *ct = gc->chip_types;
536 if (ct->chip.irq_suspend) {
537 struct irq_data *data = irq_gc_get_irq_data(gc);
540 ct->chip.irq_suspend(data);
546 static void irq_gc_resume(void)
548 struct irq_chip_generic *gc;
550 list_for_each_entry(gc, &gc_list, list) {
551 struct irq_chip_type *ct = gc->chip_types;
553 if (ct->chip.irq_resume) {
554 struct irq_data *data = irq_gc_get_irq_data(gc);
557 ct->chip.irq_resume(data);
562 #define irq_gc_suspend NULL
563 #define irq_gc_resume NULL
566 static void irq_gc_shutdown(void)
568 struct irq_chip_generic *gc;
570 list_for_each_entry(gc, &gc_list, list) {
571 struct irq_chip_type *ct = gc->chip_types;
573 if (ct->chip.irq_pm_shutdown) {
574 struct irq_data *data = irq_gc_get_irq_data(gc);
577 ct->chip.irq_pm_shutdown(data);
582 static struct syscore_ops irq_gc_syscore_ops = {
583 .suspend = irq_gc_suspend,
584 .resume = irq_gc_resume,
585 .shutdown = irq_gc_shutdown,
588 static int __init irq_gc_init_ops(void)
590 register_syscore_ops(&irq_gc_syscore_ops);
593 device_initcall(irq_gc_init_ops);