1 //===- CostModel.cpp ------ Cost Model Analysis ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the cost model analysis. It provides a very basic cost
11 // estimation for LLVM-IR. This analysis uses the services of the codegen
12 // to approximate the cost of any IR instruction when lowered to machine
13 // instructions. The cost results are unit-less and the cost number represents
14 // the throughput of the machine assuming that all loads hit the cache, all
15 // branches are predicted, etc. The cost numbers can be added in order to
16 // compare two or more transformation alternatives.
18 //===----------------------------------------------------------------------===//
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/Analysis/Passes.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/IR/Instructions.h"
25 #include "llvm/IR/IntrinsicInst.h"
26 #include "llvm/IR/Value.h"
27 #include "llvm/Pass.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/raw_ostream.h"
33 #define CM_NAME "cost-model"
34 #define DEBUG_TYPE CM_NAME
36 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
38 cl::desc("Recognize reduction patterns."));
41 class CostModelAnalysis : public FunctionPass {
44 static char ID; // Class identification, replacement for typeinfo
45 CostModelAnalysis() : FunctionPass(ID), F(nullptr), TTI(nullptr) {
46 initializeCostModelAnalysisPass(
47 *PassRegistry::getPassRegistry());
50 /// Returns the expected cost of the instruction.
51 /// Returns -1 if the cost is unknown.
52 /// Note, this method does not cache the cost calculation and it
53 /// can be expensive in some cases.
54 unsigned getInstructionCost(const Instruction *I) const;
57 void getAnalysisUsage(AnalysisUsage &AU) const override;
58 bool runOnFunction(Function &F) override;
59 void print(raw_ostream &OS, const Module*) const override;
61 /// The function that we analyze.
63 /// Target information.
64 const TargetTransformInfo *TTI;
66 } // End of anonymous namespace
68 // Register this pass.
69 char CostModelAnalysis::ID = 0;
70 static const char cm_name[] = "Cost Model Analysis";
71 INITIALIZE_PASS_BEGIN(CostModelAnalysis, CM_NAME, cm_name, false, true)
72 INITIALIZE_PASS_END (CostModelAnalysis, CM_NAME, cm_name, false, true)
74 FunctionPass *llvm::createCostModelAnalysisPass() {
75 return new CostModelAnalysis();
79 CostModelAnalysis::getAnalysisUsage(AnalysisUsage &AU) const {
84 CostModelAnalysis::runOnFunction(Function &F) {
86 auto *TTIWP = getAnalysisIfAvailable<TargetTransformInfoWrapperPass>();
87 TTI = TTIWP ? &TTIWP->getTTI(F) : nullptr;
92 static bool isReverseVectorMask(SmallVectorImpl<int> &Mask) {
93 for (unsigned i = 0, MaskSize = Mask.size(); i < MaskSize; ++i)
94 if (Mask[i] > 0 && Mask[i] != (int)(MaskSize - 1 - i))
99 static bool isAlternateVectorMask(SmallVectorImpl<int> &Mask) {
100 bool isAlternate = true;
101 unsigned MaskSize = Mask.size();
103 // Example: shufflevector A, B, <0,5,2,7>
104 for (unsigned i = 0; i < MaskSize && isAlternate; ++i) {
107 isAlternate = Mask[i] == (int)((i & 1) ? MaskSize + i : i);
114 // Example: shufflevector A, B, <4,1,6,3>
115 for (unsigned i = 0; i < MaskSize && isAlternate; ++i) {
118 isAlternate = Mask[i] == (int)((i & 1) ? i : MaskSize + i);
124 static TargetTransformInfo::OperandValueKind getOperandInfo(Value *V) {
125 TargetTransformInfo::OperandValueKind OpInfo =
126 TargetTransformInfo::OK_AnyValue;
128 // Check for a splat of a constant or for a non uniform vector of constants.
129 if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
130 OpInfo = TargetTransformInfo::OK_NonUniformConstantValue;
131 if (cast<Constant>(V)->getSplatValue() != nullptr)
132 OpInfo = TargetTransformInfo::OK_UniformConstantValue;
138 static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft,
140 // We don't need a shuffle if we just want to have element 0 in position 0 of
142 if (!SI && Level == 0 && IsLeft)
147 SmallVector<int, 32> Mask(SI->getType()->getVectorNumElements(), -1);
149 // Build a mask of 0, 2, ... (left) or 1, 3, ... (right) depending on whether
150 // we look at the left or right side.
151 for (unsigned i = 0, e = (1 << Level), val = !IsLeft; i != e; ++i, val += 2)
154 SmallVector<int, 16> ActualMask = SI->getShuffleMask();
155 if (Mask != ActualMask)
161 static bool matchPairwiseReductionAtLevel(const BinaryOperator *BinOp,
162 unsigned Level, unsigned NumLevels) {
163 // Match one level of pairwise operations.
164 // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
165 // <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
166 // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
167 // <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
168 // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
169 if (BinOp == nullptr)
172 assert(BinOp->getType()->isVectorTy() && "Expecting a vector type");
174 unsigned Opcode = BinOp->getOpcode();
175 Value *L = BinOp->getOperand(0);
176 Value *R = BinOp->getOperand(1);
178 ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(L);
181 ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(R);
185 // On level 0 we can omit one shufflevector instruction.
186 if (!Level && !RS && !LS)
189 // Shuffle inputs must match.
190 Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
191 Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
192 Value *NextLevelOp = nullptr;
193 if (NextLevelOpR && NextLevelOpL) {
194 // If we have two shuffles their operands must match.
195 if (NextLevelOpL != NextLevelOpR)
198 NextLevelOp = NextLevelOpL;
199 } else if (Level == 0 && (NextLevelOpR || NextLevelOpL)) {
200 // On the first level we can omit the shufflevector <0, undef,...>. So the
201 // input to the other shufflevector <1, undef> must match with one of the
202 // inputs to the current binary operation.
204 // %NextLevelOpL = shufflevector %R, <1, undef ...>
205 // %BinOp = fadd %NextLevelOpL, %R
206 if (NextLevelOpL && NextLevelOpL != R)
208 else if (NextLevelOpR && NextLevelOpR != L)
211 NextLevelOp = NextLevelOpL ? R : L;
215 // Check that the next levels binary operation exists and matches with the
217 BinaryOperator *NextLevelBinOp = nullptr;
218 if (Level + 1 != NumLevels) {
219 if (!(NextLevelBinOp = dyn_cast<BinaryOperator>(NextLevelOp)))
221 else if (NextLevelBinOp->getOpcode() != Opcode)
225 // Shuffle mask for pairwise operation must match.
226 if (matchPairwiseShuffleMask(LS, true, Level)) {
227 if (!matchPairwiseShuffleMask(RS, false, Level))
229 } else if (matchPairwiseShuffleMask(RS, true, Level)) {
230 if (!matchPairwiseShuffleMask(LS, false, Level))
235 if (++Level == NumLevels)
239 return matchPairwiseReductionAtLevel(NextLevelBinOp, Level, NumLevels);
242 static bool matchPairwiseReduction(const ExtractElementInst *ReduxRoot,
243 unsigned &Opcode, Type *&Ty) {
244 if (!EnableReduxCost)
247 // Need to extract the first element.
248 ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
251 Idx = CI->getZExtValue();
255 BinaryOperator *RdxStart = dyn_cast<BinaryOperator>(ReduxRoot->getOperand(0));
259 Type *VecTy = ReduxRoot->getOperand(0)->getType();
260 unsigned NumVecElems = VecTy->getVectorNumElements();
261 if (!isPowerOf2_32(NumVecElems))
264 // We look for a sequence of shuffle,shuffle,add triples like the following
265 // that builds a pairwise reduction tree.
268 // (X0 + X1, X2 + X3, undef, undef)
269 // ((X0 + X1) + (X2 + X3), undef, undef, undef)
271 // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
272 // <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
273 // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
274 // <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
275 // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
276 // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
277 // <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
278 // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
279 // <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
280 // %bin.rdx8 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
281 // %r = extractelement <4 x float> %bin.rdx8, i32 0
282 if (!matchPairwiseReductionAtLevel(RdxStart, 0, Log2_32(NumVecElems)))
285 Opcode = RdxStart->getOpcode();
291 static std::pair<Value *, ShuffleVectorInst *>
292 getShuffleAndOtherOprd(BinaryOperator *B) {
294 Value *L = B->getOperand(0);
295 Value *R = B->getOperand(1);
296 ShuffleVectorInst *S = nullptr;
298 if ((S = dyn_cast<ShuffleVectorInst>(L)))
299 return std::make_pair(R, S);
301 S = dyn_cast<ShuffleVectorInst>(R);
302 return std::make_pair(L, S);
305 static bool matchVectorSplittingReduction(const ExtractElementInst *ReduxRoot,
306 unsigned &Opcode, Type *&Ty) {
307 if (!EnableReduxCost)
310 // Need to extract the first element.
311 ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
314 Idx = CI->getZExtValue();
318 BinaryOperator *RdxStart = dyn_cast<BinaryOperator>(ReduxRoot->getOperand(0));
321 unsigned RdxOpcode = RdxStart->getOpcode();
323 Type *VecTy = ReduxRoot->getOperand(0)->getType();
324 unsigned NumVecElems = VecTy->getVectorNumElements();
325 if (!isPowerOf2_32(NumVecElems))
328 // We look for a sequence of shuffles and adds like the following matching one
329 // fadd, shuffle vector pair at a time.
331 // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
332 // <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
333 // %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
334 // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
335 // <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
336 // %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
337 // %r = extractelement <4 x float> %bin.rdx8, i32 0
339 unsigned MaskStart = 1;
340 Value *RdxOp = RdxStart;
341 SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
342 unsigned NumVecElemsRemain = NumVecElems;
343 while (NumVecElemsRemain - 1) {
344 // Check for the right reduction operation.
345 BinaryOperator *BinOp;
346 if (!(BinOp = dyn_cast<BinaryOperator>(RdxOp)))
348 if (BinOp->getOpcode() != RdxOpcode)
352 ShuffleVectorInst *Shuffle;
353 std::tie(NextRdxOp, Shuffle) = getShuffleAndOtherOprd(BinOp);
355 // Check the current reduction operation and the shuffle use the same value.
356 if (Shuffle == nullptr)
358 if (Shuffle->getOperand(0) != NextRdxOp)
361 // Check that shuffle masks matches.
362 for (unsigned j = 0; j != MaskStart; ++j)
363 ShuffleMask[j] = MaskStart + j;
364 // Fill the rest of the mask with -1 for undef.
365 std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
367 SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
368 if (ShuffleMask != Mask)
372 NumVecElemsRemain /= 2;
381 unsigned CostModelAnalysis::getInstructionCost(const Instruction *I) const {
385 switch (I->getOpcode()) {
386 case Instruction::GetElementPtr:
387 return TTI->getUserCost(I);
389 case Instruction::Ret:
390 case Instruction::PHI:
391 case Instruction::Br: {
392 return TTI->getCFInstrCost(I->getOpcode());
394 case Instruction::Add:
395 case Instruction::FAdd:
396 case Instruction::Sub:
397 case Instruction::FSub:
398 case Instruction::Mul:
399 case Instruction::FMul:
400 case Instruction::UDiv:
401 case Instruction::SDiv:
402 case Instruction::FDiv:
403 case Instruction::URem:
404 case Instruction::SRem:
405 case Instruction::FRem:
406 case Instruction::Shl:
407 case Instruction::LShr:
408 case Instruction::AShr:
409 case Instruction::And:
410 case Instruction::Or:
411 case Instruction::Xor: {
412 TargetTransformInfo::OperandValueKind Op1VK =
413 getOperandInfo(I->getOperand(0));
414 TargetTransformInfo::OperandValueKind Op2VK =
415 getOperandInfo(I->getOperand(1));
416 return TTI->getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK,
419 case Instruction::Select: {
420 const SelectInst *SI = cast<SelectInst>(I);
421 Type *CondTy = SI->getCondition()->getType();
422 return TTI->getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy);
424 case Instruction::ICmp:
425 case Instruction::FCmp: {
426 Type *ValTy = I->getOperand(0)->getType();
427 return TTI->getCmpSelInstrCost(I->getOpcode(), ValTy);
429 case Instruction::Store: {
430 const StoreInst *SI = cast<StoreInst>(I);
431 Type *ValTy = SI->getValueOperand()->getType();
432 return TTI->getMemoryOpCost(I->getOpcode(), ValTy,
434 SI->getPointerAddressSpace());
436 case Instruction::Load: {
437 const LoadInst *LI = cast<LoadInst>(I);
438 return TTI->getMemoryOpCost(I->getOpcode(), I->getType(),
440 LI->getPointerAddressSpace());
442 case Instruction::ZExt:
443 case Instruction::SExt:
444 case Instruction::FPToUI:
445 case Instruction::FPToSI:
446 case Instruction::FPExt:
447 case Instruction::PtrToInt:
448 case Instruction::IntToPtr:
449 case Instruction::SIToFP:
450 case Instruction::UIToFP:
451 case Instruction::Trunc:
452 case Instruction::FPTrunc:
453 case Instruction::BitCast:
454 case Instruction::AddrSpaceCast: {
455 Type *SrcTy = I->getOperand(0)->getType();
456 return TTI->getCastInstrCost(I->getOpcode(), I->getType(), SrcTy);
458 case Instruction::ExtractElement: {
459 const ExtractElementInst * EEI = cast<ExtractElementInst>(I);
460 ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1));
463 Idx = CI->getZExtValue();
465 // Try to match a reduction sequence (series of shufflevector and vector
466 // adds followed by a extractelement).
467 unsigned ReduxOpCode;
470 if (matchVectorSplittingReduction(EEI, ReduxOpCode, ReduxType))
471 return TTI->getReductionCost(ReduxOpCode, ReduxType, false);
472 else if (matchPairwiseReduction(EEI, ReduxOpCode, ReduxType))
473 return TTI->getReductionCost(ReduxOpCode, ReduxType, true);
475 return TTI->getVectorInstrCost(I->getOpcode(),
476 EEI->getOperand(0)->getType(), Idx);
478 case Instruction::InsertElement: {
479 const InsertElementInst * IE = cast<InsertElementInst>(I);
480 ConstantInt *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
483 Idx = CI->getZExtValue();
484 return TTI->getVectorInstrCost(I->getOpcode(),
487 case Instruction::ShuffleVector: {
488 const ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
489 Type *VecTypOp0 = Shuffle->getOperand(0)->getType();
490 unsigned NumVecElems = VecTypOp0->getVectorNumElements();
491 SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
493 if (NumVecElems == Mask.size()) {
494 if (isReverseVectorMask(Mask))
495 return TTI->getShuffleCost(TargetTransformInfo::SK_Reverse, VecTypOp0,
497 if (isAlternateVectorMask(Mask))
498 return TTI->getShuffleCost(TargetTransformInfo::SK_Alternate,
499 VecTypOp0, 0, nullptr);
504 case Instruction::Call:
505 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
506 SmallVector<Type*, 4> Tys;
507 for (unsigned J = 0, JE = II->getNumArgOperands(); J != JE; ++J)
508 Tys.push_back(II->getArgOperand(J)->getType());
510 return TTI->getIntrinsicInstrCost(II->getIntrinsicID(), II->getType(),
515 // We don't have any information on this instruction.
520 void CostModelAnalysis::print(raw_ostream &OS, const Module*) const {
524 for (Function::iterator B = F->begin(), BE = F->end(); B != BE; ++B) {
525 for (BasicBlock::iterator it = B->begin(), e = B->end(); it != e; ++it) {
526 Instruction *Inst = it;
527 unsigned Cost = getInstructionCost(Inst);
528 if (Cost != (unsigned)-1)
529 OS << "Cost Model: Found an estimated cost of " << Cost;
531 OS << "Cost Model: Unknown cost";
533 OS << " for instruction: "<< *Inst << "\n";