1 //===----- AggressiveAntiDepBreaker.cpp - Anti-dep breaker ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AggressiveAntiDepBreaker class, which
11 // implements register anti-dependence breaking during post-RA
12 // scheduling. It attempts to break all anti-dependencies within a
15 //===----------------------------------------------------------------------===//
17 #include "AggressiveAntiDepBreaker.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/CodeGen/RegisterClassInfo.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
30 #define DEBUG_TYPE "post-RA-sched"
32 // If DebugDiv > 0 then only break antidep with (ID % DebugDiv) == DebugMod
34 DebugDiv("agg-antidep-debugdiv",
35 cl::desc("Debug control for aggressive anti-dep breaker"),
36 cl::init(0), cl::Hidden);
38 DebugMod("agg-antidep-debugmod",
39 cl::desc("Debug control for aggressive anti-dep breaker"),
40 cl::init(0), cl::Hidden);
42 AggressiveAntiDepState::AggressiveAntiDepState(const unsigned TargetRegs,
43 MachineBasicBlock *BB) :
44 NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0),
45 GroupNodeIndices(TargetRegs, 0),
46 KillIndices(TargetRegs, 0),
47 DefIndices(TargetRegs, 0)
49 const unsigned BBSize = BB->size();
50 for (unsigned i = 0; i < NumTargetRegs; ++i) {
51 // Initialize all registers to be in their own group. Initially we
52 // assign the register to the same-indexed GroupNode.
53 GroupNodeIndices[i] = i;
54 // Initialize the indices to indicate that no registers are live.
56 DefIndices[i] = BBSize;
60 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
61 unsigned Node = GroupNodeIndices[Reg];
62 while (GroupNodes[Node] != Node)
63 Node = GroupNodes[Node];
68 void AggressiveAntiDepState::GetGroupRegs(
70 std::vector<unsigned> &Regs,
71 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs)
73 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
74 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
79 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2)
81 assert(GroupNodes[0] == 0 && "GroupNode 0 not parent!");
82 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
84 // find group for each register
85 unsigned Group1 = GetGroup(Reg1);
86 unsigned Group2 = GetGroup(Reg2);
88 // if either group is 0, then that must become the parent
89 unsigned Parent = (Group1 == 0) ? Group1 : Group2;
90 unsigned Other = (Parent == Group1) ? Group2 : Group1;
91 GroupNodes.at(Other) = Parent;
95 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
97 // Create a new GroupNode for Reg. Reg's existing GroupNode must
98 // stay as is because there could be other GroupNodes referring to
100 unsigned idx = GroupNodes.size();
101 GroupNodes.push_back(idx);
102 GroupNodeIndices[Reg] = idx;
106 bool AggressiveAntiDepState::IsLive(unsigned Reg)
108 // KillIndex must be defined and DefIndex not defined for a register
110 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
113 AggressiveAntiDepBreaker::AggressiveAntiDepBreaker(
114 MachineFunction &MFi, const RegisterClassInfo &RCI,
115 TargetSubtargetInfo::RegClassVector &CriticalPathRCs)
116 : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()),
117 TII(MF.getSubtarget().getInstrInfo()),
118 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI),
120 /* Collect a bitset of all registers that are only broken if they
121 are on the critical path. */
122 for (unsigned i = 0, e = CriticalPathRCs.size(); i < e; ++i) {
123 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]);
124 if (CriticalPathSet.none())
125 CriticalPathSet = CPSet;
127 CriticalPathSet |= CPSet;
130 DEBUG(dbgs() << "AntiDep Critical-Path Registers:");
131 DEBUG(for (int r = CriticalPathSet.find_first(); r != -1;
132 r = CriticalPathSet.find_next(r))
133 dbgs() << " " << TRI->getName(r));
134 DEBUG(dbgs() << '\n');
137 AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() {
141 void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
143 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
145 bool IsReturnBlock = (!BB->empty() && BB->back().isReturn());
146 std::vector<unsigned> &KillIndices = State->GetKillIndices();
147 std::vector<unsigned> &DefIndices = State->GetDefIndices();
149 // Examine the live-in regs of all successors.
150 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
151 SE = BB->succ_end(); SI != SE; ++SI)
152 for (unsigned LI : (*SI)->liveins()) {
153 for (MCRegAliasIterator AI(LI, TRI, true); AI.isValid(); ++AI) {
155 State->UnionGroups(Reg, 0);
156 KillIndices[Reg] = BB->size();
157 DefIndices[Reg] = ~0u;
161 // Mark live-out callee-saved registers. In a return block this is
162 // all callee-saved registers. In non-return this is any
163 // callee-saved register that is not saved in the prolog.
164 const MachineFrameInfo *MFI = MF.getFrameInfo();
165 BitVector Pristine = MFI->getPristineRegs(MF);
166 for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
168 if (!IsReturnBlock && !Pristine.test(Reg)) continue;
169 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
170 unsigned AliasReg = *AI;
171 State->UnionGroups(AliasReg, 0);
172 KillIndices[AliasReg] = BB->size();
173 DefIndices[AliasReg] = ~0u;
178 void AggressiveAntiDepBreaker::FinishBlock() {
183 void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
184 unsigned InsertPosIndex) {
185 assert(Count < InsertPosIndex && "Instruction index out of expected range!");
187 std::set<unsigned> PassthruRegs;
188 GetPassthruRegs(MI, PassthruRegs);
189 PrescanInstruction(MI, Count, PassthruRegs);
190 ScanInstruction(MI, Count);
192 DEBUG(dbgs() << "Observe: ");
194 DEBUG(dbgs() << "\tRegs:");
196 std::vector<unsigned> &DefIndices = State->GetDefIndices();
197 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
198 // If Reg is current live, then mark that it can't be renamed as
199 // we don't know the extent of its live-range anymore (now that it
200 // has been scheduled). If it is not live but was defined in the
201 // previous schedule region, then set its def index to the most
202 // conservative location (i.e. the beginning of the previous
204 if (State->IsLive(Reg)) {
205 DEBUG(if (State->GetGroup(Reg) != 0)
206 dbgs() << " " << TRI->getName(Reg) << "=g" <<
207 State->GetGroup(Reg) << "->g0(region live-out)");
208 State->UnionGroups(Reg, 0);
209 } else if ((DefIndices[Reg] < InsertPosIndex)
210 && (DefIndices[Reg] >= Count)) {
211 DefIndices[Reg] = Count;
214 DEBUG(dbgs() << '\n');
217 bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr *MI,
220 if (!MO.isReg() || !MO.isImplicit())
223 unsigned Reg = MO.getReg();
227 MachineOperand *Op = nullptr;
229 Op = MI->findRegisterUseOperand(Reg, true);
231 Op = MI->findRegisterDefOperand(Reg);
233 return(Op && Op->isImplicit());
236 void AggressiveAntiDepBreaker::GetPassthruRegs(MachineInstr *MI,
237 std::set<unsigned>& PassthruRegs) {
238 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
239 MachineOperand &MO = MI->getOperand(i);
240 if (!MO.isReg()) continue;
241 if ((MO.isDef() && MI->isRegTiedToUseOperand(i)) ||
242 IsImplicitDefUse(MI, MO)) {
243 const unsigned Reg = MO.getReg();
244 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
245 SubRegs.isValid(); ++SubRegs)
246 PassthruRegs.insert(*SubRegs);
251 /// AntiDepEdges - Return in Edges the anti- and output- dependencies
252 /// in SU that we want to consider for breaking.
253 static void AntiDepEdges(const SUnit *SU, std::vector<const SDep*>& Edges) {
254 SmallSet<unsigned, 4> RegSet;
255 for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
257 if ((P->getKind() == SDep::Anti) || (P->getKind() == SDep::Output)) {
258 if (RegSet.insert(P->getReg()).second)
259 Edges.push_back(&*P);
264 /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
266 static const SUnit *CriticalPathStep(const SUnit *SU) {
267 const SDep *Next = nullptr;
268 unsigned NextDepth = 0;
269 // Find the predecessor edge with the greatest depth.
271 for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
273 const SUnit *PredSU = P->getSUnit();
274 unsigned PredLatency = P->getLatency();
275 unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
276 // In the case of a latency tie, prefer an anti-dependency edge over
277 // other types of edges.
278 if (NextDepth < PredTotalLatency ||
279 (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
280 NextDepth = PredTotalLatency;
286 return (Next) ? Next->getSUnit() : nullptr;
289 void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
292 const char *footer) {
293 std::vector<unsigned> &KillIndices = State->GetKillIndices();
294 std::vector<unsigned> &DefIndices = State->GetDefIndices();
295 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
296 RegRefs = State->GetRegRefs();
298 // FIXME: We must leave subregisters of live super registers as live, so that
299 // we don't clear out the register tracking information for subregisters of
300 // super registers we're still tracking (and with which we're unioning
301 // subregister definitions).
302 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
303 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) {
304 DEBUG(if (!header && footer) dbgs() << footer);
308 if (!State->IsLive(Reg)) {
309 KillIndices[Reg] = KillIdx;
310 DefIndices[Reg] = ~0u;
312 State->LeaveGroup(Reg);
314 dbgs() << header << TRI->getName(Reg); header = nullptr; });
315 DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
317 // Repeat for subregisters.
318 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
319 unsigned SubregReg = *SubRegs;
320 if (!State->IsLive(SubregReg)) {
321 KillIndices[SubregReg] = KillIdx;
322 DefIndices[SubregReg] = ~0u;
323 RegRefs.erase(SubregReg);
324 State->LeaveGroup(SubregReg);
326 dbgs() << header << TRI->getName(Reg); header = nullptr; });
327 DEBUG(dbgs() << " " << TRI->getName(SubregReg) << "->g" <<
328 State->GetGroup(SubregReg) << tag);
332 DEBUG(if (!header && footer) dbgs() << footer);
335 void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI,
337 std::set<unsigned>& PassthruRegs) {
338 std::vector<unsigned> &DefIndices = State->GetDefIndices();
339 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
340 RegRefs = State->GetRegRefs();
342 // Handle dead defs by simulating a last-use of the register just
343 // after the def. A dead def can occur because the def is truly
344 // dead, or because only a subregister is live at the def. If we
345 // don't do this the dead def will be incorrectly merged into the
347 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
348 MachineOperand &MO = MI->getOperand(i);
349 if (!MO.isReg() || !MO.isDef()) continue;
350 unsigned Reg = MO.getReg();
351 if (Reg == 0) continue;
353 HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
356 DEBUG(dbgs() << "\tDef Groups:");
357 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
358 MachineOperand &MO = MI->getOperand(i);
359 if (!MO.isReg() || !MO.isDef()) continue;
360 unsigned Reg = MO.getReg();
361 if (Reg == 0) continue;
363 DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
365 // If MI's defs have a special allocation requirement, don't allow
366 // any def registers to be changed. Also assume all registers
367 // defined in a call must not be changed (ABI).
368 if (MI->isCall() || MI->hasExtraDefRegAllocReq() ||
369 TII->isPredicated(MI)) {
370 DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
371 State->UnionGroups(Reg, 0);
374 // Any aliased that are live at this point are completely or
375 // partially defined here, so group those aliases with Reg.
376 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
377 unsigned AliasReg = *AI;
378 if (State->IsLive(AliasReg)) {
379 State->UnionGroups(Reg, AliasReg);
380 DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " <<
381 TRI->getName(AliasReg) << ")");
385 // Note register reference...
386 const TargetRegisterClass *RC = nullptr;
387 if (i < MI->getDesc().getNumOperands())
388 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
389 AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
390 RegRefs.insert(std::make_pair(Reg, RR));
393 DEBUG(dbgs() << '\n');
395 // Scan the register defs for this instruction and update
397 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
398 MachineOperand &MO = MI->getOperand(i);
399 if (!MO.isReg() || !MO.isDef()) continue;
400 unsigned Reg = MO.getReg();
401 if (Reg == 0) continue;
402 // Ignore KILLs and passthru registers for liveness...
403 if (MI->isKill() || (PassthruRegs.count(Reg) != 0))
406 // Update def for Reg and aliases.
407 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
408 // We need to be careful here not to define already-live super registers.
409 // If the super register is already live, then this definition is not
410 // a definition of the whole super register (just a partial insertion
411 // into it). Earlier subregister definitions (which we've not yet visited
412 // because we're iterating bottom-up) need to be linked to the same group
413 // as this definition.
414 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI))
417 DefIndices[*AI] = Count;
422 void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
424 DEBUG(dbgs() << "\tUse Groups:");
425 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
426 RegRefs = State->GetRegRefs();
428 // If MI's uses have special allocation requirement, don't allow
429 // any use registers to be changed. Also assume all registers
430 // used in a call must not be changed (ABI).
431 // FIXME: The issue with predicated instruction is more complex. We are being
432 // conservatively here because the kill markers cannot be trusted after
434 // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
436 // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
437 // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
438 // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
440 // The first R6 kill is not really a kill since it's killed by a predicated
441 // instruction which may not be executed. The second R6 def may or may not
442 // re-define R6 so it's not safe to change it since the last R6 use cannot be
444 bool Special = MI->isCall() ||
445 MI->hasExtraSrcRegAllocReq() ||
446 TII->isPredicated(MI);
448 // Scan the register uses for this instruction and update
449 // live-ranges, groups and RegRefs.
450 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
451 MachineOperand &MO = MI->getOperand(i);
452 if (!MO.isReg() || !MO.isUse()) continue;
453 unsigned Reg = MO.getReg();
454 if (Reg == 0) continue;
456 DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" <<
457 State->GetGroup(Reg));
459 // It wasn't previously live but now it is, this is a kill. Forget
460 // the previous live-range information and start a new live-range
462 HandleLastUse(Reg, Count, "(last-use)");
465 DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
466 State->UnionGroups(Reg, 0);
469 // Note register reference...
470 const TargetRegisterClass *RC = nullptr;
471 if (i < MI->getDesc().getNumOperands())
472 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
473 AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
474 RegRefs.insert(std::make_pair(Reg, RR));
477 DEBUG(dbgs() << '\n');
479 // Form a group of all defs and uses of a KILL instruction to ensure
480 // that all registers are renamed as a group.
482 DEBUG(dbgs() << "\tKill Group:");
484 unsigned FirstReg = 0;
485 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
486 MachineOperand &MO = MI->getOperand(i);
487 if (!MO.isReg()) continue;
488 unsigned Reg = MO.getReg();
489 if (Reg == 0) continue;
492 DEBUG(dbgs() << "=" << TRI->getName(Reg));
493 State->UnionGroups(FirstReg, Reg);
495 DEBUG(dbgs() << " " << TRI->getName(Reg));
500 DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
504 BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
505 BitVector BV(TRI->getNumRegs(), false);
508 // Check all references that need rewriting for Reg. For each, use
509 // the corresponding register class to narrow the set of registers
510 // that are appropriate for renaming.
511 for (const auto &Q : make_range(State->GetRegRefs().equal_range(Reg))) {
512 const TargetRegisterClass *RC = Q.second.RC;
515 BitVector RCBV = TRI->getAllocatableSet(MF, RC);
523 DEBUG(dbgs() << " " << TRI->getRegClassName(RC));
529 bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
530 unsigned AntiDepGroupIndex,
531 RenameOrderType& RenameOrder,
532 std::map<unsigned, unsigned> &RenameMap) {
533 std::vector<unsigned> &KillIndices = State->GetKillIndices();
534 std::vector<unsigned> &DefIndices = State->GetDefIndices();
535 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
536 RegRefs = State->GetRegRefs();
538 // Collect all referenced registers in the same group as
539 // AntiDepReg. These all need to be renamed together if we are to
540 // break the anti-dependence.
541 std::vector<unsigned> Regs;
542 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
543 assert(Regs.size() > 0 && "Empty register group!");
544 if (Regs.size() == 0)
547 // Find the "superest" register in the group. At the same time,
548 // collect the BitVector of registers that can be used to rename
550 DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex
552 std::map<unsigned, BitVector> RenameRegisterMap;
553 unsigned SuperReg = 0;
554 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
555 unsigned Reg = Regs[i];
556 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
559 // If Reg has any references, then collect possible rename regs
560 if (RegRefs.count(Reg) > 0) {
561 DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":");
563 BitVector BV = GetRenameRegisters(Reg);
564 RenameRegisterMap.insert(std::pair<unsigned, BitVector>(Reg, BV));
566 DEBUG(dbgs() << " ::");
567 DEBUG(for (int r = BV.find_first(); r != -1; r = BV.find_next(r))
568 dbgs() << " " << TRI->getName(r));
569 DEBUG(dbgs() << "\n");
573 // All group registers should be a subreg of SuperReg.
574 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
575 unsigned Reg = Regs[i];
576 if (Reg == SuperReg) continue;
577 bool IsSub = TRI->isSubRegister(SuperReg, Reg);
578 // FIXME: remove this once PR18663 has been properly fixed. For now,
579 // return a conservative answer:
580 // assert(IsSub && "Expecting group subregister");
586 // If DebugDiv > 0 then only rename (renamecnt % DebugDiv) == DebugMod
588 static int renamecnt = 0;
589 if (renamecnt++ % DebugDiv != DebugMod)
592 dbgs() << "*** Performing rename " << TRI->getName(SuperReg) <<
597 // Check each possible rename register for SuperReg in round-robin
598 // order. If that register is available, and the corresponding
599 // registers are available for the other group subregisters, then we
600 // can use those registers to rename.
602 // FIXME: Using getMinimalPhysRegClass is very conservative. We should
603 // check every use of the register and find the largest register class
604 // that can be used in all of them.
605 const TargetRegisterClass *SuperRC =
606 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other);
608 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
610 DEBUG(dbgs() << "\tEmpty Super Regclass!!\n");
614 DEBUG(dbgs() << "\tFind Registers:");
616 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size()));
618 unsigned OrigR = RenameOrder[SuperRC];
619 unsigned EndR = ((OrigR == Order.size()) ? 0 : OrigR);
622 if (R == 0) R = Order.size();
624 const unsigned NewSuperReg = Order[R];
625 // Don't consider non-allocatable registers
626 if (!MRI.isAllocatable(NewSuperReg)) continue;
627 // Don't replace a register with itself.
628 if (NewSuperReg == SuperReg) continue;
630 DEBUG(dbgs() << " [" << TRI->getName(NewSuperReg) << ':');
633 // For each referenced group register (which must be a SuperReg or
634 // a subregister of SuperReg), find the corresponding subregister
635 // of NewSuperReg and make sure it is free to be renamed.
636 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
637 unsigned Reg = Regs[i];
639 if (Reg == SuperReg) {
640 NewReg = NewSuperReg;
642 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg);
643 if (NewSubRegIdx != 0)
644 NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx);
647 DEBUG(dbgs() << " " << TRI->getName(NewReg));
649 // Check if Reg can be renamed to NewReg.
650 BitVector BV = RenameRegisterMap[Reg];
651 if (!BV.test(NewReg)) {
652 DEBUG(dbgs() << "(no rename)");
656 // If NewReg is dead and NewReg's most recent def is not before
657 // Regs's kill, it's safe to replace Reg with NewReg. We
658 // must also check all aliases of NewReg, because we can't define a
659 // register when any sub or super is already live.
660 if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) {
661 DEBUG(dbgs() << "(live)");
665 for (MCRegAliasIterator AI(NewReg, TRI, false); AI.isValid(); ++AI) {
666 unsigned AliasReg = *AI;
667 if (State->IsLive(AliasReg) ||
668 (KillIndices[Reg] > DefIndices[AliasReg])) {
669 DEBUG(dbgs() << "(alias " << TRI->getName(AliasReg) << " live)");
678 // We cannot rename 'Reg' to 'NewReg' if one of the uses of 'Reg' also
679 // defines 'NewReg' via an early-clobber operand.
680 for (const auto &Q : make_range(RegRefs.equal_range(Reg))) {
681 MachineInstr *UseMI = Q.second.Operand->getParent();
682 int Idx = UseMI->findRegisterDefOperandIdx(NewReg, false, true, TRI);
686 if (UseMI->getOperand(Idx).isEarlyClobber()) {
687 DEBUG(dbgs() << "(ec)");
692 // Also, we cannot rename 'Reg' to 'NewReg' if the instruction defining
693 // 'Reg' is an early-clobber define and that instruction also uses
695 for (const auto &Q : make_range(RegRefs.equal_range(Reg))) {
696 if (!Q.second.Operand->isDef() || !Q.second.Operand->isEarlyClobber())
699 MachineInstr *DefMI = Q.second.Operand->getParent();
700 if (DefMI->readsRegister(NewReg, TRI)) {
701 DEBUG(dbgs() << "(ec)");
706 // Record that 'Reg' can be renamed to 'NewReg'.
707 RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg));
710 // If we fall-out here, then every register in the group can be
711 // renamed, as recorded in RenameMap.
712 RenameOrder.erase(SuperRC);
713 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R));
714 DEBUG(dbgs() << "]\n");
718 DEBUG(dbgs() << ']');
721 DEBUG(dbgs() << '\n');
723 // No registers are free and available!
727 /// BreakAntiDependencies - Identifiy anti-dependencies within the
728 /// ScheduleDAG and break them by renaming registers.
730 unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
731 const std::vector<SUnit>& SUnits,
732 MachineBasicBlock::iterator Begin,
733 MachineBasicBlock::iterator End,
734 unsigned InsertPosIndex,
735 DbgValueVector &DbgValues) {
737 std::vector<unsigned> &KillIndices = State->GetKillIndices();
738 std::vector<unsigned> &DefIndices = State->GetDefIndices();
739 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
740 RegRefs = State->GetRegRefs();
742 // The code below assumes that there is at least one instruction,
743 // so just duck out immediately if the block is empty.
744 if (SUnits.empty()) return 0;
746 // For each regclass the next register to use for renaming.
747 RenameOrderType RenameOrder;
749 // ...need a map from MI to SUnit.
750 std::map<MachineInstr *, const SUnit *> MISUnitMap;
751 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
752 const SUnit *SU = &SUnits[i];
753 MISUnitMap.insert(std::pair<MachineInstr *, const SUnit *>(SU->getInstr(),
757 // Track progress along the critical path through the SUnit graph as
758 // we walk the instructions. This is needed for regclasses that only
759 // break critical-path anti-dependencies.
760 const SUnit *CriticalPathSU = nullptr;
761 MachineInstr *CriticalPathMI = nullptr;
762 if (CriticalPathSet.any()) {
763 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
764 const SUnit *SU = &SUnits[i];
765 if (!CriticalPathSU ||
766 ((SU->getDepth() + SU->Latency) >
767 (CriticalPathSU->getDepth() + CriticalPathSU->Latency))) {
772 CriticalPathMI = CriticalPathSU->getInstr();
776 DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n");
777 DEBUG(dbgs() << "Available regs:");
778 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
779 if (!State->IsLive(Reg))
780 DEBUG(dbgs() << " " << TRI->getName(Reg));
782 DEBUG(dbgs() << '\n');
785 // Attempt to break anti-dependence edges. Walk the instructions
786 // from the bottom up, tracking information about liveness as we go
787 // to help determine which registers are available.
789 unsigned Count = InsertPosIndex - 1;
790 for (MachineBasicBlock::iterator I = End, E = Begin;
792 MachineInstr *MI = --I;
794 if (MI->isDebugValue())
797 DEBUG(dbgs() << "Anti: ");
800 std::set<unsigned> PassthruRegs;
801 GetPassthruRegs(MI, PassthruRegs);
803 // Process the defs in MI...
804 PrescanInstruction(MI, Count, PassthruRegs);
806 // The dependence edges that represent anti- and output-
807 // dependencies that are candidates for breaking.
808 std::vector<const SDep *> Edges;
809 const SUnit *PathSU = MISUnitMap[MI];
810 AntiDepEdges(PathSU, Edges);
812 // If MI is not on the critical path, then we don't rename
813 // registers in the CriticalPathSet.
814 BitVector *ExcludeRegs = nullptr;
815 if (MI == CriticalPathMI) {
816 CriticalPathSU = CriticalPathStep(CriticalPathSU);
817 CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : nullptr;
818 } else if (CriticalPathSet.any()) {
819 ExcludeRegs = &CriticalPathSet;
822 // Ignore KILL instructions (they form a group in ScanInstruction
823 // but don't cause any anti-dependence breaking themselves)
825 // Attempt to break each anti-dependency...
826 for (unsigned i = 0, e = Edges.size(); i != e; ++i) {
827 const SDep *Edge = Edges[i];
828 SUnit *NextSU = Edge->getSUnit();
830 if ((Edge->getKind() != SDep::Anti) &&
831 (Edge->getKind() != SDep::Output)) continue;
833 unsigned AntiDepReg = Edge->getReg();
834 DEBUG(dbgs() << "\tAntidep reg: " << TRI->getName(AntiDepReg));
835 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
837 if (!MRI.isAllocatable(AntiDepReg)) {
838 // Don't break anti-dependencies on non-allocatable registers.
839 DEBUG(dbgs() << " (non-allocatable)\n");
841 } else if (ExcludeRegs && ExcludeRegs->test(AntiDepReg)) {
842 // Don't break anti-dependencies for critical path registers
843 // if not on the critical path
844 DEBUG(dbgs() << " (not critical-path)\n");
846 } else if (PassthruRegs.count(AntiDepReg) != 0) {
847 // If the anti-dep register liveness "passes-thru", then
848 // don't try to change it. It will be changed along with
849 // the use if required to break an earlier antidep.
850 DEBUG(dbgs() << " (passthru)\n");
853 // No anti-dep breaking for implicit deps
854 MachineOperand *AntiDepOp = MI->findRegisterDefOperand(AntiDepReg);
855 assert(AntiDepOp && "Can't find index for defined register operand");
856 if (!AntiDepOp || AntiDepOp->isImplicit()) {
857 DEBUG(dbgs() << " (implicit)\n");
861 // If the SUnit has other dependencies on the SUnit that
862 // it anti-depends on, don't bother breaking the
863 // anti-dependency since those edges would prevent such
864 // units from being scheduled past each other
867 // Also, if there are dependencies on other SUnits with the
868 // same register as the anti-dependency, don't attempt to
870 for (SUnit::const_pred_iterator P = PathSU->Preds.begin(),
871 PE = PathSU->Preds.end(); P != PE; ++P) {
872 if (P->getSUnit() == NextSU ?
873 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
874 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
879 for (SUnit::const_pred_iterator P = PathSU->Preds.begin(),
880 PE = PathSU->Preds.end(); P != PE; ++P) {
881 if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) &&
882 (P->getKind() != SDep::Output)) {
883 DEBUG(dbgs() << " (real dependency)\n");
886 } else if ((P->getSUnit() != NextSU) &&
887 (P->getKind() == SDep::Data) &&
888 (P->getReg() == AntiDepReg)) {
889 DEBUG(dbgs() << " (other dependency)\n");
895 if (AntiDepReg == 0) continue;
898 assert(AntiDepReg != 0);
899 if (AntiDepReg == 0) continue;
901 // Determine AntiDepReg's register group.
902 const unsigned GroupIndex = State->GetGroup(AntiDepReg);
903 if (GroupIndex == 0) {
904 DEBUG(dbgs() << " (zero group)\n");
908 DEBUG(dbgs() << '\n');
910 // Look for a suitable register to use to break the anti-dependence.
911 std::map<unsigned, unsigned> RenameMap;
912 if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) {
913 DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
914 << TRI->getName(AntiDepReg) << ":");
916 // Handle each group register...
917 for (std::map<unsigned, unsigned>::iterator
918 S = RenameMap.begin(), E = RenameMap.end(); S != E; ++S) {
919 unsigned CurrReg = S->first;
920 unsigned NewReg = S->second;
922 DEBUG(dbgs() << " " << TRI->getName(CurrReg) << "->" <<
923 TRI->getName(NewReg) << "(" <<
924 RegRefs.count(CurrReg) << " refs)");
926 // Update the references to the old register CurrReg to
927 // refer to the new register NewReg.
928 for (const auto &Q : make_range(RegRefs.equal_range(CurrReg))) {
929 Q.second.Operand->setReg(NewReg);
930 // If the SU for the instruction being updated has debug
931 // information related to the anti-dependency register, make
932 // sure to update that as well.
933 const SUnit *SU = MISUnitMap[Q.second.Operand->getParent()];
935 for (DbgValueVector::iterator DVI = DbgValues.begin(),
936 DVE = DbgValues.end(); DVI != DVE; ++DVI)
937 if (DVI->second == Q.second.Operand->getParent())
938 UpdateDbgValue(DVI->first, AntiDepReg, NewReg);
941 // We just went back in time and modified history; the
942 // liveness information for CurrReg is now inconsistent. Set
943 // the state as if it were dead.
944 State->UnionGroups(NewReg, 0);
945 RegRefs.erase(NewReg);
946 DefIndices[NewReg] = DefIndices[CurrReg];
947 KillIndices[NewReg] = KillIndices[CurrReg];
949 State->UnionGroups(CurrReg, 0);
950 RegRefs.erase(CurrReg);
951 DefIndices[CurrReg] = KillIndices[CurrReg];
952 KillIndices[CurrReg] = ~0u;
953 assert(((KillIndices[CurrReg] == ~0u) !=
954 (DefIndices[CurrReg] == ~0u)) &&
955 "Kill and Def maps aren't consistent for AntiDepReg!");
959 DEBUG(dbgs() << '\n');
964 ScanInstruction(MI, Count);