1 //===----- AggressiveAntiDepBreaker.cpp - Anti-dep breaker ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AggressiveAntiDepBreaker class, which
11 // implements register anti-dependence breaking during post-RA
12 // scheduling. It attempts to break all anti-dependencies within a
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "post-RA-sched"
18 #include "AggressiveAntiDepBreaker.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
31 // If DebugDiv > 0 then only break antidep with (ID % DebugDiv) == DebugMod
33 DebugDiv("agg-antidep-debugdiv",
34 cl::desc("Debug control for aggressive anti-dep breaker"),
35 cl::init(0), cl::Hidden);
37 DebugMod("agg-antidep-debugmod",
38 cl::desc("Debug control for aggressive anti-dep breaker"),
39 cl::init(0), cl::Hidden);
41 AggressiveAntiDepState::AggressiveAntiDepState(const unsigned TargetRegs,
42 MachineBasicBlock *BB) :
43 NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0) {
45 const unsigned BBSize = BB->size();
46 for (unsigned i = 0; i < NumTargetRegs; ++i) {
47 // Initialize all registers to be in their own group. Initially we
48 // assign the register to the same-indexed GroupNode.
49 GroupNodeIndices[i] = i;
50 // Initialize the indices to indicate that no registers are live.
52 DefIndices[i] = BBSize;
56 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg)
58 unsigned Node = GroupNodeIndices[Reg];
59 while (GroupNodes[Node] != Node)
60 Node = GroupNodes[Node];
65 void AggressiveAntiDepState::GetGroupRegs(
67 std::vector<unsigned> &Regs,
68 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs)
70 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
71 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
76 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2)
78 assert(GroupNodes[0] == 0 && "GroupNode 0 not parent!");
79 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
81 // find group for each register
82 unsigned Group1 = GetGroup(Reg1);
83 unsigned Group2 = GetGroup(Reg2);
85 // if either group is 0, then that must become the parent
86 unsigned Parent = (Group1 == 0) ? Group1 : Group2;
87 unsigned Other = (Parent == Group1) ? Group2 : Group1;
88 GroupNodes.at(Other) = Parent;
92 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
94 // Create a new GroupNode for Reg. Reg's existing GroupNode must
95 // stay as is because there could be other GroupNodes referring to
97 unsigned idx = GroupNodes.size();
98 GroupNodes.push_back(idx);
99 GroupNodeIndices[Reg] = idx;
103 bool AggressiveAntiDepState::IsLive(unsigned Reg)
105 // KillIndex must be defined and DefIndex not defined for a register
107 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
112 AggressiveAntiDepBreaker::
113 AggressiveAntiDepBreaker(MachineFunction& MFi,
114 TargetSubtarget::RegClassVector& CriticalPathRCs) :
115 AntiDepBreaker(), MF(MFi),
116 MRI(MF.getRegInfo()),
117 TRI(MF.getTarget().getRegisterInfo()),
118 AllocatableSet(TRI->getAllocatableSet(MF)),
120 /* Collect a bitset of all registers that are only broken if they
121 are on the critical path. */
122 for (unsigned i = 0, e = CriticalPathRCs.size(); i < e; ++i) {
123 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]);
124 if (CriticalPathSet.none())
125 CriticalPathSet = CPSet;
127 CriticalPathSet |= CPSet;
130 DEBUG(dbgs() << "AntiDep Critical-Path Registers:");
131 DEBUG(for (int r = CriticalPathSet.find_first(); r != -1;
132 r = CriticalPathSet.find_next(r))
133 dbgs() << " " << TRI->getName(r));
134 DEBUG(dbgs() << '\n');
137 AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() {
141 void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
142 assert(State == NULL);
143 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
145 bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn());
146 unsigned *KillIndices = State->GetKillIndices();
147 unsigned *DefIndices = State->GetDefIndices();
149 // Determine the live-out physregs for this block.
151 // In a return block, examine the function live-out regs.
152 for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
153 E = MRI.liveout_end(); I != E; ++I) {
155 State->UnionGroups(Reg, 0);
156 KillIndices[Reg] = BB->size();
157 DefIndices[Reg] = ~0u;
158 // Repeat, for all aliases.
159 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
160 unsigned AliasReg = *Alias;
161 State->UnionGroups(AliasReg, 0);
162 KillIndices[AliasReg] = BB->size();
163 DefIndices[AliasReg] = ~0u;
167 // In a non-return block, examine the live-in regs of all successors.
168 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
169 SE = BB->succ_end(); SI != SE; ++SI)
170 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
171 E = (*SI)->livein_end(); I != E; ++I) {
173 State->UnionGroups(Reg, 0);
174 KillIndices[Reg] = BB->size();
175 DefIndices[Reg] = ~0u;
176 // Repeat, for all aliases.
177 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
178 unsigned AliasReg = *Alias;
179 State->UnionGroups(AliasReg, 0);
180 KillIndices[AliasReg] = BB->size();
181 DefIndices[AliasReg] = ~0u;
186 // Mark live-out callee-saved registers. In a return block this is
187 // all callee-saved registers. In non-return this is any
188 // callee-saved register that is not saved in the prolog.
189 const MachineFrameInfo *MFI = MF.getFrameInfo();
190 BitVector Pristine = MFI->getPristineRegs(BB);
191 for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
193 if (!IsReturnBlock && !Pristine.test(Reg)) continue;
194 State->UnionGroups(Reg, 0);
195 KillIndices[Reg] = BB->size();
196 DefIndices[Reg] = ~0u;
197 // Repeat, for all aliases.
198 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
199 unsigned AliasReg = *Alias;
200 State->UnionGroups(AliasReg, 0);
201 KillIndices[AliasReg] = BB->size();
202 DefIndices[AliasReg] = ~0u;
207 void AggressiveAntiDepBreaker::FinishBlock() {
212 void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
213 unsigned InsertPosIndex) {
214 assert(Count < InsertPosIndex && "Instruction index out of expected range!");
216 std::set<unsigned> PassthruRegs;
217 GetPassthruRegs(MI, PassthruRegs);
218 PrescanInstruction(MI, Count, PassthruRegs);
219 ScanInstruction(MI, Count);
221 DEBUG(dbgs() << "Observe: ");
223 DEBUG(dbgs() << "\tRegs:");
225 unsigned *DefIndices = State->GetDefIndices();
226 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
227 // If Reg is current live, then mark that it can't be renamed as
228 // we don't know the extent of its live-range anymore (now that it
229 // has been scheduled). If it is not live but was defined in the
230 // previous schedule region, then set its def index to the most
231 // conservative location (i.e. the beginning of the previous
233 if (State->IsLive(Reg)) {
234 DEBUG(if (State->GetGroup(Reg) != 0)
235 dbgs() << " " << TRI->getName(Reg) << "=g" <<
236 State->GetGroup(Reg) << "->g0(region live-out)");
237 State->UnionGroups(Reg, 0);
238 } else if ((DefIndices[Reg] < InsertPosIndex)
239 && (DefIndices[Reg] >= Count)) {
240 DefIndices[Reg] = Count;
243 DEBUG(dbgs() << '\n');
246 bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr *MI,
249 if (!MO.isReg() || !MO.isImplicit())
252 unsigned Reg = MO.getReg();
256 MachineOperand *Op = NULL;
258 Op = MI->findRegisterUseOperand(Reg, true);
260 Op = MI->findRegisterDefOperand(Reg);
262 return((Op != NULL) && Op->isImplicit());
265 void AggressiveAntiDepBreaker::GetPassthruRegs(MachineInstr *MI,
266 std::set<unsigned>& PassthruRegs) {
267 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
268 MachineOperand &MO = MI->getOperand(i);
269 if (!MO.isReg()) continue;
270 if ((MO.isDef() && MI->isRegTiedToUseOperand(i)) ||
271 IsImplicitDefUse(MI, MO)) {
272 const unsigned Reg = MO.getReg();
273 PassthruRegs.insert(Reg);
274 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
276 PassthruRegs.insert(*Subreg);
282 /// AntiDepEdges - Return in Edges the anti- and output- dependencies
283 /// in SU that we want to consider for breaking.
284 static void AntiDepEdges(SUnit *SU, std::vector<SDep*>& Edges) {
285 SmallSet<unsigned, 4> RegSet;
286 for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
288 if ((P->getKind() == SDep::Anti) || (P->getKind() == SDep::Output)) {
289 unsigned Reg = P->getReg();
290 if (RegSet.count(Reg) == 0) {
291 Edges.push_back(&*P);
298 /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
300 static SUnit *CriticalPathStep(SUnit *SU) {
302 unsigned NextDepth = 0;
303 // Find the predecessor edge with the greatest depth.
305 for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
307 SUnit *PredSU = P->getSUnit();
308 unsigned PredLatency = P->getLatency();
309 unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
310 // In the case of a latency tie, prefer an anti-dependency edge over
311 // other types of edges.
312 if (NextDepth < PredTotalLatency ||
313 (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
314 NextDepth = PredTotalLatency;
320 return (Next) ? Next->getSUnit() : 0;
323 void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
326 const char *footer) {
327 unsigned *KillIndices = State->GetKillIndices();
328 unsigned *DefIndices = State->GetDefIndices();
329 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
330 RegRefs = State->GetRegRefs();
332 if (!State->IsLive(Reg)) {
333 KillIndices[Reg] = KillIdx;
334 DefIndices[Reg] = ~0u;
336 State->LeaveGroup(Reg);
337 DEBUG(if (header != NULL) {
338 dbgs() << header << TRI->getName(Reg); header = NULL; });
339 DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
341 // Repeat for subregisters.
342 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
344 unsigned SubregReg = *Subreg;
345 if (!State->IsLive(SubregReg)) {
346 KillIndices[SubregReg] = KillIdx;
347 DefIndices[SubregReg] = ~0u;
348 RegRefs.erase(SubregReg);
349 State->LeaveGroup(SubregReg);
350 DEBUG(if (header != NULL) {
351 dbgs() << header << TRI->getName(Reg); header = NULL; });
352 DEBUG(dbgs() << " " << TRI->getName(SubregReg) << "->g" <<
353 State->GetGroup(SubregReg) << tag);
357 DEBUG(if ((header == NULL) && (footer != NULL)) dbgs() << footer);
360 void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI,
362 std::set<unsigned>& PassthruRegs)
364 unsigned *DefIndices = State->GetDefIndices();
365 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
366 RegRefs = State->GetRegRefs();
368 // Handle dead defs by simulating a last-use of the register just
369 // after the def. A dead def can occur because the def is truely
370 // dead, or because only a subregister is live at the def. If we
371 // don't do this the dead def will be incorrectly merged into the
373 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
374 MachineOperand &MO = MI->getOperand(i);
375 if (!MO.isReg() || !MO.isDef()) continue;
376 unsigned Reg = MO.getReg();
377 if (Reg == 0) continue;
379 HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
382 DEBUG(dbgs() << "\tDef Groups:");
383 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
384 MachineOperand &MO = MI->getOperand(i);
385 if (!MO.isReg() || !MO.isDef()) continue;
386 unsigned Reg = MO.getReg();
387 if (Reg == 0) continue;
389 DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
391 // If MI's defs have a special allocation requirement, don't allow
392 // any def registers to be changed. Also assume all registers
393 // defined in a call must not be changed (ABI).
394 if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq()) {
395 DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
396 State->UnionGroups(Reg, 0);
399 // Any aliased that are live at this point are completely or
400 // partially defined here, so group those aliases with Reg.
401 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
402 unsigned AliasReg = *Alias;
403 if (State->IsLive(AliasReg)) {
404 State->UnionGroups(Reg, AliasReg);
405 DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " <<
406 TRI->getName(AliasReg) << ")");
410 // Note register reference...
411 const TargetRegisterClass *RC = NULL;
412 if (i < MI->getDesc().getNumOperands())
413 RC = MI->getDesc().OpInfo[i].getRegClass(TRI);
414 AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
415 RegRefs.insert(std::make_pair(Reg, RR));
418 DEBUG(dbgs() << '\n');
420 // Scan the register defs for this instruction and update
422 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
423 MachineOperand &MO = MI->getOperand(i);
424 if (!MO.isReg() || !MO.isDef()) continue;
425 unsigned Reg = MO.getReg();
426 if (Reg == 0) continue;
427 // Ignore KILLs and passthru registers for liveness...
428 if (MI->isKill() || (PassthruRegs.count(Reg) != 0))
431 // Update def for Reg and aliases.
432 DefIndices[Reg] = Count;
433 for (const unsigned *Alias = TRI->getAliasSet(Reg);
435 unsigned AliasReg = *Alias;
436 DefIndices[AliasReg] = Count;
441 void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
443 DEBUG(dbgs() << "\tUse Groups:");
444 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
445 RegRefs = State->GetRegRefs();
447 // Scan the register uses for this instruction and update
448 // live-ranges, groups and RegRefs.
449 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
450 MachineOperand &MO = MI->getOperand(i);
451 if (!MO.isReg() || !MO.isUse()) continue;
452 unsigned Reg = MO.getReg();
453 if (Reg == 0) continue;
455 DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" <<
456 State->GetGroup(Reg));
458 // It wasn't previously live but now it is, this is a kill. Forget
459 // the previous live-range information and start a new live-range
461 HandleLastUse(Reg, Count, "(last-use)");
463 // If MI's uses have special allocation requirement, don't allow
464 // any use registers to be changed. Also assume all registers
465 // used in a call must not be changed (ABI).
466 if (MI->getDesc().isCall() || MI->getDesc().hasExtraSrcRegAllocReq()) {
467 DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
468 State->UnionGroups(Reg, 0);
471 // Note register reference...
472 const TargetRegisterClass *RC = NULL;
473 if (i < MI->getDesc().getNumOperands())
474 RC = MI->getDesc().OpInfo[i].getRegClass(TRI);
475 AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
476 RegRefs.insert(std::make_pair(Reg, RR));
479 DEBUG(dbgs() << '\n');
481 // Form a group of all defs and uses of a KILL instruction to ensure
482 // that all registers are renamed as a group.
484 DEBUG(dbgs() << "\tKill Group:");
486 unsigned FirstReg = 0;
487 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
488 MachineOperand &MO = MI->getOperand(i);
489 if (!MO.isReg()) continue;
490 unsigned Reg = MO.getReg();
491 if (Reg == 0) continue;
494 DEBUG(dbgs() << "=" << TRI->getName(Reg));
495 State->UnionGroups(FirstReg, Reg);
497 DEBUG(dbgs() << " " << TRI->getName(Reg));
502 DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
506 BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
507 BitVector BV(TRI->getNumRegs(), false);
510 // Check all references that need rewriting for Reg. For each, use
511 // the corresponding register class to narrow the set of registers
512 // that are appropriate for renaming.
513 std::pair<std::multimap<unsigned,
514 AggressiveAntiDepState::RegisterReference>::iterator,
515 std::multimap<unsigned,
516 AggressiveAntiDepState::RegisterReference>::iterator>
517 Range = State->GetRegRefs().equal_range(Reg);
518 for (std::multimap<unsigned,
519 AggressiveAntiDepState::RegisterReference>::iterator Q = Range.first,
520 QE = Range.second; Q != QE; ++Q) {
521 const TargetRegisterClass *RC = Q->second.RC;
522 if (RC == NULL) continue;
524 BitVector RCBV = TRI->getAllocatableSet(MF, RC);
532 DEBUG(dbgs() << " " << RC->getName());
538 bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
539 unsigned AntiDepGroupIndex,
540 RenameOrderType& RenameOrder,
541 std::map<unsigned, unsigned> &RenameMap) {
542 unsigned *KillIndices = State->GetKillIndices();
543 unsigned *DefIndices = State->GetDefIndices();
544 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
545 RegRefs = State->GetRegRefs();
547 // Collect all referenced registers in the same group as
548 // AntiDepReg. These all need to be renamed together if we are to
549 // break the anti-dependence.
550 std::vector<unsigned> Regs;
551 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
552 assert(Regs.size() > 0 && "Empty register group!");
553 if (Regs.size() == 0)
556 // Find the "superest" register in the group. At the same time,
557 // collect the BitVector of registers that can be used to rename
559 DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex
561 std::map<unsigned, BitVector> RenameRegisterMap;
562 unsigned SuperReg = 0;
563 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
564 unsigned Reg = Regs[i];
565 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
568 // If Reg has any references, then collect possible rename regs
569 if (RegRefs.count(Reg) > 0) {
570 DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":");
572 BitVector BV = GetRenameRegisters(Reg);
573 RenameRegisterMap.insert(std::pair<unsigned, BitVector>(Reg, BV));
575 DEBUG(dbgs() << " ::");
576 DEBUG(for (int r = BV.find_first(); r != -1; r = BV.find_next(r))
577 dbgs() << " " << TRI->getName(r));
578 DEBUG(dbgs() << "\n");
582 // All group registers should be a subreg of SuperReg.
583 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
584 unsigned Reg = Regs[i];
585 if (Reg == SuperReg) continue;
586 bool IsSub = TRI->isSubRegister(SuperReg, Reg);
587 assert(IsSub && "Expecting group subregister");
593 // If DebugDiv > 0 then only rename (renamecnt % DebugDiv) == DebugMod
595 static int renamecnt = 0;
596 if (renamecnt++ % DebugDiv != DebugMod)
599 dbgs() << "*** Performing rename " << TRI->getName(SuperReg) <<
604 // Check each possible rename register for SuperReg in round-robin
605 // order. If that register is available, and the corresponding
606 // registers are available for the other group subregisters, then we
607 // can use those registers to rename.
608 const TargetRegisterClass *SuperRC =
609 TRI->getPhysicalRegisterRegClass(SuperReg, MVT::Other);
611 const TargetRegisterClass::iterator RB = SuperRC->allocation_order_begin(MF);
612 const TargetRegisterClass::iterator RE = SuperRC->allocation_order_end(MF);
614 DEBUG(dbgs() << "\tEmpty Super Regclass!!\n");
618 DEBUG(dbgs() << "\tFind Registers:");
620 if (RenameOrder.count(SuperRC) == 0)
621 RenameOrder.insert(RenameOrderType::value_type(SuperRC, RE));
623 const TargetRegisterClass::iterator OrigR = RenameOrder[SuperRC];
624 const TargetRegisterClass::iterator EndR = ((OrigR == RE) ? RB : OrigR);
625 TargetRegisterClass::iterator R = OrigR;
629 const unsigned NewSuperReg = *R;
630 // Don't replace a register with itself.
631 if (NewSuperReg == SuperReg) continue;
633 DEBUG(dbgs() << " [" << TRI->getName(NewSuperReg) << ':');
636 // For each referenced group register (which must be a SuperReg or
637 // a subregister of SuperReg), find the corresponding subregister
638 // of NewSuperReg and make sure it is free to be renamed.
639 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
640 unsigned Reg = Regs[i];
642 if (Reg == SuperReg) {
643 NewReg = NewSuperReg;
645 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg);
646 if (NewSubRegIdx != 0)
647 NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx);
650 DEBUG(dbgs() << " " << TRI->getName(NewReg));
652 // Check if Reg can be renamed to NewReg.
653 BitVector BV = RenameRegisterMap[Reg];
654 if (!BV.test(NewReg)) {
655 DEBUG(dbgs() << "(no rename)");
659 // If NewReg is dead and NewReg's most recent def is not before
660 // Regs's kill, it's safe to replace Reg with NewReg. We
661 // must also check all aliases of NewReg, because we can't define a
662 // register when any sub or super is already live.
663 if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) {
664 DEBUG(dbgs() << "(live)");
668 for (const unsigned *Alias = TRI->getAliasSet(NewReg);
670 unsigned AliasReg = *Alias;
671 if (State->IsLive(AliasReg) ||
672 (KillIndices[Reg] > DefIndices[AliasReg])) {
673 DEBUG(dbgs() << "(alias " << TRI->getName(AliasReg) << " live)");
682 // Record that 'Reg' can be renamed to 'NewReg'.
683 RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg));
686 // If we fall-out here, then every register in the group can be
687 // renamed, as recorded in RenameMap.
688 RenameOrder.erase(SuperRC);
689 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R));
690 DEBUG(dbgs() << "]\n");
694 DEBUG(dbgs() << ']');
697 DEBUG(dbgs() << '\n');
699 // No registers are free and available!
703 /// BreakAntiDependencies - Identifiy anti-dependencies within the
704 /// ScheduleDAG and break them by renaming registers.
706 unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
707 std::vector<SUnit>& SUnits,
708 MachineBasicBlock::iterator& Begin,
709 MachineBasicBlock::iterator& End,
710 unsigned InsertPosIndex) {
711 unsigned *KillIndices = State->GetKillIndices();
712 unsigned *DefIndices = State->GetDefIndices();
713 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
714 RegRefs = State->GetRegRefs();
716 // The code below assumes that there is at least one instruction,
717 // so just duck out immediately if the block is empty.
718 if (SUnits.empty()) return 0;
720 // For each regclass the next register to use for renaming.
721 RenameOrderType RenameOrder;
723 // ...need a map from MI to SUnit.
724 std::map<MachineInstr *, SUnit *> MISUnitMap;
725 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
726 SUnit *SU = &SUnits[i];
727 MISUnitMap.insert(std::pair<MachineInstr *, SUnit *>(SU->getInstr(), SU));
730 // Track progress along the critical path through the SUnit graph as
731 // we walk the instructions. This is needed for regclasses that only
732 // break critical-path anti-dependencies.
733 SUnit *CriticalPathSU = 0;
734 MachineInstr *CriticalPathMI = 0;
735 if (CriticalPathSet.any()) {
736 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
737 SUnit *SU = &SUnits[i];
738 if (!CriticalPathSU ||
739 ((SU->getDepth() + SU->Latency) >
740 (CriticalPathSU->getDepth() + CriticalPathSU->Latency))) {
745 CriticalPathMI = CriticalPathSU->getInstr();
749 DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n");
750 DEBUG(dbgs() << "Available regs:");
751 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
752 if (!State->IsLive(Reg))
753 DEBUG(dbgs() << " " << TRI->getName(Reg));
755 DEBUG(dbgs() << '\n');
758 // Attempt to break anti-dependence edges. Walk the instructions
759 // from the bottom up, tracking information about liveness as we go
760 // to help determine which registers are available.
762 unsigned Count = InsertPosIndex - 1;
763 for (MachineBasicBlock::iterator I = End, E = Begin;
765 MachineInstr *MI = --I;
767 DEBUG(dbgs() << "Anti: ");
770 std::set<unsigned> PassthruRegs;
771 GetPassthruRegs(MI, PassthruRegs);
773 // Process the defs in MI...
774 PrescanInstruction(MI, Count, PassthruRegs);
776 // The dependence edges that represent anti- and output-
777 // dependencies that are candidates for breaking.
778 std::vector<SDep*> Edges;
779 SUnit *PathSU = MISUnitMap[MI];
780 AntiDepEdges(PathSU, Edges);
782 // If MI is not on the critical path, then we don't rename
783 // registers in the CriticalPathSet.
784 BitVector *ExcludeRegs = NULL;
785 if (MI == CriticalPathMI) {
786 CriticalPathSU = CriticalPathStep(CriticalPathSU);
787 CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : 0;
789 ExcludeRegs = &CriticalPathSet;
792 // Ignore KILL instructions (they form a group in ScanInstruction
793 // but don't cause any anti-dependence breaking themselves)
795 // Attempt to break each anti-dependency...
796 for (unsigned i = 0, e = Edges.size(); i != e; ++i) {
797 SDep *Edge = Edges[i];
798 SUnit *NextSU = Edge->getSUnit();
800 if ((Edge->getKind() != SDep::Anti) &&
801 (Edge->getKind() != SDep::Output)) continue;
803 unsigned AntiDepReg = Edge->getReg();
804 DEBUG(dbgs() << "\tAntidep reg: " << TRI->getName(AntiDepReg));
805 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
807 if (!AllocatableSet.test(AntiDepReg)) {
808 // Don't break anti-dependencies on non-allocatable registers.
809 DEBUG(dbgs() << " (non-allocatable)\n");
811 } else if ((ExcludeRegs != NULL) && ExcludeRegs->test(AntiDepReg)) {
812 // Don't break anti-dependencies for critical path registers
813 // if not on the critical path
814 DEBUG(dbgs() << " (not critical-path)\n");
816 } else if (PassthruRegs.count(AntiDepReg) != 0) {
817 // If the anti-dep register liveness "passes-thru", then
818 // don't try to change it. It will be changed along with
819 // the use if required to break an earlier antidep.
820 DEBUG(dbgs() << " (passthru)\n");
823 // No anti-dep breaking for implicit deps
824 MachineOperand *AntiDepOp = MI->findRegisterDefOperand(AntiDepReg);
825 assert(AntiDepOp != NULL &&
826 "Can't find index for defined register operand");
827 if ((AntiDepOp == NULL) || AntiDepOp->isImplicit()) {
828 DEBUG(dbgs() << " (implicit)\n");
832 // If the SUnit has other dependencies on the SUnit that
833 // it anti-depends on, don't bother breaking the
834 // anti-dependency since those edges would prevent such
835 // units from being scheduled past each other
838 // Also, if there are dependencies on other SUnits with the
839 // same register as the anti-dependency, don't attempt to
841 for (SUnit::pred_iterator P = PathSU->Preds.begin(),
842 PE = PathSU->Preds.end(); P != PE; ++P) {
843 if (P->getSUnit() == NextSU ?
844 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
845 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
850 for (SUnit::pred_iterator P = PathSU->Preds.begin(),
851 PE = PathSU->Preds.end(); P != PE; ++P) {
852 if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) &&
853 (P->getKind() != SDep::Output)) {
854 DEBUG(dbgs() << " (real dependency)\n");
857 } else if ((P->getSUnit() != NextSU) &&
858 (P->getKind() == SDep::Data) &&
859 (P->getReg() == AntiDepReg)) {
860 DEBUG(dbgs() << " (other dependency)\n");
866 if (AntiDepReg == 0) continue;
869 assert(AntiDepReg != 0);
870 if (AntiDepReg == 0) continue;
872 // Determine AntiDepReg's register group.
873 const unsigned GroupIndex = State->GetGroup(AntiDepReg);
874 if (GroupIndex == 0) {
875 DEBUG(dbgs() << " (zero group)\n");
879 DEBUG(dbgs() << '\n');
881 // Look for a suitable register to use to break the anti-dependence.
882 std::map<unsigned, unsigned> RenameMap;
883 if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) {
884 DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
885 << TRI->getName(AntiDepReg) << ":");
887 // Handle each group register...
888 for (std::map<unsigned, unsigned>::iterator
889 S = RenameMap.begin(), E = RenameMap.end(); S != E; ++S) {
890 unsigned CurrReg = S->first;
891 unsigned NewReg = S->second;
893 DEBUG(dbgs() << " " << TRI->getName(CurrReg) << "->" <<
894 TRI->getName(NewReg) << "(" <<
895 RegRefs.count(CurrReg) << " refs)");
897 // Update the references to the old register CurrReg to
898 // refer to the new register NewReg.
899 std::pair<std::multimap<unsigned,
900 AggressiveAntiDepState::RegisterReference>::iterator,
901 std::multimap<unsigned,
902 AggressiveAntiDepState::RegisterReference>::iterator>
903 Range = RegRefs.equal_range(CurrReg);
904 for (std::multimap<unsigned,
905 AggressiveAntiDepState::RegisterReference>::iterator
906 Q = Range.first, QE = Range.second; Q != QE; ++Q) {
907 Q->second.Operand->setReg(NewReg);
910 // We just went back in time and modified history; the
911 // liveness information for CurrReg is now inconsistent. Set
912 // the state as if it were dead.
913 State->UnionGroups(NewReg, 0);
914 RegRefs.erase(NewReg);
915 DefIndices[NewReg] = DefIndices[CurrReg];
916 KillIndices[NewReg] = KillIndices[CurrReg];
918 State->UnionGroups(CurrReg, 0);
919 RegRefs.erase(CurrReg);
920 DefIndices[CurrReg] = KillIndices[CurrReg];
921 KillIndices[CurrReg] = ~0u;
922 assert(((KillIndices[CurrReg] == ~0u) !=
923 (DefIndices[CurrReg] == ~0u)) &&
924 "Kill and Def maps aren't consistent for AntiDepReg!");
928 DEBUG(dbgs() << '\n');
933 ScanInstruction(MI, Count);