1 //===----- AggressiveAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AggressiveAntiDepBreaker class, which
11 // implements register anti-dependence breaking during post-RA
12 // scheduling. It attempts to break all anti-dependencies within a
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "aggressive-antidep"
18 #include "AggressiveAntiDepBreaker.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
32 AntiDepTrials("agg-antidep-trials",
33 cl::desc("Maximum number of anti-dependency breaking passes"),
34 cl::init(2), cl::Hidden);
36 AggressiveAntiDepState::AggressiveAntiDepState(MachineBasicBlock *BB) :
37 GroupNodes(TargetRegisterInfo::FirstVirtualRegister, 0) {
38 // Initialize all registers to be in their own group. Initially we
39 // assign the register to the same-indexed GroupNode.
40 for (unsigned i = 0; i < TargetRegisterInfo::FirstVirtualRegister; ++i)
41 GroupNodeIndices[i] = i;
43 // Initialize the indices to indicate that no registers are live.
44 std::fill(KillIndices, array_endof(KillIndices), ~0u);
45 std::fill(DefIndices, array_endof(DefIndices), BB->size());
48 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg)
50 unsigned Node = GroupNodeIndices[Reg];
51 while (GroupNodes[Node] != Node)
52 Node = GroupNodes[Node];
57 void AggressiveAntiDepState::GetGroupRegs(unsigned Group, std::vector<unsigned> &Regs)
59 for (unsigned Reg = 0; Reg != TargetRegisterInfo::FirstVirtualRegister; ++Reg) {
60 if (GetGroup(Reg) == Group)
65 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2)
67 assert(GroupNodes[0] == 0 && "GroupNode 0 not parent!");
68 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
70 // find group for each register
71 unsigned Group1 = GetGroup(Reg1);
72 unsigned Group2 = GetGroup(Reg2);
74 // if either group is 0, then that must become the parent
75 unsigned Parent = (Group1 == 0) ? Group1 : Group2;
76 unsigned Other = (Parent == Group1) ? Group2 : Group1;
77 GroupNodes.at(Other) = Parent;
81 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
83 // Create a new GroupNode for Reg. Reg's existing GroupNode must
84 // stay as is because there could be other GroupNodes referring to
86 unsigned idx = GroupNodes.size();
87 GroupNodes.push_back(idx);
88 GroupNodeIndices[Reg] = idx;
92 bool AggressiveAntiDepState::IsLive(unsigned Reg)
94 // KillIndex must be defined and DefIndex not defined for a register
96 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
101 AggressiveAntiDepBreaker::
102 AggressiveAntiDepBreaker(MachineFunction& MFi) :
103 AntiDepBreaker(), MF(MFi),
104 MRI(MF.getRegInfo()),
105 TRI(MF.getTarget().getRegisterInfo()),
106 AllocatableSet(TRI->getAllocatableSet(MF)),
107 State(NULL), SavedState(NULL) {
110 AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() {
115 unsigned AggressiveAntiDepBreaker::GetMaxTrials() {
116 if (AntiDepTrials <= 0)
118 return AntiDepTrials;
121 void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
122 assert(State == NULL);
123 State = new AggressiveAntiDepState(BB);
125 bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn());
126 unsigned *KillIndices = State->GetKillIndices();
127 unsigned *DefIndices = State->GetDefIndices();
129 // Determine the live-out physregs for this block.
131 // In a return block, examine the function live-out regs.
132 for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
133 E = MRI.liveout_end(); I != E; ++I) {
135 State->UnionGroups(Reg, 0);
136 KillIndices[Reg] = BB->size();
137 DefIndices[Reg] = ~0u;
138 // Repeat, for all aliases.
139 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
140 unsigned AliasReg = *Alias;
141 State->UnionGroups(AliasReg, 0);
142 KillIndices[AliasReg] = BB->size();
143 DefIndices[AliasReg] = ~0u;
147 // In a non-return block, examine the live-in regs of all successors.
148 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
149 SE = BB->succ_end(); SI != SE; ++SI)
150 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
151 E = (*SI)->livein_end(); I != E; ++I) {
153 State->UnionGroups(Reg, 0);
154 KillIndices[Reg] = BB->size();
155 DefIndices[Reg] = ~0u;
156 // Repeat, for all aliases.
157 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
158 unsigned AliasReg = *Alias;
159 State->UnionGroups(AliasReg, 0);
160 KillIndices[AliasReg] = BB->size();
161 DefIndices[AliasReg] = ~0u;
166 // Mark live-out callee-saved registers. In a return block this is
167 // all callee-saved registers. In non-return this is any
168 // callee-saved register that is not saved in the prolog.
169 const MachineFrameInfo *MFI = MF.getFrameInfo();
170 BitVector Pristine = MFI->getPristineRegs(BB);
171 for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
173 if (!IsReturnBlock && !Pristine.test(Reg)) continue;
174 State->UnionGroups(Reg, 0);
175 KillIndices[Reg] = BB->size();
176 DefIndices[Reg] = ~0u;
177 // Repeat, for all aliases.
178 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
179 unsigned AliasReg = *Alias;
180 State->UnionGroups(AliasReg, 0);
181 KillIndices[AliasReg] = BB->size();
182 DefIndices[AliasReg] = ~0u;
187 void AggressiveAntiDepBreaker::FinishBlock() {
194 void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
195 unsigned InsertPosIndex) {
196 assert(Count < InsertPosIndex && "Instruction index out of expected range!");
198 DEBUG(errs() << "Observe: ");
201 unsigned *DefIndices = State->GetDefIndices();
202 for (unsigned Reg = 0; Reg != TargetRegisterInfo::FirstVirtualRegister; ++Reg) {
203 // If Reg is current live, then mark that it can't be renamed as
204 // we don't know the extent of its live-range anymore (now that it
205 // has been scheduled). If it is not live but was defined in the
206 // previous schedule region, then set its def index to the most
207 // conservative location (i.e. the beginning of the previous
209 if (State->IsLive(Reg)) {
210 DEBUG(if (State->GetGroup(Reg) != 0)
211 errs() << " " << TRI->getName(Reg) << "=g" <<
212 State->GetGroup(Reg) << "->g0(region live-out)");
213 State->UnionGroups(Reg, 0);
214 } else if ((DefIndices[Reg] < InsertPosIndex) && (DefIndices[Reg] >= Count)) {
215 DefIndices[Reg] = Count;
219 std::set<unsigned> PassthruRegs;
220 GetPassthruRegs(MI, PassthruRegs);
221 PrescanInstruction(MI, Count, PassthruRegs);
222 ScanInstruction(MI, Count);
224 // We're starting a new schedule region so forget any saved state.
229 bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr *MI,
232 if (!MO.isReg() || !MO.isImplicit())
235 unsigned Reg = MO.getReg();
239 MachineOperand *Op = NULL;
241 Op = MI->findRegisterUseOperand(Reg, true);
243 Op = MI->findRegisterDefOperand(Reg);
245 return((Op != NULL) && Op->isImplicit());
248 void AggressiveAntiDepBreaker::GetPassthruRegs(MachineInstr *MI,
249 std::set<unsigned>& PassthruRegs) {
250 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
251 MachineOperand &MO = MI->getOperand(i);
252 if (!MO.isReg()) continue;
253 if ((MO.isDef() && MI->isRegTiedToUseOperand(i)) ||
254 IsImplicitDefUse(MI, MO)) {
255 const unsigned Reg = MO.getReg();
256 PassthruRegs.insert(Reg);
257 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
259 PassthruRegs.insert(*Subreg);
265 /// AntiDepPathStep - Return SUnit that SU has an anti-dependence on.
266 static void AntiDepPathStep(SUnit *SU, std::vector<SDep*>& Edges) {
267 SmallSet<unsigned, 8> Dups;
268 for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
270 if (P->getKind() == SDep::Anti) {
271 unsigned Reg = P->getReg();
272 if (Dups.count(Reg) == 0) {
273 Edges.push_back(&*P);
280 void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Count,
281 std::set<unsigned>& PassthruRegs) {
282 unsigned *DefIndices = State->GetDefIndices();
283 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
284 RegRefs = State->GetRegRefs();
286 // Scan the register defs for this instruction and update
287 // live-ranges, groups and RegRefs.
288 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
289 MachineOperand &MO = MI->getOperand(i);
290 if (!MO.isReg() || !MO.isDef()) continue;
291 unsigned Reg = MO.getReg();
292 if (Reg == 0) continue;
293 // Ignore passthru registers for liveness...
294 if (PassthruRegs.count(Reg) != 0) continue;
296 // Update Def for Reg and subregs.
297 DefIndices[Reg] = Count;
298 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
300 unsigned SubregReg = *Subreg;
301 DefIndices[SubregReg] = Count;
305 DEBUG(errs() << "\tDef Groups:");
306 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
307 MachineOperand &MO = MI->getOperand(i);
308 if (!MO.isReg() || !MO.isDef()) continue;
309 unsigned Reg = MO.getReg();
310 if (Reg == 0) continue;
312 DEBUG(errs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
314 // If MI's defs have special allocation requirement, don't allow
315 // any def registers to be changed. Also assume all registers
316 // defined in a call must not be changed (ABI).
317 if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq()) {
318 DEBUG(if (State->GetGroup(Reg) != 0) errs() << "->g0(alloc-req)");
319 State->UnionGroups(Reg, 0);
322 // Any aliased that are live at this point are completely or
323 // partially defined here, so group those subregisters with Reg.
324 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
325 unsigned AliasReg = *Alias;
326 if (State->IsLive(AliasReg)) {
327 State->UnionGroups(Reg, AliasReg);
328 DEBUG(errs() << "->g" << State->GetGroup(Reg) << "(via " <<
329 TRI->getName(AliasReg) << ")");
333 // Note register reference...
334 const TargetRegisterClass *RC = NULL;
335 if (i < MI->getDesc().getNumOperands())
336 RC = MI->getDesc().OpInfo[i].getRegClass(TRI);
337 AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
338 RegRefs.insert(std::make_pair(Reg, RR));
341 DEBUG(errs() << '\n');
344 void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
346 DEBUG(errs() << "\tUse Groups:");
347 unsigned *KillIndices = State->GetKillIndices();
348 unsigned *DefIndices = State->GetDefIndices();
349 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
350 RegRefs = State->GetRegRefs();
352 // Scan the register uses for this instruction and update
353 // live-ranges, groups and RegRefs.
354 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
355 MachineOperand &MO = MI->getOperand(i);
356 if (!MO.isReg() || !MO.isUse()) continue;
357 unsigned Reg = MO.getReg();
358 if (Reg == 0) continue;
360 DEBUG(errs() << " " << TRI->getName(Reg) << "=g" <<
361 State->GetGroup(Reg));
363 // It wasn't previously live but now it is, this is a kill. Forget
364 // the previous live-range information and start a new live-range
366 if (!State->IsLive(Reg)) {
367 KillIndices[Reg] = Count;
368 DefIndices[Reg] = ~0u;
370 State->LeaveGroup(Reg);
371 DEBUG(errs() << "->g" << State->GetGroup(Reg) << "(last-use)");
373 // Repeat, for subregisters.
374 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
376 unsigned SubregReg = *Subreg;
377 if (!State->IsLive(SubregReg)) {
378 KillIndices[SubregReg] = Count;
379 DefIndices[SubregReg] = ~0u;
380 RegRefs.erase(SubregReg);
381 State->LeaveGroup(SubregReg);
382 DEBUG(errs() << " " << TRI->getName(SubregReg) << "->g" <<
383 State->GetGroup(SubregReg) << "(last-use)");
387 // If MI's uses have special allocation requirement, don't allow
388 // any use registers to be changed. Also assume all registers
389 // used in a call must not be changed (ABI).
390 if (MI->getDesc().isCall() || MI->getDesc().hasExtraSrcRegAllocReq()) {
391 DEBUG(if (State->GetGroup(Reg) != 0) errs() << "->g0(alloc-req)");
392 State->UnionGroups(Reg, 0);
395 // Note register reference...
396 const TargetRegisterClass *RC = NULL;
397 if (i < MI->getDesc().getNumOperands())
398 RC = MI->getDesc().OpInfo[i].getRegClass(TRI);
399 AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
400 RegRefs.insert(std::make_pair(Reg, RR));
403 DEBUG(errs() << '\n');
405 // Form a group of all defs and uses of a KILL instruction to ensure
406 // that all registers are renamed as a group.
407 if (MI->getOpcode() == TargetInstrInfo::KILL) {
408 DEBUG(errs() << "\tKill Group:");
410 unsigned FirstReg = 0;
411 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
412 MachineOperand &MO = MI->getOperand(i);
413 if (!MO.isReg()) continue;
414 unsigned Reg = MO.getReg();
415 if (Reg == 0) continue;
418 DEBUG(errs() << "=" << TRI->getName(Reg));
419 State->UnionGroups(FirstReg, Reg);
421 DEBUG(errs() << " " << TRI->getName(Reg));
426 DEBUG(errs() << "->g" << State->GetGroup(FirstReg) << '\n');
430 BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
431 BitVector BV(TRI->getNumRegs(), false);
434 // Check all references that need rewriting for Reg. For each, use
435 // the corresponding register class to narrow the set of registers
436 // that are appropriate for renaming.
437 std::pair<std::multimap<unsigned,
438 AggressiveAntiDepState::RegisterReference>::iterator,
439 std::multimap<unsigned,
440 AggressiveAntiDepState::RegisterReference>::iterator>
441 Range = State->GetRegRefs().equal_range(Reg);
442 for (std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>::iterator
443 Q = Range.first, QE = Range.second; Q != QE; ++Q) {
444 const TargetRegisterClass *RC = Q->second.RC;
445 if (RC == NULL) continue;
447 BitVector RCBV = TRI->getAllocatableSet(MF, RC);
455 DEBUG(errs() << " " << RC->getName());
461 bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
462 unsigned AntiDepGroupIndex,
463 std::map<unsigned, unsigned> &RenameMap) {
464 unsigned *KillIndices = State->GetKillIndices();
465 unsigned *DefIndices = State->GetDefIndices();
466 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
467 RegRefs = State->GetRegRefs();
469 // Collect all registers in the same group as AntiDepReg. These all
470 // need to be renamed together if we are to break the
472 std::vector<unsigned> Regs;
473 State->GetGroupRegs(AntiDepGroupIndex, Regs);
474 assert(Regs.size() > 0 && "Empty register group!");
475 if (Regs.size() == 0)
478 // Find the "superest" register in the group. At the same time,
479 // collect the BitVector of registers that can be used to rename
481 DEBUG(errs() << "\tRename Candidates for Group g" << AntiDepGroupIndex << ":\n");
482 std::map<unsigned, BitVector> RenameRegisterMap;
483 unsigned SuperReg = 0;
484 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
485 unsigned Reg = Regs[i];
486 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
489 // If Reg has any references, then collect possible rename regs
490 if (RegRefs.count(Reg) > 0) {
491 DEBUG(errs() << "\t\t" << TRI->getName(Reg) << ":");
493 BitVector BV = GetRenameRegisters(Reg);
494 RenameRegisterMap.insert(std::pair<unsigned, BitVector>(Reg, BV));
496 DEBUG(errs() << " ::");
497 DEBUG(for (int r = BV.find_first(); r != -1; r = BV.find_next(r))
498 errs() << " " << TRI->getName(r));
499 DEBUG(errs() << "\n");
503 // All group registers should be a subreg of SuperReg.
504 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
505 unsigned Reg = Regs[i];
506 if (Reg == SuperReg) continue;
507 bool IsSub = TRI->isSubRegister(SuperReg, Reg);
508 assert(IsSub && "Expecting group subregister");
513 // FIXME: for now just handle single register in group case...
517 // Check each possible rename register for SuperReg. If that register
518 // is available, and the corresponding registers are available for
519 // the other group subregisters, then we can use those registers to
521 DEBUG(errs() << "\tFind Register:");
522 BitVector SuperBV = RenameRegisterMap[SuperReg];
523 for (int r = SuperBV.find_first(); r != -1; r = SuperBV.find_next(r)) {
524 const unsigned Reg = (unsigned)r;
525 // Don't replace a register with itself.
526 if (Reg == SuperReg) continue;
528 DEBUG(errs() << " " << TRI->getName(Reg));
530 // If Reg is dead and Reg's most recent def is not before
531 // SuperRegs's kill, it's safe to replace SuperReg with
532 // Reg. We must also check all subregisters of Reg.
533 if (State->IsLive(Reg) || (KillIndices[SuperReg] > DefIndices[Reg])) {
534 DEBUG(errs() << "(live)");
538 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
540 unsigned SubregReg = *Subreg;
541 if (State->IsLive(SubregReg) || (KillIndices[SuperReg] > DefIndices[SubregReg])) {
542 DEBUG(errs() << "(subreg " << TRI->getName(SubregReg) << " live)");
552 DEBUG(errs() << '\n');
553 RenameMap.insert(std::pair<unsigned, unsigned>(SuperReg, Reg));
558 DEBUG(errs() << '\n');
560 // No registers are free and available!
564 /// BreakAntiDependencies - Identifiy anti-dependencies within the
565 /// ScheduleDAG and break them by renaming registers.
567 unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
568 std::vector<SUnit>& SUnits,
569 MachineBasicBlock::iterator& Begin,
570 MachineBasicBlock::iterator& End,
571 unsigned InsertPosIndex) {
572 unsigned *KillIndices = State->GetKillIndices();
573 unsigned *DefIndices = State->GetDefIndices();
574 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
575 RegRefs = State->GetRegRefs();
577 // The code below assumes that there is at least one instruction,
578 // so just duck out immediately if the block is empty.
579 if (SUnits.empty()) return false;
581 // Manage saved state to enable multiple passes...
582 if (AntiDepTrials > 1) {
583 if (SavedState == NULL) {
584 SavedState = new AggressiveAntiDepState(*State);
587 State = new AggressiveAntiDepState(*SavedState);
591 // ...need a map from MI to SUnit.
592 std::map<MachineInstr *, SUnit *> MISUnitMap;
594 DEBUG(errs() << "Breaking all anti-dependencies\n");
595 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
596 SUnit *SU = &SUnits[i];
597 MISUnitMap.insert(std::pair<MachineInstr *, SUnit *>(SU->getInstr(), SU));
602 DEBUG(errs() << "Available regs:");
603 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
604 if (!State->IsLive(Reg))
605 DEBUG(errs() << " " << TRI->getName(Reg));
607 DEBUG(errs() << '\n');
611 // Attempt to break anti-dependence edges. Walk the instructions
612 // from the bottom up, tracking information about liveness as we go
613 // to help determine which registers are available.
615 unsigned Count = InsertPosIndex - 1;
616 for (MachineBasicBlock::iterator I = End, E = Begin;
618 MachineInstr *MI = --I;
620 DEBUG(errs() << "Anti: ");
623 std::set<unsigned> PassthruRegs;
624 GetPassthruRegs(MI, PassthruRegs);
626 // Process the defs in MI...
627 PrescanInstruction(MI, Count, PassthruRegs);
629 std::vector<SDep*> Edges;
630 SUnit *PathSU = MISUnitMap[MI];
632 AntiDepPathStep(PathSU, Edges);
634 // Ignore KILL instructions (they form a group in ScanInstruction
635 // but don't cause any anti-dependence breaking themselves)
636 if (MI->getOpcode() != TargetInstrInfo::KILL) {
637 // Attempt to break each anti-dependency...
638 for (unsigned i = 0, e = Edges.size(); i != e; ++i) {
639 SDep *Edge = Edges[i];
640 SUnit *NextSU = Edge->getSUnit();
642 if (Edge->getKind() != SDep::Anti) continue;
644 unsigned AntiDepReg = Edge->getReg();
645 DEBUG(errs() << "\tAntidep reg: " << TRI->getName(AntiDepReg));
646 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
648 if (!AllocatableSet.test(AntiDepReg)) {
649 // Don't break anti-dependencies on non-allocatable registers.
650 DEBUG(errs() << " (non-allocatable)\n");
652 } else if (PassthruRegs.count(AntiDepReg) != 0) {
653 // If the anti-dep register liveness "passes-thru", then
654 // don't try to change it. It will be changed along with
655 // the use if required to break an earlier antidep.
656 DEBUG(errs() << " (passthru)\n");
659 // No anti-dep breaking for implicit deps
660 MachineOperand *AntiDepOp = MI->findRegisterDefOperand(AntiDepReg);
661 assert(AntiDepOp != NULL && "Can't find index for defined register operand");
662 if ((AntiDepOp == NULL) || AntiDepOp->isImplicit()) {
663 DEBUG(errs() << " (implicit)\n");
667 // If the SUnit has other dependencies on the SUnit that
668 // it anti-depends on, don't bother breaking the
669 // anti-dependency since those edges would prevent such
670 // units from being scheduled past each other
672 for (SUnit::pred_iterator P = PathSU->Preds.begin(),
673 PE = PathSU->Preds.end(); P != PE; ++P) {
674 if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti)) {
675 DEBUG(errs() << " (real dependency)\n");
681 if (AntiDepReg == 0) continue;
684 assert(AntiDepReg != 0);
685 if (AntiDepReg == 0) continue;
687 // Determine AntiDepReg's register group.
688 const unsigned GroupIndex = State->GetGroup(AntiDepReg);
689 if (GroupIndex == 0) {
690 DEBUG(errs() << " (zero group)\n");
694 DEBUG(errs() << '\n');
696 // Look for a suitable register to use to break the anti-dependence.
697 std::map<unsigned, unsigned> RenameMap;
698 if (FindSuitableFreeRegisters(GroupIndex, RenameMap)) {
699 DEBUG(errs() << "\tBreaking anti-dependence edge on "
700 << TRI->getName(AntiDepReg) << ":");
702 // Handle each group register...
703 for (std::map<unsigned, unsigned>::iterator
704 S = RenameMap.begin(), E = RenameMap.end(); S != E; ++S) {
705 unsigned CurrReg = S->first;
706 unsigned NewReg = S->second;
708 DEBUG(errs() << " " << TRI->getName(CurrReg) << "->" <<
709 TRI->getName(NewReg) << "(" <<
710 RegRefs.count(CurrReg) << " refs)");
712 // Update the references to the old register CurrReg to
713 // refer to the new register NewReg.
714 std::pair<std::multimap<unsigned,
715 AggressiveAntiDepState::RegisterReference>::iterator,
716 std::multimap<unsigned,
717 AggressiveAntiDepState::RegisterReference>::iterator>
718 Range = RegRefs.equal_range(CurrReg);
719 for (std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>::iterator
720 Q = Range.first, QE = Range.second; Q != QE; ++Q) {
721 Q->second.Operand->setReg(NewReg);
724 // We just went back in time and modified history; the
725 // liveness information for CurrReg is now inconsistent. Set
726 // the state as if it were dead.
727 State->UnionGroups(NewReg, 0);
728 RegRefs.erase(NewReg);
729 DefIndices[NewReg] = DefIndices[CurrReg];
730 KillIndices[NewReg] = KillIndices[CurrReg];
732 State->UnionGroups(CurrReg, 0);
733 RegRefs.erase(CurrReg);
734 DefIndices[CurrReg] = KillIndices[CurrReg];
735 KillIndices[CurrReg] = ~0u;
736 assert(((KillIndices[CurrReg] == ~0u) !=
737 (DefIndices[CurrReg] == ~0u)) &&
738 "Kill and Def maps aren't consistent for AntiDepReg!");
742 DEBUG(errs() << '\n');
747 ScanInstruction(MI, Count);