1 //=- llvm/CodeGen/AggressiveAntiDepBreaker.h - Anti-Dep Support -*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AggressiveAntiDepBreaker class, which
11 // implements register anti-dependence breaking during post-RA
12 // scheduling. It attempts to break all anti-dependencies within a
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H
18 #define LLVM_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H
20 #include "AntiDepBreaker.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/ScheduleDAG.h"
26 #include "llvm/Target/TargetSubtarget.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/ADT/BitVector.h"
29 #include "llvm/ADT/SmallSet.h"
33 /// Class AggressiveAntiDepState
34 /// Contains all the state necessary for anti-dep breaking.
35 class AggressiveAntiDepState {
37 /// RegisterReference - Information about a register reference
38 /// within a liverange
40 /// Operand - The registers operand
41 MachineOperand *Operand;
42 /// RC - The register class
43 const TargetRegisterClass *RC;
47 /// NumTargetRegs - Number of non-virtual target registers
48 /// (i.e. TRI->getNumRegs()).
49 const unsigned NumTargetRegs;
51 /// GroupNodes - Implements a disjoint-union data structure to
52 /// form register groups. A node is represented by an index into
53 /// the vector. A node can "point to" itself to indicate that it
54 /// is the parent of a group, or point to another node to indicate
55 /// that it is a member of the same group as that node.
56 std::vector<unsigned> GroupNodes;
58 /// GroupNodeIndices - For each register, the index of the GroupNode
59 /// currently representing the group that the register belongs to.
60 /// Register 0 is always represented by the 0 group, a group
61 /// composed of registers that are not eligible for anti-aliasing.
62 unsigned GroupNodeIndices[TargetRegisterInfo::FirstVirtualRegister];
64 /// RegRefs - Map registers to all their references within a live range.
65 std::multimap<unsigned, RegisterReference> RegRefs;
67 /// KillIndices - The index of the most recent kill (proceding bottom-up),
68 /// or ~0u if the register is not live.
69 unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
71 /// DefIndices - The index of the most recent complete def (proceding bottom
72 /// up), or ~0u if the register is live.
73 unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister];
76 AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB);
78 /// GetKillIndices - Return the kill indices.
79 unsigned *GetKillIndices() { return KillIndices; }
81 /// GetDefIndices - Return the define indices.
82 unsigned *GetDefIndices() { return DefIndices; }
84 /// GetRegRefs - Return the RegRefs map.
85 std::multimap<unsigned, RegisterReference>& GetRegRefs() { return RegRefs; }
87 // GetGroup - Get the group for a register. The returned value is
88 // the index of the GroupNode representing the group.
89 unsigned GetGroup(unsigned Reg);
91 // GetGroupRegs - Return a vector of the registers belonging to a
92 // group. If RegRefs is non-NULL then only included referenced registers.
95 std::vector<unsigned> &Regs,
96 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs);
98 // UnionGroups - Union Reg1's and Reg2's groups to form a new
99 // group. Return the index of the GroupNode representing the
101 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
103 // LeaveGroup - Remove a register from its current group and place
104 // it alone in its own group. Return the index of the GroupNode
105 // representing the registers new group.
106 unsigned LeaveGroup(unsigned Reg);
108 /// IsLive - Return true if Reg is live
109 bool IsLive(unsigned Reg);
113 /// Class AggressiveAntiDepBreaker
114 class AggressiveAntiDepBreaker : public AntiDepBreaker {
116 MachineRegisterInfo &MRI;
117 const TargetRegisterInfo *TRI;
119 /// AllocatableSet - The set of allocatable registers.
120 /// We'll be ignoring anti-dependencies on non-allocatable registers,
121 /// because they may not be safe to break.
122 const BitVector AllocatableSet;
124 /// CriticalPathSet - The set of registers that should only be
125 /// renamed if they are on the critical path.
126 BitVector CriticalPathSet;
128 /// State - The state used to identify and rename anti-dependence
130 AggressiveAntiDepState *State;
133 AggressiveAntiDepBreaker(MachineFunction& MFi,
134 TargetSubtarget::RegClassVector& CriticalPathRCs);
135 ~AggressiveAntiDepBreaker();
137 /// Start - Initialize anti-dep breaking for a new basic block.
138 void StartBlock(MachineBasicBlock *BB);
140 /// BreakAntiDependencies - Identifiy anti-dependencies along the critical path
141 /// of the ScheduleDAG and break them by renaming registers.
143 unsigned BreakAntiDependencies(std::vector<SUnit>& SUnits,
144 MachineBasicBlock::iterator& Begin,
145 MachineBasicBlock::iterator& End,
146 unsigned InsertPosIndex);
148 /// Observe - Update liveness information to account for the current
149 /// instruction, which will not be scheduled.
151 void Observe(MachineInstr *MI, unsigned Count, unsigned InsertPosIndex);
153 /// Finish - Finish anti-dep breaking for a basic block.
157 typedef std::map<const TargetRegisterClass *,
158 TargetRegisterClass::const_iterator> RenameOrderType;
160 /// IsImplicitDefUse - Return true if MO represents a register
161 /// that is both implicitly used and defined in MI
162 bool IsImplicitDefUse(MachineInstr *MI, MachineOperand& MO);
164 /// GetPassthruRegs - If MI implicitly def/uses a register, then
165 /// return that register and all subregisters.
166 void GetPassthruRegs(MachineInstr *MI, std::set<unsigned>& PassthruRegs);
168 void HandleLastUse(unsigned Reg, unsigned KillIdx, const char *tag,
169 const char *header =NULL, const char *footer =NULL);
171 void PrescanInstruction(MachineInstr *MI, unsigned Count,
172 std::set<unsigned>& PassthruRegs);
173 void ScanInstruction(MachineInstr *MI, unsigned Count);
174 BitVector GetRenameRegisters(unsigned Reg);
175 bool FindSuitableFreeRegisters(unsigned AntiDepGroupIndex,
176 RenameOrderType& RenameOrder,
177 std::map<unsigned, unsigned> &RenameMap);