1 //===-- AsmPrinterDwarf.cpp - AsmPrinter Dwarf Support --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the Dwarf emissions parts of AsmPrinter.
12 //===----------------------------------------------------------------------===//
14 #include "ByteStreamer.h"
15 #include "llvm/CodeGen/AsmPrinter.h"
16 #include "llvm/ADT/SmallBitVector.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/IR/DataLayout.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCSection.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/MC/MCSymbol.h"
23 #include "llvm/MC/MachineLocation.h"
24 #include "llvm/Support/Dwarf.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Target/TargetFrameLowering.h"
27 #include "llvm/Target/TargetLoweringObjectFile.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
30 #include "llvm/Target/TargetSubtargetInfo.h"
33 #define DEBUG_TYPE "asm-printer"
35 //===----------------------------------------------------------------------===//
36 // Dwarf Emission Helper Routines
37 //===----------------------------------------------------------------------===//
39 /// EmitSLEB128 - emit the specified signed leb128 value.
40 void AsmPrinter::EmitSLEB128(int64_t Value, const char *Desc) const {
41 if (isVerbose() && Desc)
42 OutStreamer.AddComment(Desc);
44 OutStreamer.EmitSLEB128IntValue(Value);
47 /// EmitULEB128 - emit the specified signed leb128 value.
48 void AsmPrinter::EmitULEB128(uint64_t Value, const char *Desc,
49 unsigned PadTo) const {
50 if (isVerbose() && Desc)
51 OutStreamer.AddComment(Desc);
53 OutStreamer.EmitULEB128IntValue(Value, PadTo);
56 /// EmitCFAByte - Emit a .byte 42 directive for a DW_CFA_xxx value.
57 void AsmPrinter::EmitCFAByte(unsigned Val) const {
59 if (Val >= dwarf::DW_CFA_offset && Val < dwarf::DW_CFA_offset + 64)
60 OutStreamer.AddComment("DW_CFA_offset + Reg (" +
61 Twine(Val - dwarf::DW_CFA_offset) + ")");
63 OutStreamer.AddComment(dwarf::CallFrameString(Val));
65 OutStreamer.EmitIntValue(Val, 1);
68 static const char *DecodeDWARFEncoding(unsigned Encoding) {
70 case dwarf::DW_EH_PE_absptr:
72 case dwarf::DW_EH_PE_omit:
74 case dwarf::DW_EH_PE_pcrel:
76 case dwarf::DW_EH_PE_udata4:
78 case dwarf::DW_EH_PE_udata8:
80 case dwarf::DW_EH_PE_sdata4:
82 case dwarf::DW_EH_PE_sdata8:
84 case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata4:
85 return "pcrel udata4";
86 case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4:
87 return "pcrel sdata4";
88 case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata8:
89 return "pcrel udata8";
90 case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata8:
91 return "pcrel sdata8";
92 case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata4
94 return "indirect pcrel udata4";
95 case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4
97 return "indirect pcrel sdata4";
98 case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata8
100 return "indirect pcrel udata8";
101 case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata8
103 return "indirect pcrel sdata8";
106 return "<unknown encoding>";
109 /// EmitEncodingByte - Emit a .byte 42 directive that corresponds to an
110 /// encoding. If verbose assembly output is enabled, we output comments
111 /// describing the encoding. Desc is an optional string saying what the
112 /// encoding is specifying (e.g. "LSDA").
113 void AsmPrinter::EmitEncodingByte(unsigned Val, const char *Desc) const {
116 OutStreamer.AddComment(Twine(Desc) + " Encoding = " +
117 Twine(DecodeDWARFEncoding(Val)));
119 OutStreamer.AddComment(Twine("Encoding = ") + DecodeDWARFEncoding(Val));
122 OutStreamer.EmitIntValue(Val, 1);
125 /// GetSizeOfEncodedValue - Return the size of the encoding in bytes.
126 unsigned AsmPrinter::GetSizeOfEncodedValue(unsigned Encoding) const {
127 if (Encoding == dwarf::DW_EH_PE_omit)
130 switch (Encoding & 0x07) {
132 llvm_unreachable("Invalid encoded value.");
133 case dwarf::DW_EH_PE_absptr:
134 return TM.getSubtargetImpl()->getDataLayout()->getPointerSize();
135 case dwarf::DW_EH_PE_udata2:
137 case dwarf::DW_EH_PE_udata4:
139 case dwarf::DW_EH_PE_udata8:
144 void AsmPrinter::EmitTTypeReference(const GlobalValue *GV,
145 unsigned Encoding) const {
147 const TargetLoweringObjectFile &TLOF = getObjFileLowering();
150 TLOF.getTTypeGlobalReference(GV, Encoding, *Mang, TM, MMI, OutStreamer);
151 OutStreamer.EmitValue(Exp, GetSizeOfEncodedValue(Encoding));
153 OutStreamer.EmitIntValue(0, GetSizeOfEncodedValue(Encoding));
156 /// EmitSectionOffset - Emit the 4-byte offset of Label from the start of its
157 /// section. This can be done with a special directive if the target supports
158 /// it (e.g. cygwin) or by emitting it as an offset from a label at the start
161 /// SectionLabel is a temporary label emitted at the start of the section that
163 void AsmPrinter::EmitSectionOffset(const MCSymbol *Label,
164 const MCSymbol *SectionLabel) const {
165 // On COFF targets, we have to emit the special .secrel32 directive.
166 if (MAI->needsDwarfSectionOffsetDirective()) {
167 OutStreamer.EmitCOFFSecRel32(Label);
171 // Get the section that we're referring to, based on SectionLabel.
172 const MCSection &Section = SectionLabel->getSection();
174 // If Label has already been emitted, verify that it is in the same section as
175 // section label for sanity.
176 assert((!Label->isInSection() || &Label->getSection() == &Section) &&
177 "Section offset using wrong section base for label");
179 // If the section in question will end up with an address of 0 anyway, we can
180 // just emit an absolute reference to save a relocation.
181 if (Section.isBaseAddressKnownZero()) {
182 OutStreamer.EmitSymbolValue(Label, 4);
186 // Otherwise, emit it as a label difference from the start of the section.
187 EmitLabelDifference(Label, SectionLabel, 4);
190 /// Emit a dwarf register operation.
191 static void emitDwarfRegOp(ByteStreamer &Streamer, int Reg) {
194 Streamer.EmitInt8(dwarf::DW_OP_reg0 + Reg,
195 dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
197 Streamer.EmitInt8(dwarf::DW_OP_regx, "DW_OP_regx");
198 Streamer.EmitULEB128(Reg, Twine(Reg));
202 /// Emit an (double-)indirect dwarf register operation.
203 static void emitDwarfRegOpIndirect(ByteStreamer &Streamer, int Reg, int Offset,
207 Streamer.EmitInt8(dwarf::DW_OP_breg0 + Reg,
208 dwarf::OperationEncodingString(dwarf::DW_OP_breg0 + Reg));
210 Streamer.EmitInt8(dwarf::DW_OP_bregx, "DW_OP_bregx");
211 Streamer.EmitULEB128(Reg, Twine(Reg));
213 Streamer.EmitSLEB128(Offset);
215 Streamer.EmitInt8(dwarf::DW_OP_deref, "DW_OP_deref");
218 void AsmPrinter::EmitDwarfOpPiece(ByteStreamer &Streamer, unsigned SizeInBits,
219 unsigned OffsetInBits) const {
220 assert(SizeInBits > 0 && "piece has size zero");
221 const unsigned SizeOfByte = 8;
222 if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
223 Streamer.EmitInt8(dwarf::DW_OP_bit_piece, "DW_OP_bit_piece");
224 Streamer.EmitULEB128(SizeInBits, Twine(SizeInBits));
225 Streamer.EmitULEB128(OffsetInBits, Twine(OffsetInBits));
227 Streamer.EmitInt8(dwarf::DW_OP_piece, "DW_OP_piece");
228 unsigned ByteSize = SizeInBits / SizeOfByte;
229 Streamer.EmitULEB128(ByteSize, Twine(ByteSize));
233 /// Emit a shift-right dwarf expression.
234 static void emitDwarfOpShr(ByteStreamer &Streamer,
236 Streamer.EmitInt8(dwarf::DW_OP_constu, "DW_OP_constu");
237 Streamer.EmitULEB128(ShiftBy);
238 Streamer.EmitInt8(dwarf::DW_OP_shr, "DW_OP_shr");
241 // Some targets do not provide a DWARF register number for every
242 // register. This function attempts to emit a DWARF register by
243 // emitting a piece of a super-register or by piecing together
244 // multiple subregisters that alias the register.
245 void AsmPrinter::EmitDwarfRegOpPiece(ByteStreamer &Streamer,
246 const MachineLocation &MLoc,
247 unsigned PieceSizeInBits,
248 unsigned PieceOffsetInBits) const {
249 assert(MLoc.isReg() && "MLoc must be a register");
250 const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();
251 int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
253 // If this is a valid register number, emit it.
255 emitDwarfRegOp(Streamer, Reg);
256 EmitDwarfOpPiece(Streamer, PieceSizeInBits, PieceOffsetInBits);
260 // Walk up the super-register chain until we find a valid number.
261 // For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
262 for (MCSuperRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) {
263 Reg = TRI->getDwarfRegNum(*SR, false);
265 unsigned Idx = TRI->getSubRegIndex(*SR, MLoc.getReg());
266 unsigned Size = TRI->getSubRegIdxSize(Idx);
267 unsigned RegOffset = TRI->getSubRegIdxOffset(Idx);
268 OutStreamer.AddComment("super-register");
269 emitDwarfRegOp(Streamer, Reg);
270 if (PieceOffsetInBits == RegOffset) {
271 EmitDwarfOpPiece(Streamer, Size, RegOffset);
273 // If this is part of a variable in a sub-register at a
274 // non-zero offset, we need to manually shift the value into
275 // place, since the DW_OP_piece describes the part of the
276 // variable, not the position of the subregister.
278 emitDwarfOpShr(Streamer, RegOffset);
279 EmitDwarfOpPiece(Streamer, Size, PieceOffsetInBits);
285 // Otherwise, attempt to find a covering set of sub-register numbers.
286 // For example, Q0 on ARM is a composition of D0+D1.
288 // Keep track of the current position so we can emit the more
289 // efficient DW_OP_piece.
290 unsigned CurPos = PieceOffsetInBits;
291 // The size of the register in bits, assuming 8 bits per byte.
292 unsigned RegSize = TRI->getMinimalPhysRegClass(MLoc.getReg())->getSize() * 8;
293 // Keep track of the bits in the register we already emitted, so we
294 // can avoid emitting redundant aliasing subregs.
295 SmallBitVector Coverage(RegSize, false);
296 for (MCSubRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) {
297 unsigned Idx = TRI->getSubRegIndex(MLoc.getReg(), *SR);
298 unsigned Size = TRI->getSubRegIdxSize(Idx);
299 unsigned Offset = TRI->getSubRegIdxOffset(Idx);
300 Reg = TRI->getDwarfRegNum(*SR, false);
302 // Intersection between the bits we already emitted and the bits
303 // covered by this subregister.
304 SmallBitVector Intersection(RegSize, false);
305 Intersection.set(Offset, Offset + Size);
306 Intersection ^= Coverage;
308 // If this sub-register has a DWARF number and we haven't covered
309 // its range, emit a DWARF piece for it.
310 if (Reg >= 0 && Intersection.any()) {
311 OutStreamer.AddComment("sub-register");
312 emitDwarfRegOp(Streamer, Reg);
313 EmitDwarfOpPiece(Streamer, Size, Offset == CurPos ? 0 : Offset);
314 CurPos = Offset + Size;
316 // Mark it as emitted.
317 Coverage.set(Offset, Offset + Size);
321 if (CurPos == PieceOffsetInBits) {
322 // FIXME: We have no reasonable way of handling errors in here.
323 Streamer.EmitInt8(dwarf::DW_OP_nop,
324 "nop (could not find a dwarf register number)");
328 /// EmitDwarfRegOp - Emit dwarf register operation.
329 void AsmPrinter::EmitDwarfRegOp(ByteStreamer &Streamer,
330 const MachineLocation &MLoc,
331 bool Indirect) const {
332 const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();
333 int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
335 // We assume that pointers are always in an addressable register.
336 if (Indirect || MLoc.isIndirect()) {
337 // FIXME: We have no reasonable way of handling errors in here. The
338 // caller might be in the middle of a dwarf expression. We should
339 // probably assert that Reg >= 0 once debug info generation is more
341 Streamer.EmitInt8(dwarf::DW_OP_nop,
342 "nop (invalid dwarf register number for indirect loc)");
346 // Attempt to find a valid super- or sub-register.
347 return EmitDwarfRegOpPiece(Streamer, MLoc);
350 if (MLoc.isIndirect())
351 emitDwarfRegOpIndirect(Streamer, Reg, MLoc.getOffset(), Indirect);
353 emitDwarfRegOpIndirect(Streamer, Reg, 0, false);
355 emitDwarfRegOp(Streamer, Reg);
358 //===----------------------------------------------------------------------===//
359 // Dwarf Lowering Routines
360 //===----------------------------------------------------------------------===//
362 void AsmPrinter::emitCFIInstruction(const MCCFIInstruction &Inst) const {
363 switch (Inst.getOperation()) {
365 llvm_unreachable("Unexpected instruction");
366 case MCCFIInstruction::OpDefCfaOffset:
367 OutStreamer.EmitCFIDefCfaOffset(Inst.getOffset());
369 case MCCFIInstruction::OpDefCfa:
370 OutStreamer.EmitCFIDefCfa(Inst.getRegister(), Inst.getOffset());
372 case MCCFIInstruction::OpDefCfaRegister:
373 OutStreamer.EmitCFIDefCfaRegister(Inst.getRegister());
375 case MCCFIInstruction::OpOffset:
376 OutStreamer.EmitCFIOffset(Inst.getRegister(), Inst.getOffset());
378 case MCCFIInstruction::OpRegister:
379 OutStreamer.EmitCFIRegister(Inst.getRegister(), Inst.getRegister2());
381 case MCCFIInstruction::OpWindowSave:
382 OutStreamer.EmitCFIWindowSave();
384 case MCCFIInstruction::OpSameValue:
385 OutStreamer.EmitCFISameValue(Inst.getRegister());