1 //===-- AsmPrinterDwarf.cpp - AsmPrinter Dwarf Support --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the Dwarf emissions parts of AsmPrinter.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "llvm/CodeGen/AsmPrinter.h"
16 #include "llvm/ADT/SmallBitVector.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/IR/DataLayout.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCSection.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/MC/MCSymbol.h"
23 #include "llvm/MC/MachineLocation.h"
24 #include "llvm/Support/Dwarf.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Target/TargetFrameLowering.h"
27 #include "llvm/Target/TargetLoweringObjectFile.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
32 //===----------------------------------------------------------------------===//
33 // Dwarf Emission Helper Routines
34 //===----------------------------------------------------------------------===//
36 /// EmitSLEB128 - emit the specified signed leb128 value.
37 void AsmPrinter::EmitSLEB128(int64_t Value, const char *Desc) const {
38 if (isVerbose() && Desc)
39 OutStreamer.AddComment(Desc);
41 OutStreamer.EmitSLEB128IntValue(Value);
44 /// EmitULEB128 - emit the specified signed leb128 value.
45 void AsmPrinter::EmitULEB128(uint64_t Value, const char *Desc,
46 unsigned PadTo) const {
47 if (isVerbose() && Desc)
48 OutStreamer.AddComment(Desc);
50 OutStreamer.EmitULEB128IntValue(Value, PadTo);
53 /// EmitCFAByte - Emit a .byte 42 directive for a DW_CFA_xxx value.
54 void AsmPrinter::EmitCFAByte(unsigned Val) const {
56 if (Val >= dwarf::DW_CFA_offset && Val < dwarf::DW_CFA_offset + 64)
57 OutStreamer.AddComment("DW_CFA_offset + Reg (" +
58 Twine(Val - dwarf::DW_CFA_offset) + ")");
60 OutStreamer.AddComment(dwarf::CallFrameString(Val));
62 OutStreamer.EmitIntValue(Val, 1);
65 static const char *DecodeDWARFEncoding(unsigned Encoding) {
67 case dwarf::DW_EH_PE_absptr:
69 case dwarf::DW_EH_PE_omit:
71 case dwarf::DW_EH_PE_pcrel:
73 case dwarf::DW_EH_PE_udata4:
75 case dwarf::DW_EH_PE_udata8:
77 case dwarf::DW_EH_PE_sdata4:
79 case dwarf::DW_EH_PE_sdata8:
81 case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata4:
82 return "pcrel udata4";
83 case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4:
84 return "pcrel sdata4";
85 case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata8:
86 return "pcrel udata8";
87 case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata8:
88 return "pcrel sdata8";
89 case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata4
91 return "indirect pcrel udata4";
92 case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4
94 return "indirect pcrel sdata4";
95 case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata8
97 return "indirect pcrel udata8";
98 case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata8
100 return "indirect pcrel sdata8";
103 return "<unknown encoding>";
106 /// EmitEncodingByte - Emit a .byte 42 directive that corresponds to an
107 /// encoding. If verbose assembly output is enabled, we output comments
108 /// describing the encoding. Desc is an optional string saying what the
109 /// encoding is specifying (e.g. "LSDA").
110 void AsmPrinter::EmitEncodingByte(unsigned Val, const char *Desc) const {
113 OutStreamer.AddComment(Twine(Desc) + " Encoding = " +
114 Twine(DecodeDWARFEncoding(Val)));
116 OutStreamer.AddComment(Twine("Encoding = ") + DecodeDWARFEncoding(Val));
119 OutStreamer.EmitIntValue(Val, 1);
122 /// GetSizeOfEncodedValue - Return the size of the encoding in bytes.
123 unsigned AsmPrinter::GetSizeOfEncodedValue(unsigned Encoding) const {
124 if (Encoding == dwarf::DW_EH_PE_omit)
127 switch (Encoding & 0x07) {
129 llvm_unreachable("Invalid encoded value.");
130 case dwarf::DW_EH_PE_absptr:
131 return TM.getDataLayout()->getPointerSize();
132 case dwarf::DW_EH_PE_udata2:
134 case dwarf::DW_EH_PE_udata4:
136 case dwarf::DW_EH_PE_udata8:
141 void AsmPrinter::EmitTTypeReference(const GlobalValue *GV,
142 unsigned Encoding) const {
144 const TargetLoweringObjectFile &TLOF = getObjFileLowering();
147 TLOF.getTTypeGlobalReference(GV, Encoding, *Mang, TM, MMI, OutStreamer);
148 OutStreamer.EmitValue(Exp, GetSizeOfEncodedValue(Encoding));
150 OutStreamer.EmitIntValue(0, GetSizeOfEncodedValue(Encoding));
153 /// EmitSectionOffset - Emit the 4-byte offset of Label from the start of its
154 /// section. This can be done with a special directive if the target supports
155 /// it (e.g. cygwin) or by emitting it as an offset from a label at the start
158 /// SectionLabel is a temporary label emitted at the start of the section that
160 void AsmPrinter::EmitSectionOffset(const MCSymbol *Label,
161 const MCSymbol *SectionLabel) const {
162 // On COFF targets, we have to emit the special .secrel32 directive.
163 if (MAI->needsDwarfSectionOffsetDirective()) {
164 OutStreamer.EmitCOFFSecRel32(Label);
168 // Get the section that we're referring to, based on SectionLabel.
169 const MCSection &Section = SectionLabel->getSection();
171 // If Label has already been emitted, verify that it is in the same section as
172 // section label for sanity.
173 assert((!Label->isInSection() || &Label->getSection() == &Section) &&
174 "Section offset using wrong section base for label");
176 // If the section in question will end up with an address of 0 anyway, we can
177 // just emit an absolute reference to save a relocation.
178 if (Section.isBaseAddressKnownZero()) {
179 OutStreamer.EmitSymbolValue(Label, 4);
183 // Otherwise, emit it as a label difference from the start of the section.
184 EmitLabelDifference(Label, SectionLabel, 4);
188 /// Emit a dwarf register operation.
189 static void emitDwarfRegOp(const AsmPrinter &AP, int Reg) {
192 AP.OutStreamer.AddComment(
193 dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
194 AP.EmitInt8(dwarf::DW_OP_reg0 + Reg);
196 AP.OutStreamer.AddComment("DW_OP_regx");
197 AP.EmitInt8(dwarf::DW_OP_regx);
198 AP.OutStreamer.AddComment(Twine(Reg));
203 /// Emit an (double-)indirect dwarf register operation.
204 static void emitDwarfRegOpIndirect(const AsmPrinter &AP,
205 int Reg, int Offset, bool Deref) {
208 AP.OutStreamer.AddComment(
209 dwarf::OperationEncodingString(dwarf::DW_OP_breg0 + Reg));
210 AP.EmitInt8(dwarf::DW_OP_breg0 + Reg);
212 AP.OutStreamer.AddComment("DW_OP_bregx");
213 AP.EmitInt8(dwarf::DW_OP_bregx);
214 AP.OutStreamer.AddComment(Twine(Reg));
217 AP.EmitSLEB128(Offset);
219 AP.EmitInt8(dwarf::DW_OP_deref);
222 /// Emit a dwarf register operation for describing
223 /// - a small value occupying only part of a register or
224 /// - a small register representing only part of a value.
225 static void emitDwarfOpPiece(const AsmPrinter &AP,
226 unsigned Size, unsigned Offset) {
229 AP.OutStreamer.AddComment("DW_OP_bit_piece");
230 AP.EmitInt8(dwarf::DW_OP_bit_piece);
231 AP.OutStreamer.AddComment(Twine(Size));
232 AP.EmitULEB128(Size);
233 AP.OutStreamer.AddComment(Twine(Offset));
234 AP.EmitULEB128(Offset);
236 AP.OutStreamer.AddComment("DW_OP_piece");
237 AP.EmitInt8(dwarf::DW_OP_piece);
238 unsigned ByteSize = Size / 8; // Assuming 8 bits per byte.
239 AP.OutStreamer.AddComment(Twine(ByteSize));
240 AP.EmitULEB128(ByteSize);
244 /// Some targets do not provide a DWARF register number for every
245 /// register. This function attempts to emit a dwarf register by
246 /// emitting a piece of a super-register or by piecing together
247 /// multiple subregisters that alias the register.
248 static void EmitDwarfRegOpPiece(const AsmPrinter &AP,
249 const MachineLocation &MLoc) {
250 assert(!MLoc.isIndirect());
251 const TargetRegisterInfo *TRI = AP.TM.getRegisterInfo();
252 int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
254 // Walk up the super-register chain until we find a valid number.
255 // For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
256 for (MCSuperRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) {
257 Reg = TRI->getDwarfRegNum(*SR, false);
259 unsigned Idx = TRI->getSubRegIndex(*SR, MLoc.getReg());
260 unsigned Size = TRI->getSubRegIdxSize(Idx);
261 unsigned Offset = TRI->getSubRegIdxOffset(Idx);
262 AP.OutStreamer.AddComment("super-register");
263 emitDwarfRegOp(AP, Reg);
264 emitDwarfOpPiece(AP, Size, Offset);
269 // Otherwise, attempt to find a covering set of sub-register numbers.
270 // For example, Q0 on ARM is a composition of D0+D1.
272 // Keep track of the current position so we can emit the more
273 // efficient DW_OP_piece.
275 // The size of the register in bits, assuming 8 bits per byte.
276 unsigned RegSize = TRI->getMinimalPhysRegClass(MLoc.getReg())->getSize()*8;
277 // Keep track of the bits in the register we already emitted, so we
278 // can avoid emitting redundant aliasing subregs.
279 SmallBitVector Coverage(RegSize, false);
280 for (MCSubRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) {
281 unsigned Idx = TRI->getSubRegIndex(MLoc.getReg(), *SR);
282 unsigned Size = TRI->getSubRegIdxSize(Idx);
283 unsigned Offset = TRI->getSubRegIdxOffset(Idx);
284 Reg = TRI->getDwarfRegNum(*SR, false);
286 // Intersection between the bits we already emitted and the bits
287 // covered by this subregister.
288 SmallBitVector Intersection(RegSize, false);
289 Intersection.set(Offset, Offset+Size);
290 Intersection ^= Coverage;
292 // If this sub-register has a DWARF number and we haven't covered
293 // its range, emit a DWARF piece for it.
294 if (Reg >= 0 && Intersection.any()) {
295 AP.OutStreamer.AddComment("sub-register");
296 emitDwarfRegOp(AP, Reg);
297 emitDwarfOpPiece(AP, Size, Offset == CurPos ? 0 : Offset);
298 CurPos = Offset+Size;
300 // Mark it as emitted.
301 Coverage.set(Offset, Offset+Size);
306 // FIXME: We have no reasonable way of handling errors in here.
307 AP.OutStreamer.AddComment("nop (could not find a dwarf register number)");
308 AP.EmitInt8(dwarf::DW_OP_nop);
312 /// EmitDwarfRegOp - Emit dwarf register operation.
313 void AsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
314 bool Indirect) const {
315 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
316 int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
318 // We assume that pointers are always in an addressable register.
319 if (Indirect || MLoc.isIndirect()) {
320 // FIXME: We have no reasonable way of handling errors in here. The
321 // caller might be in the middle of a dwarf expression. We should
322 // probably assert that Reg >= 0 once debug info generation is more
324 OutStreamer.AddComment(
325 "nop (invalid dwarf register number for indirect loc)");
326 EmitInt8(dwarf::DW_OP_nop);
330 // Attempt to find a valid super- or sub-register.
331 if (!Indirect && !MLoc.isIndirect())
332 return EmitDwarfRegOpPiece(*this, MLoc);
335 if (MLoc.isIndirect())
336 emitDwarfRegOpIndirect(*this, Reg, MLoc.getOffset(), Indirect);
338 emitDwarfRegOpIndirect(*this, Reg, 0, false);
340 emitDwarfRegOp(*this, Reg);
343 //===----------------------------------------------------------------------===//
344 // Dwarf Lowering Routines
345 //===----------------------------------------------------------------------===//
347 void AsmPrinter::emitCFIInstruction(const MCCFIInstruction &Inst) const {
348 switch (Inst.getOperation()) {
350 llvm_unreachable("Unexpected instruction");
351 case MCCFIInstruction::OpDefCfaOffset:
352 OutStreamer.EmitCFIDefCfaOffset(Inst.getOffset());
354 case MCCFIInstruction::OpDefCfa:
355 OutStreamer.EmitCFIDefCfa(Inst.getRegister(), Inst.getOffset());
357 case MCCFIInstruction::OpDefCfaRegister:
358 OutStreamer.EmitCFIDefCfaRegister(Inst.getRegister());
360 case MCCFIInstruction::OpOffset:
361 OutStreamer.EmitCFIOffset(Inst.getRegister(), Inst.getOffset());
363 case MCCFIInstruction::OpRegister:
364 OutStreamer.EmitCFIRegister(Inst.getRegister(), Inst.getRegister2());
366 case MCCFIInstruction::OpWindowSave:
367 OutStreamer.EmitCFIWindowSave();