1 //===-- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains support for writing dwarf debug info into asm files.
12 //===----------------------------------------------------------------------===//
14 #include "DwarfExpression.h"
16 #include "DwarfDebug.h"
17 #include "llvm/ADT/SmallBitVector.h"
18 #include "llvm/CodeGen/AsmPrinter.h"
19 #include "llvm/Support/Dwarf.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetRegisterInfo.h"
22 #include "llvm/Target/TargetSubtargetInfo.h"
26 const TargetRegisterInfo *DwarfExpression::getTRI() const {
27 return AP.TM.getSubtargetImpl()->getRegisterInfo();
30 unsigned DwarfExpression::getDwarfVersion() const {
31 return AP.getDwarfDebug()->getDwarfVersion();
34 void DwarfExpression::AddReg(int DwarfReg, const char *Comment) {
35 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
37 EmitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
39 EmitOp(dwarf::DW_OP_regx, Comment);
40 EmitUnsigned(DwarfReg);
44 void DwarfExpression::AddRegIndirect(int DwarfReg, int Offset, bool Deref) {
45 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
47 EmitOp(dwarf::DW_OP_breg0 + DwarfReg);
49 EmitOp(dwarf::DW_OP_bregx);
50 EmitUnsigned(DwarfReg);
54 EmitOp(dwarf::DW_OP_deref);
57 void DwarfExpression::AddOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
58 assert(SizeInBits > 0 && "piece has size zero");
59 const unsigned SizeOfByte = 8;
60 if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
61 EmitOp(dwarf::DW_OP_bit_piece);
62 EmitUnsigned(SizeInBits);
63 EmitUnsigned(OffsetInBits);
65 EmitOp(dwarf::DW_OP_piece);
66 unsigned ByteSize = SizeInBits / SizeOfByte;
67 EmitUnsigned(ByteSize);
71 void DwarfExpression::AddShr(unsigned ShiftBy) {
72 EmitOp(dwarf::DW_OP_constu);
73 EmitUnsigned(ShiftBy);
74 EmitOp(dwarf::DW_OP_shr);
77 bool DwarfExpression::AddMachineRegIndirect(unsigned MachineReg, int Offset) {
78 int DwarfReg = getTRI()->getDwarfRegNum(MachineReg, false);
82 if (isFrameRegister(MachineReg)) {
83 // If variable offset is based in frame register then use fbreg.
84 EmitOp(dwarf::DW_OP_fbreg);
87 AddRegIndirect(DwarfReg, Offset);
92 void DwarfExpression::AddMachineRegPiece(unsigned MachineReg,
93 unsigned PieceSizeInBits,
94 unsigned PieceOffsetInBits) {
95 const TargetRegisterInfo *TRI = getTRI();
96 int Reg = TRI->getDwarfRegNum(MachineReg, false);
98 // If this is a valid register number, emit it.
102 AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
106 // Walk up the super-register chain until we find a valid number.
107 // For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
108 for (MCSuperRegIterator SR(MachineReg, TRI); SR.isValid(); ++SR) {
109 Reg = TRI->getDwarfRegNum(*SR, false);
111 unsigned Idx = TRI->getSubRegIndex(*SR, MachineReg);
112 unsigned Size = TRI->getSubRegIdxSize(Idx);
113 unsigned RegOffset = TRI->getSubRegIdxOffset(Idx);
114 AddReg(Reg, "super-register");
115 if (PieceOffsetInBits == RegOffset) {
116 AddOpPiece(Size, RegOffset);
118 // If this is part of a variable in a sub-register at a
119 // non-zero offset, we need to manually shift the value into
120 // place, since the DW_OP_piece describes the part of the
121 // variable, not the position of the subregister.
124 AddOpPiece(Size, PieceOffsetInBits);
130 // Otherwise, attempt to find a covering set of sub-register numbers.
131 // For example, Q0 on ARM is a composition of D0+D1.
133 // Keep track of the current position so we can emit the more
134 // efficient DW_OP_piece.
135 unsigned CurPos = PieceOffsetInBits;
136 // The size of the register in bits, assuming 8 bits per byte.
137 unsigned RegSize = TRI->getMinimalPhysRegClass(MachineReg)->getSize() * 8;
138 // Keep track of the bits in the register we already emitted, so we
139 // can avoid emitting redundant aliasing subregs.
140 SmallBitVector Coverage(RegSize, false);
141 for (MCSubRegIterator SR(MachineReg, TRI); SR.isValid(); ++SR) {
142 unsigned Idx = TRI->getSubRegIndex(MachineReg, *SR);
143 unsigned Size = TRI->getSubRegIdxSize(Idx);
144 unsigned Offset = TRI->getSubRegIdxOffset(Idx);
145 Reg = TRI->getDwarfRegNum(*SR, false);
147 // Intersection between the bits we already emitted and the bits
148 // covered by this subregister.
149 SmallBitVector Intersection(RegSize, false);
150 Intersection.set(Offset, Offset + Size);
151 Intersection ^= Coverage;
153 // If this sub-register has a DWARF number and we haven't covered
154 // its range, emit a DWARF piece for it.
155 if (Reg >= 0 && Intersection.any()) {
156 AddReg(Reg, "sub-register");
157 AddOpPiece(Size, Offset == CurPos ? 0 : Offset);
158 CurPos = Offset + Size;
160 // Mark it as emitted.
161 Coverage.set(Offset, Offset + Size);
165 if (CurPos == PieceOffsetInBits)
166 // FIXME: We have no reasonable way of handling errors in here.
167 EmitOp(dwarf::DW_OP_nop, "nop (could not find a dwarf register number)");
170 void DwarfExpression::AddSignedConstant(int Value) {
171 EmitOp(dwarf::DW_OP_consts);
173 // The proper way to describe a constant value is
174 // DW_OP_constu <const>, DW_OP_stack_value.
175 // Unfortunately, DW_OP_stack_value was not available until DWARF-4,
176 // so we will continue to generate DW_OP_constu <const> for DWARF-2
177 // and DWARF-3. Technically, this is incorrect since DW_OP_const <const>
178 // actually describes a value at a constant addess, not a constant value.
179 // However, in the past there was no better way to describe a constant
180 // value, so the producers and consumers started to rely on heuristics
181 // to disambiguate the value vs. location status of the expression.
182 // See PR21176 for more details.
183 if (getDwarfVersion() >= 4)
184 EmitOp(dwarf::DW_OP_stack_value);
187 void DwarfExpression::AddUnsignedConstant(unsigned Value) {
188 EmitOp(dwarf::DW_OP_constu);
190 // cf. comment in DwarfExpression::AddSignedConstant().
191 if (getDwarfVersion() >= 4)
192 EmitOp(dwarf::DW_OP_stack_value);
195 static unsigned getOffsetOrZero(unsigned OffsetInBits,
196 unsigned PieceOffsetInBits) {
197 if (OffsetInBits == PieceOffsetInBits)
199 assert(OffsetInBits >= PieceOffsetInBits && "overlapping pieces");
203 void DwarfExpression::AddMachineRegExpression(DIExpression Expr,
205 unsigned PieceOffsetInBits) {
206 unsigned N = Expr.getNumElements();
208 // Pattern-match combinations for which more efficient representations exist
210 if (N >= 3 && Expr.getElement(0) == dwarf::DW_OP_piece) {
211 unsigned SizeOfByte = 8;
212 unsigned OffsetInBits = Expr.getElement(1) * SizeOfByte;
213 unsigned SizeInBits = Expr.getElement(2) * SizeOfByte;
214 AddMachineRegPiece(MachineReg, SizeInBits,
215 getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
217 } else if (N >= 3 && Expr.getElement(0) == dwarf::DW_OP_plus &&
218 Expr.getElement(2) == dwarf::DW_OP_deref) {
219 // [DW_OP_reg,Offset,DW_OP_plus,DW_OP_deref] --> [DW_OP_breg,Offset].
220 unsigned Offset = Expr.getElement(1);
221 AddMachineRegIndirect(MachineReg, Offset);
223 } else if (N >= 1 && Expr.getElement(0) == dwarf::DW_OP_deref) {
224 // [DW_OP_reg,DW_OP_deref] --> [DW_OP_breg].
225 AddMachineRegIndirect(MachineReg);
228 AddMachineRegPiece(MachineReg);
230 // Emit remaining elements of the expression.
231 AddExpression(Expr, I);
234 void DwarfExpression::AddExpression(DIExpression Expr, unsigned I,
235 unsigned PieceOffsetInBits) {
236 unsigned N = Expr.getNumElements();
238 switch (Expr.getElement(I)) {
239 case dwarf::DW_OP_piece: {
240 unsigned SizeOfByte = 8;
241 unsigned OffsetInBits = Expr.getElement(++I) * SizeOfByte;
242 unsigned SizeInBits = Expr.getElement(++I) * SizeOfByte;
243 AddOpPiece(SizeInBits, getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
246 case dwarf::DW_OP_plus:
247 EmitOp(dwarf::DW_OP_plus_uconst);
248 EmitUnsigned(Expr.getElement(++I));
250 case dwarf::DW_OP_deref:
251 EmitOp(dwarf::DW_OP_deref);
254 llvm_unreachable("unhandled opcode found in DIExpression");