1 //===----- CriticalAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the CriticalAntiDepBreaker class, which
11 // implements register anti-dependence breaking along a blocks
12 // critical path during post-RA scheduler.
14 //===----------------------------------------------------------------------===//
16 #include "CriticalAntiDepBreaker.h"
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
28 #define DEBUG_TYPE "post-RA-sched"
30 CriticalAntiDepBreaker::
31 CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI) :
32 AntiDepBreaker(), MF(MFi),
34 TII(MF.getTarget().getInstrInfo()),
35 TRI(MF.getTarget().getRegisterInfo()),
37 Classes(TRI->getNumRegs(), nullptr),
38 KillIndices(TRI->getNumRegs(), 0),
39 DefIndices(TRI->getNumRegs(), 0),
40 KeepRegs(TRI->getNumRegs(), false) {}
42 CriticalAntiDepBreaker::~CriticalAntiDepBreaker() {
45 void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
46 const unsigned BBSize = BB->size();
47 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
48 // Clear out the register class data.
51 // Initialize the indices to indicate that no registers are live.
53 DefIndices[i] = BBSize;
56 // Clear "do not change" set.
59 bool IsReturnBlock = (BBSize != 0 && BB->back().isReturn());
61 // Examine the live-in regs of all successors.
62 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
63 SE = BB->succ_end(); SI != SE; ++SI)
64 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
65 E = (*SI)->livein_end(); I != E; ++I) {
66 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
68 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
69 KillIndices[Reg] = BBSize;
70 DefIndices[Reg] = ~0u;
74 // Mark live-out callee-saved registers. In a return block this is
75 // all callee-saved registers. In non-return this is any
76 // callee-saved register that is not saved in the prolog.
77 const MachineFrameInfo *MFI = MF.getFrameInfo();
78 BitVector Pristine = MFI->getPristineRegs(BB);
79 for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
80 if (!IsReturnBlock && !Pristine.test(*I)) continue;
81 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
83 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
84 KillIndices[Reg] = BBSize;
85 DefIndices[Reg] = ~0u;
90 void CriticalAntiDepBreaker::FinishBlock() {
95 void CriticalAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
96 unsigned InsertPosIndex) {
97 if (MI->isDebugValue())
99 assert(Count < InsertPosIndex && "Instruction index out of expected range!");
101 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
102 if (KillIndices[Reg] != ~0u) {
103 // If Reg is currently live, then mark that it can't be renamed as
104 // we don't know the extent of its live-range anymore (now that it
105 // has been scheduled).
106 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
107 KillIndices[Reg] = Count;
108 } else if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
109 // Any register which was defined within the previous scheduling region
110 // may have been rescheduled and its lifetime may overlap with registers
111 // in ways not reflected in our current liveness state. For each such
112 // register, adjust the liveness state to be conservatively correct.
113 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
115 // Move the def index to the end of the previous region, to reflect
116 // that the def could theoretically have been scheduled at the end.
117 DefIndices[Reg] = InsertPosIndex;
121 PrescanInstruction(MI);
122 ScanInstruction(MI, Count);
125 /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
127 static const SDep *CriticalPathStep(const SUnit *SU) {
128 const SDep *Next = nullptr;
129 unsigned NextDepth = 0;
130 // Find the predecessor edge with the greatest depth.
131 for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
133 const SUnit *PredSU = P->getSUnit();
134 unsigned PredLatency = P->getLatency();
135 unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
136 // In the case of a latency tie, prefer an anti-dependency edge over
137 // other types of edges.
138 if (NextDepth < PredTotalLatency ||
139 (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
140 NextDepth = PredTotalLatency;
147 void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) {
148 // It's not safe to change register allocation for source operands of
149 // instructions that have special allocation requirements. Also assume all
150 // registers used in a call must not be changed (ABI).
151 // FIXME: The issue with predicated instruction is more complex. We are being
152 // conservative here because the kill markers cannot be trusted after
154 // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
156 // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
157 // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
158 // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
160 // The first R6 kill is not really a kill since it's killed by a predicated
161 // instruction which may not be executed. The second R6 def may or may not
162 // re-define R6 so it's not safe to change it since the last R6 use cannot be
164 bool Special = MI->isCall() ||
165 MI->hasExtraSrcRegAllocReq() ||
166 TII->isPredicated(MI);
168 // Scan the register operands for this instruction and update
169 // Classes and RegRefs.
170 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
171 MachineOperand &MO = MI->getOperand(i);
172 if (!MO.isReg()) continue;
173 unsigned Reg = MO.getReg();
174 if (Reg == 0) continue;
175 const TargetRegisterClass *NewRC = nullptr;
177 if (i < MI->getDesc().getNumOperands())
178 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
180 // For now, only allow the register to be changed if its register
181 // class is consistent across all uses.
182 if (!Classes[Reg] && NewRC)
183 Classes[Reg] = NewRC;
184 else if (!NewRC || Classes[Reg] != NewRC)
185 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
187 // Now check for aliases.
188 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
189 // If an alias of the reg is used during the live range, give up.
190 // Note that this allows us to skip checking if AntiDepReg
191 // overlaps with any of the aliases, among other things.
192 unsigned AliasReg = *AI;
193 if (Classes[AliasReg]) {
194 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
195 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
199 // If we're still willing to consider this register, note the reference.
200 if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
201 RegRefs.insert(std::make_pair(Reg, &MO));
203 if (MO.isUse() && Special) {
204 if (!KeepRegs.test(Reg)) {
205 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
206 SubRegs.isValid(); ++SubRegs)
207 KeepRegs.set(*SubRegs);
213 void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
216 // Proceeding upwards, registers that are defed but not used in this
217 // instruction are now dead.
219 if (!TII->isPredicated(MI)) {
220 // Predicated defs are modeled as read + write, i.e. similar to two
222 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
223 MachineOperand &MO = MI->getOperand(i);
226 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
227 if (MO.clobbersPhysReg(i)) {
228 DefIndices[i] = Count;
229 KillIndices[i] = ~0u;
231 Classes[i] = nullptr;
235 if (!MO.isReg()) continue;
236 unsigned Reg = MO.getReg();
237 if (Reg == 0) continue;
238 if (!MO.isDef()) continue;
239 // Ignore two-addr defs.
240 if (MI->isRegTiedToUseOperand(i)) continue;
242 DefIndices[Reg] = Count;
243 KillIndices[Reg] = ~0u;
244 assert(((KillIndices[Reg] == ~0u) !=
245 (DefIndices[Reg] == ~0u)) &&
246 "Kill and Def maps aren't consistent for Reg!");
248 Classes[Reg] = nullptr;
250 // Repeat, for all subregs.
251 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
252 unsigned SubregReg = *SubRegs;
253 DefIndices[SubregReg] = Count;
254 KillIndices[SubregReg] = ~0u;
255 KeepRegs.reset(SubregReg);
256 Classes[SubregReg] = nullptr;
257 RegRefs.erase(SubregReg);
259 // Conservatively mark super-registers as unusable.
260 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR)
261 Classes[*SR] = reinterpret_cast<TargetRegisterClass *>(-1);
264 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
265 MachineOperand &MO = MI->getOperand(i);
266 if (!MO.isReg()) continue;
267 unsigned Reg = MO.getReg();
268 if (Reg == 0) continue;
269 if (!MO.isUse()) continue;
271 const TargetRegisterClass *NewRC = nullptr;
272 if (i < MI->getDesc().getNumOperands())
273 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
275 // For now, only allow the register to be changed if its register
276 // class is consistent across all uses.
277 if (!Classes[Reg] && NewRC)
278 Classes[Reg] = NewRC;
279 else if (!NewRC || Classes[Reg] != NewRC)
280 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
282 RegRefs.insert(std::make_pair(Reg, &MO));
284 // It wasn't previously live but now it is, this is a kill.
285 if (KillIndices[Reg] == ~0u) {
286 KillIndices[Reg] = Count;
287 DefIndices[Reg] = ~0u;
288 assert(((KillIndices[Reg] == ~0u) !=
289 (DefIndices[Reg] == ~0u)) &&
290 "Kill and Def maps aren't consistent for Reg!");
292 // Repeat, for all aliases.
293 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
294 unsigned AliasReg = *AI;
295 if (KillIndices[AliasReg] == ~0u) {
296 KillIndices[AliasReg] = Count;
297 DefIndices[AliasReg] = ~0u;
303 // Check all machine operands that reference the antidependent register and must
304 // be replaced by NewReg. Return true if any of their parent instructions may
305 // clobber the new register.
307 // Note: AntiDepReg may be referenced by a two-address instruction such that
308 // it's use operand is tied to a def operand. We guard against the case in which
309 // the two-address instruction also defines NewReg, as may happen with
310 // pre/postincrement loads. In this case, both the use and def operands are in
311 // RegRefs because the def is inserted by PrescanInstruction and not erased
312 // during ScanInstruction. So checking for an instruction with definitions of
313 // both NewReg and AntiDepReg covers it.
315 CriticalAntiDepBreaker::isNewRegClobberedByRefs(RegRefIter RegRefBegin,
316 RegRefIter RegRefEnd,
319 for (RegRefIter I = RegRefBegin; I != RegRefEnd; ++I ) {
320 MachineOperand *RefOper = I->second;
322 // Don't allow the instruction defining AntiDepReg to earlyclobber its
323 // operands, in case they may be assigned to NewReg. In this case antidep
324 // breaking must fail, but it's too rare to bother optimizing.
325 if (RefOper->isDef() && RefOper->isEarlyClobber())
328 // Handle cases in which this instruction defines NewReg.
329 MachineInstr *MI = RefOper->getParent();
330 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
331 const MachineOperand &CheckOper = MI->getOperand(i);
333 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg))
336 if (!CheckOper.isReg() || !CheckOper.isDef() ||
337 CheckOper.getReg() != NewReg)
340 // Don't allow the instruction to define NewReg and AntiDepReg.
341 // When AntiDepReg is renamed it will be an illegal op.
342 if (RefOper->isDef())
345 // Don't allow an instruction using AntiDepReg to be earlyclobbered by
347 if (CheckOper.isEarlyClobber())
350 // Don't allow inline asm to define NewReg at all. Who knows what it's
352 if (MI->isInlineAsm())
359 unsigned CriticalAntiDepBreaker::
360 findSuitableFreeRegister(RegRefIter RegRefBegin,
361 RegRefIter RegRefEnd,
364 const TargetRegisterClass *RC,
365 SmallVectorImpl<unsigned> &Forbid)
367 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
368 for (unsigned i = 0; i != Order.size(); ++i) {
369 unsigned NewReg = Order[i];
370 // Don't replace a register with itself.
371 if (NewReg == AntiDepReg) continue;
372 // Don't replace a register with one that was recently used to repair
373 // an anti-dependence with this AntiDepReg, because that would
374 // re-introduce that anti-dependence.
375 if (NewReg == LastNewReg) continue;
376 // If any instructions that define AntiDepReg also define the NewReg, it's
377 // not suitable. For example, Instruction with multiple definitions can
378 // result in this condition.
379 if (isNewRegClobberedByRefs(RegRefBegin, RegRefEnd, NewReg)) continue;
380 // If NewReg is dead and NewReg's most recent def is not before
381 // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
382 assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u))
383 && "Kill and Def maps aren't consistent for AntiDepReg!");
384 assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u))
385 && "Kill and Def maps aren't consistent for NewReg!");
386 if (KillIndices[NewReg] != ~0u ||
387 Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
388 KillIndices[AntiDepReg] > DefIndices[NewReg])
390 // If NewReg overlaps any of the forbidden registers, we can't use it.
391 bool Forbidden = false;
392 for (SmallVectorImpl<unsigned>::iterator it = Forbid.begin(),
393 ite = Forbid.end(); it != ite; ++it)
394 if (TRI->regsOverlap(NewReg, *it)) {
398 if (Forbidden) continue;
402 // No registers are free and available!
406 unsigned CriticalAntiDepBreaker::
407 BreakAntiDependencies(const std::vector<SUnit>& SUnits,
408 MachineBasicBlock::iterator Begin,
409 MachineBasicBlock::iterator End,
410 unsigned InsertPosIndex,
411 DbgValueVector &DbgValues) {
412 // The code below assumes that there is at least one instruction,
413 // so just duck out immediately if the block is empty.
414 if (SUnits.empty()) return 0;
416 // Keep a map of the MachineInstr*'s back to the SUnit representing them.
417 // This is used for updating debug information.
419 // FIXME: Replace this with the existing map in ScheduleDAGInstrs::MISUnitMap
420 DenseMap<MachineInstr*,const SUnit*> MISUnitMap;
422 // Find the node at the bottom of the critical path.
423 const SUnit *Max = nullptr;
424 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
425 const SUnit *SU = &SUnits[i];
426 MISUnitMap[SU->getInstr()] = SU;
427 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
433 DEBUG(dbgs() << "Critical path has total latency "
434 << (Max->getDepth() + Max->Latency) << "\n");
435 DEBUG(dbgs() << "Available regs:");
436 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
437 if (KillIndices[Reg] == ~0u)
438 DEBUG(dbgs() << " " << TRI->getName(Reg));
440 DEBUG(dbgs() << '\n');
444 // Track progress along the critical path through the SUnit graph as we walk
446 const SUnit *CriticalPathSU = Max;
447 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
449 // Consider this pattern:
458 // There are three anti-dependencies here, and without special care,
459 // we'd break all of them using the same register:
468 // because at each anti-dependence, B is the first register that
469 // isn't A which is free. This re-introduces anti-dependencies
470 // at all but one of the original anti-dependencies that we were
471 // trying to break. To avoid this, keep track of the most recent
472 // register that each register was replaced with, avoid
473 // using it to repair an anti-dependence on the same register.
474 // This lets us produce this:
483 // This still has an anti-dependence on B, but at least it isn't on the
484 // original critical path.
486 // TODO: If we tracked more than one register here, we could potentially
487 // fix that remaining critical edge too. This is a little more involved,
488 // because unlike the most recent register, less recent registers should
489 // still be considered, though only if no other registers are available.
490 std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0);
492 // Attempt to break anti-dependence edges on the critical path. Walk the
493 // instructions from the bottom up, tracking information about liveness
494 // as we go to help determine which registers are available.
496 unsigned Count = InsertPosIndex - 1;
497 for (MachineBasicBlock::iterator I = End, E = Begin; I != E; --Count) {
498 MachineInstr *MI = --I;
499 if (MI->isDebugValue())
502 // Check if this instruction has a dependence on the critical path that
503 // is an anti-dependence that we may be able to break. If it is, set
504 // AntiDepReg to the non-zero register associated with the anti-dependence.
506 // We limit our attention to the critical path as a heuristic to avoid
507 // breaking anti-dependence edges that aren't going to significantly
508 // impact the overall schedule. There are a limited number of registers
509 // and we want to save them for the important edges.
511 // TODO: Instructions with multiple defs could have multiple
512 // anti-dependencies. The current code here only knows how to break one
513 // edge per instruction. Note that we'd have to be able to break all of
514 // the anti-dependencies in an instruction in order to be effective.
515 unsigned AntiDepReg = 0;
516 if (MI == CriticalPathMI) {
517 if (const SDep *Edge = CriticalPathStep(CriticalPathSU)) {
518 const SUnit *NextSU = Edge->getSUnit();
520 // Only consider anti-dependence edges.
521 if (Edge->getKind() == SDep::Anti) {
522 AntiDepReg = Edge->getReg();
523 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
524 if (!MRI.isAllocatable(AntiDepReg))
525 // Don't break anti-dependencies on non-allocatable registers.
527 else if (KeepRegs.test(AntiDepReg))
528 // Don't break anti-dependencies if a use down below requires
529 // this exact register.
532 // If the SUnit has other dependencies on the SUnit that it
533 // anti-depends on, don't bother breaking the anti-dependency
534 // since those edges would prevent such units from being
535 // scheduled past each other regardless.
537 // Also, if there are dependencies on other SUnits with the
538 // same register as the anti-dependency, don't attempt to
540 for (SUnit::const_pred_iterator P = CriticalPathSU->Preds.begin(),
541 PE = CriticalPathSU->Preds.end(); P != PE; ++P)
542 if (P->getSUnit() == NextSU ?
543 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
544 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
550 CriticalPathSU = NextSU;
551 CriticalPathMI = CriticalPathSU->getInstr();
553 // We've reached the end of the critical path.
554 CriticalPathSU = nullptr;
555 CriticalPathMI = nullptr;
559 PrescanInstruction(MI);
561 SmallVector<unsigned, 2> ForbidRegs;
563 // If MI's defs have a special allocation requirement, don't allow
564 // any def registers to be changed. Also assume all registers
565 // defined in a call must not be changed (ABI).
566 if (MI->isCall() || MI->hasExtraDefRegAllocReq() || TII->isPredicated(MI))
567 // If this instruction's defs have special allocation requirement, don't
568 // break this anti-dependency.
570 else if (AntiDepReg) {
571 // If this instruction has a use of AntiDepReg, breaking it
572 // is invalid. If the instruction defines other registers,
573 // save a list of them so that we don't pick a new register
574 // that overlaps any of them.
575 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
576 MachineOperand &MO = MI->getOperand(i);
577 if (!MO.isReg()) continue;
578 unsigned Reg = MO.getReg();
579 if (Reg == 0) continue;
580 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) {
584 if (MO.isDef() && Reg != AntiDepReg)
585 ForbidRegs.push_back(Reg);
589 // Determine AntiDepReg's register class, if it is live and is
590 // consistently used within a single class.
591 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg]
593 assert((AntiDepReg == 0 || RC != nullptr) &&
594 "Register should be live if it's causing an anti-dependence!");
595 if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
598 // Look for a suitable register to use to break the anti-dependence.
600 // TODO: Instead of picking the first free register, consider which might
602 if (AntiDepReg != 0) {
603 std::pair<std::multimap<unsigned, MachineOperand *>::iterator,
604 std::multimap<unsigned, MachineOperand *>::iterator>
605 Range = RegRefs.equal_range(AntiDepReg);
606 if (unsigned NewReg = findSuitableFreeRegister(Range.first, Range.second,
608 LastNewReg[AntiDepReg],
610 DEBUG(dbgs() << "Breaking anti-dependence edge on "
611 << TRI->getName(AntiDepReg)
612 << " with " << RegRefs.count(AntiDepReg) << " references"
613 << " using " << TRI->getName(NewReg) << "!\n");
615 // Update the references to the old register to refer to the new
617 for (std::multimap<unsigned, MachineOperand *>::iterator
618 Q = Range.first, QE = Range.second; Q != QE; ++Q) {
619 Q->second->setReg(NewReg);
620 // If the SU for the instruction being updated has debug information
621 // related to the anti-dependency register, make sure to update that
623 const SUnit *SU = MISUnitMap[Q->second->getParent()];
625 for (DbgValueVector::iterator DVI = DbgValues.begin(),
626 DVE = DbgValues.end(); DVI != DVE; ++DVI)
627 if (DVI->second == Q->second->getParent())
628 UpdateDbgValue(DVI->first, AntiDepReg, NewReg);
631 // We just went back in time and modified history; the
632 // liveness information for the anti-dependence reg is now
633 // inconsistent. Set the state as if it were dead.
634 Classes[NewReg] = Classes[AntiDepReg];
635 DefIndices[NewReg] = DefIndices[AntiDepReg];
636 KillIndices[NewReg] = KillIndices[AntiDepReg];
637 assert(((KillIndices[NewReg] == ~0u) !=
638 (DefIndices[NewReg] == ~0u)) &&
639 "Kill and Def maps aren't consistent for NewReg!");
641 Classes[AntiDepReg] = nullptr;
642 DefIndices[AntiDepReg] = KillIndices[AntiDepReg];
643 KillIndices[AntiDepReg] = ~0u;
644 assert(((KillIndices[AntiDepReg] == ~0u) !=
645 (DefIndices[AntiDepReg] == ~0u)) &&
646 "Kill and Def maps aren't consistent for AntiDepReg!");
648 RegRefs.erase(AntiDepReg);
649 LastNewReg[AntiDepReg] = NewReg;
654 ScanInstruction(MI, Count);