1 //===----- CriticalAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the CriticalAntiDepBreaker class, which
11 // implements register anti-dependence breaking along a blocks
12 // critical path during post-RA scheduler.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "post-RA-sched"
17 #include "CriticalAntiDepBreaker.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
29 CriticalAntiDepBreaker::
30 CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI) :
31 AntiDepBreaker(), MF(MFi),
33 TII(MF.getTarget().getInstrInfo()),
34 TRI(MF.getTarget().getRegisterInfo()),
36 Classes(TRI->getNumRegs(), static_cast<const TargetRegisterClass *>(0)),
37 KillIndices(TRI->getNumRegs(), 0),
38 DefIndices(TRI->getNumRegs(), 0) {}
40 CriticalAntiDepBreaker::~CriticalAntiDepBreaker() {
43 void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
44 const unsigned BBSize = BB->size();
45 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
46 // Clear out the register class data.
47 Classes[i] = static_cast<const TargetRegisterClass *>(0);
49 // Initialize the indices to indicate that no registers are live.
51 DefIndices[i] = BBSize;
54 // Clear "do not change" set.
57 bool IsReturnBlock = (!BB->empty() && BB->back().isReturn());
59 // Determine the live-out physregs for this block.
61 // In a return block, examine the function live-out regs.
62 for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
63 E = MRI.liveout_end(); I != E; ++I) {
65 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
66 KillIndices[Reg] = BB->size();
67 DefIndices[Reg] = ~0u;
69 // Repeat, for all aliases.
70 for (const uint16_t *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
71 unsigned AliasReg = *Alias;
72 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
73 KillIndices[AliasReg] = BB->size();
74 DefIndices[AliasReg] = ~0u;
79 // In a non-return block, examine the live-in regs of all successors.
80 // Note a return block can have successors if the return instruction is
82 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
83 SE = BB->succ_end(); SI != SE; ++SI)
84 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
85 E = (*SI)->livein_end(); I != E; ++I) {
87 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
88 KillIndices[Reg] = BB->size();
89 DefIndices[Reg] = ~0u;
91 // Repeat, for all aliases.
92 for (const uint16_t *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
93 unsigned AliasReg = *Alias;
94 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
95 KillIndices[AliasReg] = BB->size();
96 DefIndices[AliasReg] = ~0u;
100 // Mark live-out callee-saved registers. In a return block this is
101 // all callee-saved registers. In non-return this is any
102 // callee-saved register that is not saved in the prolog.
103 const MachineFrameInfo *MFI = MF.getFrameInfo();
104 BitVector Pristine = MFI->getPristineRegs(BB);
105 for (const uint16_t *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
107 if (!IsReturnBlock && !Pristine.test(Reg)) continue;
108 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
109 KillIndices[Reg] = BB->size();
110 DefIndices[Reg] = ~0u;
112 // Repeat, for all aliases.
113 for (const uint16_t *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
114 unsigned AliasReg = *Alias;
115 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
116 KillIndices[AliasReg] = BB->size();
117 DefIndices[AliasReg] = ~0u;
122 void CriticalAntiDepBreaker::FinishBlock() {
127 void CriticalAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
128 unsigned InsertPosIndex) {
129 if (MI->isDebugValue())
131 assert(Count < InsertPosIndex && "Instruction index out of expected range!");
133 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
134 if (KillIndices[Reg] != ~0u) {
135 // If Reg is currently live, then mark that it can't be renamed as
136 // we don't know the extent of its live-range anymore (now that it
137 // has been scheduled).
138 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
139 KillIndices[Reg] = Count;
140 } else if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
141 // Any register which was defined within the previous scheduling region
142 // may have been rescheduled and its lifetime may overlap with registers
143 // in ways not reflected in our current liveness state. For each such
144 // register, adjust the liveness state to be conservatively correct.
145 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
147 // Move the def index to the end of the previous region, to reflect
148 // that the def could theoretically have been scheduled at the end.
149 DefIndices[Reg] = InsertPosIndex;
153 PrescanInstruction(MI);
154 ScanInstruction(MI, Count);
157 /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
159 static const SDep *CriticalPathStep(const SUnit *SU) {
160 const SDep *Next = 0;
161 unsigned NextDepth = 0;
162 // Find the predecessor edge with the greatest depth.
163 for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
165 const SUnit *PredSU = P->getSUnit();
166 unsigned PredLatency = P->getLatency();
167 unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
168 // In the case of a latency tie, prefer an anti-dependency edge over
169 // other types of edges.
170 if (NextDepth < PredTotalLatency ||
171 (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
172 NextDepth = PredTotalLatency;
179 void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) {
180 // It's not safe to change register allocation for source operands of
181 // that have special allocation requirements. Also assume all registers
182 // used in a call must not be changed (ABI).
183 // FIXME: The issue with predicated instruction is more complex. We are being
184 // conservative here because the kill markers cannot be trusted after
186 // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
188 // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
189 // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
190 // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
192 // The first R6 kill is not really a kill since it's killed by a predicated
193 // instruction which may not be executed. The second R6 def may or may not
194 // re-define R6 so it's not safe to change it since the last R6 use cannot be
196 bool Special = MI->isCall() ||
197 MI->hasExtraSrcRegAllocReq() ||
198 TII->isPredicated(MI);
200 // Scan the register operands for this instruction and update
201 // Classes and RegRefs.
202 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
203 MachineOperand &MO = MI->getOperand(i);
204 if (!MO.isReg()) continue;
205 unsigned Reg = MO.getReg();
206 if (Reg == 0) continue;
207 const TargetRegisterClass *NewRC = 0;
209 if (i < MI->getDesc().getNumOperands())
210 NewRC = TII->getRegClass(MI->getDesc(), i, TRI);
212 // For now, only allow the register to be changed if its register
213 // class is consistent across all uses.
214 if (!Classes[Reg] && NewRC)
215 Classes[Reg] = NewRC;
216 else if (!NewRC || Classes[Reg] != NewRC)
217 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
219 // Now check for aliases.
220 for (const uint16_t *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
221 // If an alias of the reg is used during the live range, give up.
222 // Note that this allows us to skip checking if AntiDepReg
223 // overlaps with any of the aliases, among other things.
224 unsigned AliasReg = *Alias;
225 if (Classes[AliasReg]) {
226 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
227 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
231 // If we're still willing to consider this register, note the reference.
232 if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
233 RegRefs.insert(std::make_pair(Reg, &MO));
235 if (MO.isUse() && Special) {
236 if (KeepRegs.insert(Reg)) {
237 for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
239 KeepRegs.insert(*Subreg);
245 void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
248 // Proceding upwards, registers that are defed but not used in this
249 // instruction are now dead.
251 if (!TII->isPredicated(MI)) {
252 // Predicated defs are modeled as read + write, i.e. similar to two
254 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
255 MachineOperand &MO = MI->getOperand(i);
258 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
259 if (MO.clobbersPhysReg(i)) {
260 DefIndices[i] = Count;
261 KillIndices[i] = ~0u;
267 if (!MO.isReg()) continue;
268 unsigned Reg = MO.getReg();
269 if (Reg == 0) continue;
270 if (!MO.isDef()) continue;
271 // Ignore two-addr defs.
272 if (MI->isRegTiedToUseOperand(i)) continue;
274 DefIndices[Reg] = Count;
275 KillIndices[Reg] = ~0u;
276 assert(((KillIndices[Reg] == ~0u) !=
277 (DefIndices[Reg] == ~0u)) &&
278 "Kill and Def maps aren't consistent for Reg!");
282 // Repeat, for all subregs.
283 for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
285 unsigned SubregReg = *Subreg;
286 DefIndices[SubregReg] = Count;
287 KillIndices[SubregReg] = ~0u;
288 KeepRegs.erase(SubregReg);
289 Classes[SubregReg] = 0;
290 RegRefs.erase(SubregReg);
292 // Conservatively mark super-registers as unusable.
293 for (const uint16_t *Super = TRI->getSuperRegisters(Reg);
295 unsigned SuperReg = *Super;
296 Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1);
300 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
301 MachineOperand &MO = MI->getOperand(i);
302 if (!MO.isReg()) continue;
303 unsigned Reg = MO.getReg();
304 if (Reg == 0) continue;
305 if (!MO.isUse()) continue;
307 const TargetRegisterClass *NewRC = 0;
308 if (i < MI->getDesc().getNumOperands())
309 NewRC = TII->getRegClass(MI->getDesc(), i, TRI);
311 // For now, only allow the register to be changed if its register
312 // class is consistent across all uses.
313 if (!Classes[Reg] && NewRC)
314 Classes[Reg] = NewRC;
315 else if (!NewRC || Classes[Reg] != NewRC)
316 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
318 RegRefs.insert(std::make_pair(Reg, &MO));
320 // It wasn't previously live but now it is, this is a kill.
321 if (KillIndices[Reg] == ~0u) {
322 KillIndices[Reg] = Count;
323 DefIndices[Reg] = ~0u;
324 assert(((KillIndices[Reg] == ~0u) !=
325 (DefIndices[Reg] == ~0u)) &&
326 "Kill and Def maps aren't consistent for Reg!");
328 // Repeat, for all aliases.
329 for (const uint16_t *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
330 unsigned AliasReg = *Alias;
331 if (KillIndices[AliasReg] == ~0u) {
332 KillIndices[AliasReg] = Count;
333 DefIndices[AliasReg] = ~0u;
339 // Check all machine operands that reference the antidependent register and must
340 // be replaced by NewReg. Return true if any of their parent instructions may
341 // clobber the new register.
343 // Note: AntiDepReg may be referenced by a two-address instruction such that
344 // it's use operand is tied to a def operand. We guard against the case in which
345 // the two-address instruction also defines NewReg, as may happen with
346 // pre/postincrement loads. In this case, both the use and def operands are in
347 // RegRefs because the def is inserted by PrescanInstruction and not erased
348 // during ScanInstruction. So checking for an instructions with definitions of
349 // both NewReg and AntiDepReg covers it.
351 CriticalAntiDepBreaker::isNewRegClobberedByRefs(RegRefIter RegRefBegin,
352 RegRefIter RegRefEnd,
355 for (RegRefIter I = RegRefBegin; I != RegRefEnd; ++I ) {
356 MachineOperand *RefOper = I->second;
358 // Don't allow the instruction defining AntiDepReg to earlyclobber its
359 // operands, in case they may be assigned to NewReg. In this case antidep
360 // breaking must fail, but it's too rare to bother optimizing.
361 if (RefOper->isDef() && RefOper->isEarlyClobber())
364 // Handle cases in which this instructions defines NewReg.
365 MachineInstr *MI = RefOper->getParent();
366 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
367 const MachineOperand &CheckOper = MI->getOperand(i);
369 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg))
372 if (!CheckOper.isReg() || !CheckOper.isDef() ||
373 CheckOper.getReg() != NewReg)
376 // Don't allow the instruction to define NewReg and AntiDepReg.
377 // When AntiDepReg is renamed it will be an illegal op.
378 if (RefOper->isDef())
381 // Don't allow an instruction using AntiDepReg to be earlyclobbered by
383 if (CheckOper.isEarlyClobber())
386 // Don't allow inline asm to define NewReg at all. Who know what it's
388 if (MI->isInlineAsm())
396 CriticalAntiDepBreaker::findSuitableFreeRegister(RegRefIter RegRefBegin,
397 RegRefIter RegRefEnd,
400 const TargetRegisterClass *RC)
402 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC);
403 for (unsigned i = 0; i != Order.size(); ++i) {
404 unsigned NewReg = Order[i];
405 // Don't replace a register with itself.
406 if (NewReg == AntiDepReg) continue;
407 // Don't replace a register with one that was recently used to repair
408 // an anti-dependence with this AntiDepReg, because that would
409 // re-introduce that anti-dependence.
410 if (NewReg == LastNewReg) continue;
411 // If any instructions that define AntiDepReg also define the NewReg, it's
412 // not suitable. For example, Instruction with multiple definitions can
413 // result in this condition.
414 if (isNewRegClobberedByRefs(RegRefBegin, RegRefEnd, NewReg)) continue;
415 // If NewReg is dead and NewReg's most recent def is not before
416 // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
417 assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u))
418 && "Kill and Def maps aren't consistent for AntiDepReg!");
419 assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u))
420 && "Kill and Def maps aren't consistent for NewReg!");
421 if (KillIndices[NewReg] != ~0u ||
422 Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
423 KillIndices[AntiDepReg] > DefIndices[NewReg])
428 // No registers are free and available!
432 unsigned CriticalAntiDepBreaker::
433 BreakAntiDependencies(const std::vector<SUnit>& SUnits,
434 MachineBasicBlock::iterator Begin,
435 MachineBasicBlock::iterator End,
436 unsigned InsertPosIndex,
437 DbgValueVector &DbgValues) {
438 // The code below assumes that there is at least one instruction,
439 // so just duck out immediately if the block is empty.
440 if (SUnits.empty()) return 0;
442 // Keep a map of the MachineInstr*'s back to the SUnit representing them.
443 // This is used for updating debug information.
445 // FIXME: Replace this with the existing map in ScheduleDAGInstrs::MISUnitMap
446 DenseMap<MachineInstr*,const SUnit*> MISUnitMap;
448 // Find the node at the bottom of the critical path.
449 const SUnit *Max = 0;
450 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
451 const SUnit *SU = &SUnits[i];
452 MISUnitMap[SU->getInstr()] = SU;
453 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
459 DEBUG(dbgs() << "Critical path has total latency "
460 << (Max->getDepth() + Max->Latency) << "\n");
461 DEBUG(dbgs() << "Available regs:");
462 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
463 if (KillIndices[Reg] == ~0u)
464 DEBUG(dbgs() << " " << TRI->getName(Reg));
466 DEBUG(dbgs() << '\n');
470 // Track progress along the critical path through the SUnit graph as we walk
472 const SUnit *CriticalPathSU = Max;
473 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
475 // Consider this pattern:
484 // There are three anti-dependencies here, and without special care,
485 // we'd break all of them using the same register:
494 // because at each anti-dependence, B is the first register that
495 // isn't A which is free. This re-introduces anti-dependencies
496 // at all but one of the original anti-dependencies that we were
497 // trying to break. To avoid this, keep track of the most recent
498 // register that each register was replaced with, avoid
499 // using it to repair an anti-dependence on the same register.
500 // This lets us produce this:
509 // This still has an anti-dependence on B, but at least it isn't on the
510 // original critical path.
512 // TODO: If we tracked more than one register here, we could potentially
513 // fix that remaining critical edge too. This is a little more involved,
514 // because unlike the most recent register, less recent registers should
515 // still be considered, though only if no other registers are available.
516 std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0);
518 // Attempt to break anti-dependence edges on the critical path. Walk the
519 // instructions from the bottom up, tracking information about liveness
520 // as we go to help determine which registers are available.
522 unsigned Count = InsertPosIndex - 1;
523 for (MachineBasicBlock::iterator I = End, E = Begin;
525 MachineInstr *MI = --I;
526 if (MI->isDebugValue())
529 // Check if this instruction has a dependence on the critical path that
530 // is an anti-dependence that we may be able to break. If it is, set
531 // AntiDepReg to the non-zero register associated with the anti-dependence.
533 // We limit our attention to the critical path as a heuristic to avoid
534 // breaking anti-dependence edges that aren't going to significantly
535 // impact the overall schedule. There are a limited number of registers
536 // and we want to save them for the important edges.
538 // TODO: Instructions with multiple defs could have multiple
539 // anti-dependencies. The current code here only knows how to break one
540 // edge per instruction. Note that we'd have to be able to break all of
541 // the anti-dependencies in an instruction in order to be effective.
542 unsigned AntiDepReg = 0;
543 if (MI == CriticalPathMI) {
544 if (const SDep *Edge = CriticalPathStep(CriticalPathSU)) {
545 const SUnit *NextSU = Edge->getSUnit();
547 // Only consider anti-dependence edges.
548 if (Edge->getKind() == SDep::Anti) {
549 AntiDepReg = Edge->getReg();
550 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
551 if (!RegClassInfo.isAllocatable(AntiDepReg))
552 // Don't break anti-dependencies on non-allocatable registers.
554 else if (KeepRegs.count(AntiDepReg))
555 // Don't break anti-dependencies if an use down below requires
556 // this exact register.
559 // If the SUnit has other dependencies on the SUnit that it
560 // anti-depends on, don't bother breaking the anti-dependency
561 // since those edges would prevent such units from being
562 // scheduled past each other regardless.
564 // Also, if there are dependencies on other SUnits with the
565 // same register as the anti-dependency, don't attempt to
567 for (SUnit::const_pred_iterator P = CriticalPathSU->Preds.begin(),
568 PE = CriticalPathSU->Preds.end(); P != PE; ++P)
569 if (P->getSUnit() == NextSU ?
570 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
571 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
577 CriticalPathSU = NextSU;
578 CriticalPathMI = CriticalPathSU->getInstr();
580 // We've reached the end of the critical path.
586 PrescanInstruction(MI);
588 // If MI's defs have a special allocation requirement, don't allow
589 // any def registers to be changed. Also assume all registers
590 // defined in a call must not be changed (ABI).
591 if (MI->isCall() || MI->hasExtraDefRegAllocReq() ||
592 TII->isPredicated(MI))
593 // If this instruction's defs have special allocation requirement, don't
594 // break this anti-dependency.
596 else if (AntiDepReg) {
597 // If this instruction has a use of AntiDepReg, breaking it
599 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
600 MachineOperand &MO = MI->getOperand(i);
601 if (!MO.isReg()) continue;
602 unsigned Reg = MO.getReg();
603 if (Reg == 0) continue;
604 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) {
611 // Determine AntiDepReg's register class, if it is live and is
612 // consistently used within a single class.
613 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0;
614 assert((AntiDepReg == 0 || RC != NULL) &&
615 "Register should be live if it's causing an anti-dependence!");
616 if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
619 // Look for a suitable register to use to break the anti-depenence.
621 // TODO: Instead of picking the first free register, consider which might
623 if (AntiDepReg != 0) {
624 std::pair<std::multimap<unsigned, MachineOperand *>::iterator,
625 std::multimap<unsigned, MachineOperand *>::iterator>
626 Range = RegRefs.equal_range(AntiDepReg);
627 if (unsigned NewReg = findSuitableFreeRegister(Range.first, Range.second,
629 LastNewReg[AntiDepReg],
631 DEBUG(dbgs() << "Breaking anti-dependence edge on "
632 << TRI->getName(AntiDepReg)
633 << " with " << RegRefs.count(AntiDepReg) << " references"
634 << " using " << TRI->getName(NewReg) << "!\n");
636 // Update the references to the old register to refer to the new
638 for (std::multimap<unsigned, MachineOperand *>::iterator
639 Q = Range.first, QE = Range.second; Q != QE; ++Q) {
640 Q->second->setReg(NewReg);
641 // If the SU for the instruction being updated has debug information
642 // related to the anti-dependency register, make sure to update that
644 const SUnit *SU = MISUnitMap[Q->second->getParent()];
646 for (DbgValueVector::iterator DVI = DbgValues.begin(),
647 DVE = DbgValues.end(); DVI != DVE; ++DVI)
648 if (DVI->second == Q->second->getParent())
649 UpdateDbgValue(DVI->first, AntiDepReg, NewReg);
652 // We just went back in time and modified history; the
653 // liveness information for the anti-dependence reg is now
654 // inconsistent. Set the state as if it were dead.
655 Classes[NewReg] = Classes[AntiDepReg];
656 DefIndices[NewReg] = DefIndices[AntiDepReg];
657 KillIndices[NewReg] = KillIndices[AntiDepReg];
658 assert(((KillIndices[NewReg] == ~0u) !=
659 (DefIndices[NewReg] == ~0u)) &&
660 "Kill and Def maps aren't consistent for NewReg!");
662 Classes[AntiDepReg] = 0;
663 DefIndices[AntiDepReg] = KillIndices[AntiDepReg];
664 KillIndices[AntiDepReg] = ~0u;
665 assert(((KillIndices[AntiDepReg] == ~0u) !=
666 (DefIndices[AntiDepReg] == ~0u)) &&
667 "Kill and Def maps aren't consistent for AntiDepReg!");
669 RegRefs.erase(AntiDepReg);
670 LastNewReg[AntiDepReg] = NewReg;
675 ScanInstruction(MI, Count);