1 //===----- CriticalAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the CriticalAntiDepBreaker class, which
11 // implements register anti-dependence breaking along a blocks
12 // critical path during post-RA scheduler.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "post-RA-sched"
17 #include "CriticalAntiDepBreaker.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
29 CriticalAntiDepBreaker::
30 CriticalAntiDepBreaker(MachineFunction& MFi) :
31 AntiDepBreaker(), MF(MFi),
33 TII(MF.getTarget().getInstrInfo()),
34 TRI(MF.getTarget().getRegisterInfo()),
35 AllocatableSet(TRI->getAllocatableSet(MF))
39 CriticalAntiDepBreaker::~CriticalAntiDepBreaker() {
42 void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
43 // Clear out the register class data.
44 std::fill(Classes, array_endof(Classes),
45 static_cast<const TargetRegisterClass *>(0));
47 // Initialize the indices to indicate that no registers are live.
48 const unsigned BBSize = BB->size();
49 for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
51 DefIndices[i] = BBSize;
54 // Clear "do not change" set.
57 bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn());
59 // Determine the live-out physregs for this block.
61 // In a return block, examine the function live-out regs.
62 for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
63 E = MRI.liveout_end(); I != E; ++I) {
65 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
66 KillIndices[Reg] = BB->size();
67 DefIndices[Reg] = ~0u;
68 // Repeat, for all aliases.
69 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
70 unsigned AliasReg = *Alias;
71 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
72 KillIndices[AliasReg] = BB->size();
73 DefIndices[AliasReg] = ~0u;
78 // In a non-return block, examine the live-in regs of all successors.
79 // Note a return block can have successors if the return instruction is
81 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
82 SE = BB->succ_end(); SI != SE; ++SI)
83 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
84 E = (*SI)->livein_end(); I != E; ++I) {
86 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
87 KillIndices[Reg] = BB->size();
88 DefIndices[Reg] = ~0u;
89 // Repeat, for all aliases.
90 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
91 unsigned AliasReg = *Alias;
92 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
93 KillIndices[AliasReg] = BB->size();
94 DefIndices[AliasReg] = ~0u;
98 // Mark live-out callee-saved registers. In a return block this is
99 // all callee-saved registers. In non-return this is any
100 // callee-saved register that is not saved in the prolog.
101 const MachineFrameInfo *MFI = MF.getFrameInfo();
102 BitVector Pristine = MFI->getPristineRegs(BB);
103 for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
105 if (!IsReturnBlock && !Pristine.test(Reg)) continue;
106 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
107 KillIndices[Reg] = BB->size();
108 DefIndices[Reg] = ~0u;
109 // Repeat, for all aliases.
110 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
111 unsigned AliasReg = *Alias;
112 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
113 KillIndices[AliasReg] = BB->size();
114 DefIndices[AliasReg] = ~0u;
119 void CriticalAntiDepBreaker::FinishBlock() {
124 void CriticalAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
125 unsigned InsertPosIndex) {
126 if (MI->isDebugValue())
128 assert(Count < InsertPosIndex && "Instruction index out of expected range!");
130 // Any register which was defined within the previous scheduling region
131 // may have been rescheduled and its lifetime may overlap with registers
132 // in ways not reflected in our current liveness state. For each such
133 // register, adjust the liveness state to be conservatively correct.
134 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg)
135 if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
136 assert(KillIndices[Reg] == ~0u && "Clobbered register is live!");
137 // Mark this register to be non-renamable.
138 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
139 // Move the def index to the end of the previous region, to reflect
140 // that the def could theoretically have been scheduled at the end.
141 DefIndices[Reg] = InsertPosIndex;
144 PrescanInstruction(MI);
145 ScanInstruction(MI, Count);
148 /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
150 static const SDep *CriticalPathStep(const SUnit *SU) {
151 const SDep *Next = 0;
152 unsigned NextDepth = 0;
153 // Find the predecessor edge with the greatest depth.
154 for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
156 const SUnit *PredSU = P->getSUnit();
157 unsigned PredLatency = P->getLatency();
158 unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
159 // In the case of a latency tie, prefer an anti-dependency edge over
160 // other types of edges.
161 if (NextDepth < PredTotalLatency ||
162 (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
163 NextDepth = PredTotalLatency;
170 void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) {
171 // It's not safe to change register allocation for source operands of
172 // that have special allocation requirements. Also assume all registers
173 // used in a call must not be changed (ABI).
174 // FIXME: The issue with predicated instruction is more complex. We are being
175 // conservatively here because the kill markers cannot be trusted after
177 // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
179 // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
180 // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
181 // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
183 // The first R6 kill is not really a kill since it's killed by a predicated
184 // instruction which may not be executed. The second R6 def may or may not
185 // re-define R6 so it's not safe to change it since the last R6 use cannot be
187 bool Special = MI->getDesc().isCall() ||
188 MI->getDesc().hasExtraSrcRegAllocReq() ||
189 TII->isPredicated(MI);
191 // Scan the register operands for this instruction and update
192 // Classes and RegRefs.
193 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
194 MachineOperand &MO = MI->getOperand(i);
195 if (!MO.isReg()) continue;
196 unsigned Reg = MO.getReg();
197 if (Reg == 0) continue;
198 const TargetRegisterClass *NewRC = 0;
200 if (i < MI->getDesc().getNumOperands())
201 NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI);
203 // For now, only allow the register to be changed if its register
204 // class is consistent across all uses.
205 if (!Classes[Reg] && NewRC)
206 Classes[Reg] = NewRC;
207 else if (!NewRC || Classes[Reg] != NewRC)
208 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
210 // Now check for aliases.
211 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
212 // If an alias of the reg is used during the live range, give up.
213 // Note that this allows us to skip checking if AntiDepReg
214 // overlaps with any of the aliases, among other things.
215 unsigned AliasReg = *Alias;
216 if (Classes[AliasReg]) {
217 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
218 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
222 // If we're still willing to consider this register, note the reference.
223 if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
224 RegRefs.insert(std::make_pair(Reg, &MO));
226 if (MO.isUse() && Special) {
227 if (KeepRegs.insert(Reg)) {
228 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
230 KeepRegs.insert(*Subreg);
236 void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
239 // Proceding upwards, registers that are defed but not used in this
240 // instruction are now dead.
242 if (!TII->isPredicated(MI)) {
243 // Predicated defs are modeled as read + write, i.e. similar to two
245 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
246 MachineOperand &MO = MI->getOperand(i);
247 if (!MO.isReg()) continue;
248 unsigned Reg = MO.getReg();
249 if (Reg == 0) continue;
250 if (!MO.isDef()) continue;
251 // Ignore two-addr defs.
252 if (MI->isRegTiedToUseOperand(i)) continue;
254 DefIndices[Reg] = Count;
255 KillIndices[Reg] = ~0u;
256 assert(((KillIndices[Reg] == ~0u) !=
257 (DefIndices[Reg] == ~0u)) &&
258 "Kill and Def maps aren't consistent for Reg!");
262 // Repeat, for all subregs.
263 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
265 unsigned SubregReg = *Subreg;
266 DefIndices[SubregReg] = Count;
267 KillIndices[SubregReg] = ~0u;
268 KeepRegs.erase(SubregReg);
269 Classes[SubregReg] = 0;
270 RegRefs.erase(SubregReg);
272 // Conservatively mark super-registers as unusable.
273 for (const unsigned *Super = TRI->getSuperRegisters(Reg);
275 unsigned SuperReg = *Super;
276 Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1);
280 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
281 MachineOperand &MO = MI->getOperand(i);
282 if (!MO.isReg()) continue;
283 unsigned Reg = MO.getReg();
284 if (Reg == 0) continue;
285 if (!MO.isUse()) continue;
287 const TargetRegisterClass *NewRC = 0;
288 if (i < MI->getDesc().getNumOperands())
289 NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI);
291 // For now, only allow the register to be changed if its register
292 // class is consistent across all uses.
293 if (!Classes[Reg] && NewRC)
294 Classes[Reg] = NewRC;
295 else if (!NewRC || Classes[Reg] != NewRC)
296 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
298 RegRefs.insert(std::make_pair(Reg, &MO));
300 // It wasn't previously live but now it is, this is a kill.
301 if (KillIndices[Reg] == ~0u) {
302 KillIndices[Reg] = Count;
303 DefIndices[Reg] = ~0u;
304 assert(((KillIndices[Reg] == ~0u) !=
305 (DefIndices[Reg] == ~0u)) &&
306 "Kill and Def maps aren't consistent for Reg!");
308 // Repeat, for all aliases.
309 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
310 unsigned AliasReg = *Alias;
311 if (KillIndices[AliasReg] == ~0u) {
312 KillIndices[AliasReg] = Count;
313 DefIndices[AliasReg] = ~0u;
320 CriticalAntiDepBreaker::findSuitableFreeRegister(MachineInstr *MI,
323 const TargetRegisterClass *RC)
325 for (TargetRegisterClass::iterator R = RC->allocation_order_begin(MF),
326 RE = RC->allocation_order_end(MF); R != RE; ++R) {
327 unsigned NewReg = *R;
328 // Don't replace a register with itself.
329 if (NewReg == AntiDepReg) continue;
330 // Don't replace a register with one that was recently used to repair
331 // an anti-dependence with this AntiDepReg, because that would
332 // re-introduce that anti-dependence.
333 if (NewReg == LastNewReg) continue;
334 // If the instruction already has a def of the NewReg, it's not suitable.
335 // For example, Instruction with multiple definitions can result in this
337 if (MI->modifiesRegister(NewReg, TRI)) continue;
338 // If NewReg is dead and NewReg's most recent def is not before
339 // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
340 assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u))
341 && "Kill and Def maps aren't consistent for AntiDepReg!");
342 assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u))
343 && "Kill and Def maps aren't consistent for NewReg!");
344 if (KillIndices[NewReg] != ~0u ||
345 Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
346 KillIndices[AntiDepReg] > DefIndices[NewReg])
351 // No registers are free and available!
355 unsigned CriticalAntiDepBreaker::
356 BreakAntiDependencies(const std::vector<SUnit>& SUnits,
357 MachineBasicBlock::iterator Begin,
358 MachineBasicBlock::iterator End,
359 unsigned InsertPosIndex) {
360 // The code below assumes that there is at least one instruction,
361 // so just duck out immediately if the block is empty.
362 if (SUnits.empty()) return 0;
364 // Keep a map of the MachineInstr*'s back to the SUnit representing them.
365 // This is used for updating debug information.
366 DenseMap<MachineInstr*,const SUnit*> MISUnitMap;
368 // Find the node at the bottom of the critical path.
369 const SUnit *Max = 0;
370 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
371 const SUnit *SU = &SUnits[i];
372 MISUnitMap[SU->getInstr()] = SU;
373 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
379 DEBUG(dbgs() << "Critical path has total latency "
380 << (Max->getDepth() + Max->Latency) << "\n");
381 DEBUG(dbgs() << "Available regs:");
382 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
383 if (KillIndices[Reg] == ~0u)
384 DEBUG(dbgs() << " " << TRI->getName(Reg));
386 DEBUG(dbgs() << '\n');
390 // Track progress along the critical path through the SUnit graph as we walk
392 const SUnit *CriticalPathSU = Max;
393 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
395 // Consider this pattern:
404 // There are three anti-dependencies here, and without special care,
405 // we'd break all of them using the same register:
414 // because at each anti-dependence, B is the first register that
415 // isn't A which is free. This re-introduces anti-dependencies
416 // at all but one of the original anti-dependencies that we were
417 // trying to break. To avoid this, keep track of the most recent
418 // register that each register was replaced with, avoid
419 // using it to repair an anti-dependence on the same register.
420 // This lets us produce this:
429 // This still has an anti-dependence on B, but at least it isn't on the
430 // original critical path.
432 // TODO: If we tracked more than one register here, we could potentially
433 // fix that remaining critical edge too. This is a little more involved,
434 // because unlike the most recent register, less recent registers should
435 // still be considered, though only if no other registers are available.
436 unsigned LastNewReg[TargetRegisterInfo::FirstVirtualRegister] = {};
438 // Attempt to break anti-dependence edges on the critical path. Walk the
439 // instructions from the bottom up, tracking information about liveness
440 // as we go to help determine which registers are available.
442 unsigned Count = InsertPosIndex - 1;
443 for (MachineBasicBlock::iterator I = End, E = Begin;
445 MachineInstr *MI = --I;
446 if (MI->isDebugValue())
449 // Check if this instruction has a dependence on the critical path that
450 // is an anti-dependence that we may be able to break. If it is, set
451 // AntiDepReg to the non-zero register associated with the anti-dependence.
453 // We limit our attention to the critical path as a heuristic to avoid
454 // breaking anti-dependence edges that aren't going to significantly
455 // impact the overall schedule. There are a limited number of registers
456 // and we want to save them for the important edges.
458 // TODO: Instructions with multiple defs could have multiple
459 // anti-dependencies. The current code here only knows how to break one
460 // edge per instruction. Note that we'd have to be able to break all of
461 // the anti-dependencies in an instruction in order to be effective.
462 unsigned AntiDepReg = 0;
463 if (MI == CriticalPathMI) {
464 if (const SDep *Edge = CriticalPathStep(CriticalPathSU)) {
465 const SUnit *NextSU = Edge->getSUnit();
467 // Only consider anti-dependence edges.
468 if (Edge->getKind() == SDep::Anti) {
469 AntiDepReg = Edge->getReg();
470 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
471 if (!AllocatableSet.test(AntiDepReg))
472 // Don't break anti-dependencies on non-allocatable registers.
474 else if (KeepRegs.count(AntiDepReg))
475 // Don't break anti-dependencies if an use down below requires
476 // this exact register.
479 // If the SUnit has other dependencies on the SUnit that it
480 // anti-depends on, don't bother breaking the anti-dependency
481 // since those edges would prevent such units from being
482 // scheduled past each other regardless.
484 // Also, if there are dependencies on other SUnits with the
485 // same register as the anti-dependency, don't attempt to
487 for (SUnit::const_pred_iterator P = CriticalPathSU->Preds.begin(),
488 PE = CriticalPathSU->Preds.end(); P != PE; ++P)
489 if (P->getSUnit() == NextSU ?
490 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
491 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
497 CriticalPathSU = NextSU;
498 CriticalPathMI = CriticalPathSU->getInstr();
500 // We've reached the end of the critical path.
506 PrescanInstruction(MI);
508 // If MI's defs have a special allocation requirement, don't allow
509 // any def registers to be changed. Also assume all registers
510 // defined in a call must not be changed (ABI).
511 if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq() ||
512 TII->isPredicated(MI))
513 // If this instruction's defs have special allocation requirement, don't
514 // break this anti-dependency.
516 else if (AntiDepReg) {
517 // If this instruction has a use of AntiDepReg, breaking it
519 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
520 MachineOperand &MO = MI->getOperand(i);
521 if (!MO.isReg()) continue;
522 unsigned Reg = MO.getReg();
523 if (Reg == 0) continue;
524 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) {
531 // Determine AntiDepReg's register class, if it is live and is
532 // consistently used within a single class.
533 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0;
534 assert((AntiDepReg == 0 || RC != NULL) &&
535 "Register should be live if it's causing an anti-dependence!");
536 if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
539 // Look for a suitable register to use to break the anti-depenence.
541 // TODO: Instead of picking the first free register, consider which might
543 if (AntiDepReg != 0) {
544 if (unsigned NewReg = findSuitableFreeRegister(MI, AntiDepReg,
545 LastNewReg[AntiDepReg],
547 DEBUG(dbgs() << "Breaking anti-dependence edge on "
548 << TRI->getName(AntiDepReg)
549 << " with " << RegRefs.count(AntiDepReg) << " references"
550 << " using " << TRI->getName(NewReg) << "!\n");
552 // Update the references to the old register to refer to the new
554 std::pair<std::multimap<unsigned, MachineOperand *>::iterator,
555 std::multimap<unsigned, MachineOperand *>::iterator>
556 Range = RegRefs.equal_range(AntiDepReg);
557 for (std::multimap<unsigned, MachineOperand *>::iterator
558 Q = Range.first, QE = Range.second; Q != QE; ++Q) {
559 Q->second->setReg(NewReg);
560 // If the SU for the instruction being updated has debug information
561 // related to the anti-dependency register, make sure to update that
563 const SUnit *SU = MISUnitMap[Q->second->getParent()];
565 for (unsigned i = 0, e = SU->DbgInstrList.size() ; i < e ; ++i) {
566 MachineInstr *DI = SU->DbgInstrList[i];
567 assert (DI->getNumOperands()==3 && DI->getOperand(0).isReg() &&
568 DI->getOperand(0).getReg()
569 && "Non register dbg_value attached to SUnit!");
570 if (DI->getOperand(0).getReg() == AntiDepReg)
571 DI->getOperand(0).setReg(NewReg);
575 // We just went back in time and modified history; the
576 // liveness information for the anti-depenence reg is now
577 // inconsistent. Set the state as if it were dead.
578 Classes[NewReg] = Classes[AntiDepReg];
579 DefIndices[NewReg] = DefIndices[AntiDepReg];
580 KillIndices[NewReg] = KillIndices[AntiDepReg];
581 assert(((KillIndices[NewReg] == ~0u) !=
582 (DefIndices[NewReg] == ~0u)) &&
583 "Kill and Def maps aren't consistent for NewReg!");
585 Classes[AntiDepReg] = 0;
586 DefIndices[AntiDepReg] = KillIndices[AntiDepReg];
587 KillIndices[AntiDepReg] = ~0u;
588 assert(((KillIndices[AntiDepReg] == ~0u) !=
589 (DefIndices[AntiDepReg] == ~0u)) &&
590 "Kill and Def maps aren't consistent for AntiDepReg!");
592 RegRefs.erase(AntiDepReg);
593 LastNewReg[AntiDepReg] = NewReg;
598 ScanInstruction(MI, Count);