1 //===----- CriticalAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the CriticalAntiDepBreaker class, which
11 // implements register anti-dependence breaking along a blocks
12 // critical path during post-RA scheduler.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "post-RA-sched"
17 #include "CriticalAntiDepBreaker.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetRegisterInfo.h"
29 CriticalAntiDepBreaker::
30 CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI) :
31 AntiDepBreaker(), MF(MFi),
33 TII(MF.getTarget().getInstrInfo()),
34 TRI(MF.getTarget().getRegisterInfo()),
36 Classes(TRI->getNumRegs(), static_cast<const TargetRegisterClass *>(0)),
37 KillIndices(TRI->getNumRegs(), 0),
38 DefIndices(TRI->getNumRegs(), 0),
39 KeepRegs(TRI->getNumRegs(), false) {}
41 CriticalAntiDepBreaker::~CriticalAntiDepBreaker() {
44 void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
45 const unsigned BBSize = BB->size();
46 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
47 // Clear out the register class data.
48 Classes[i] = static_cast<const TargetRegisterClass *>(0);
50 // Initialize the indices to indicate that no registers are live.
52 DefIndices[i] = BBSize;
55 // Clear "do not change" set.
58 bool IsReturnBlock = (BBSize != 0 && BB->back().isReturn());
60 // Determine the live-out physregs for this block.
62 // In a return block, examine the function live-out regs.
63 for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
64 E = MRI.liveout_end(); I != E; ++I) {
65 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
67 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
68 KillIndices[Reg] = BBSize;
69 DefIndices[Reg] = ~0u;
74 // In a non-return block, examine the live-in regs of all successors.
75 // Note a return block can have successors if the return instruction is
77 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
78 SE = BB->succ_end(); SI != SE; ++SI)
79 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
80 E = (*SI)->livein_end(); I != E; ++I) {
81 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
83 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
84 KillIndices[Reg] = BBSize;
85 DefIndices[Reg] = ~0u;
89 // Mark live-out callee-saved registers. In a return block this is
90 // all callee-saved registers. In non-return this is any
91 // callee-saved register that is not saved in the prolog.
92 const MachineFrameInfo *MFI = MF.getFrameInfo();
93 BitVector Pristine = MFI->getPristineRegs(BB);
94 for (const uint16_t *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
95 if (!IsReturnBlock && !Pristine.test(*I)) continue;
96 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
98 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
99 KillIndices[Reg] = BBSize;
100 DefIndices[Reg] = ~0u;
105 void CriticalAntiDepBreaker::FinishBlock() {
110 void CriticalAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
111 unsigned InsertPosIndex) {
112 if (MI->isDebugValue())
114 assert(Count < InsertPosIndex && "Instruction index out of expected range!");
116 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
117 if (KillIndices[Reg] != ~0u) {
118 // If Reg is currently live, then mark that it can't be renamed as
119 // we don't know the extent of its live-range anymore (now that it
120 // has been scheduled).
121 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
122 KillIndices[Reg] = Count;
123 } else if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
124 // Any register which was defined within the previous scheduling region
125 // may have been rescheduled and its lifetime may overlap with registers
126 // in ways not reflected in our current liveness state. For each such
127 // register, adjust the liveness state to be conservatively correct.
128 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
130 // Move the def index to the end of the previous region, to reflect
131 // that the def could theoretically have been scheduled at the end.
132 DefIndices[Reg] = InsertPosIndex;
136 PrescanInstruction(MI);
137 ScanInstruction(MI, Count);
140 /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
142 static const SDep *CriticalPathStep(const SUnit *SU) {
143 const SDep *Next = 0;
144 unsigned NextDepth = 0;
145 // Find the predecessor edge with the greatest depth.
146 for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
148 const SUnit *PredSU = P->getSUnit();
149 unsigned PredLatency = P->getLatency();
150 unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
151 // In the case of a latency tie, prefer an anti-dependency edge over
152 // other types of edges.
153 if (NextDepth < PredTotalLatency ||
154 (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
155 NextDepth = PredTotalLatency;
162 void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) {
163 // It's not safe to change register allocation for source operands of
164 // that have special allocation requirements. Also assume all registers
165 // used in a call must not be changed (ABI).
166 // FIXME: The issue with predicated instruction is more complex. We are being
167 // conservative here because the kill markers cannot be trusted after
169 // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
171 // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
172 // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
173 // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
175 // The first R6 kill is not really a kill since it's killed by a predicated
176 // instruction which may not be executed. The second R6 def may or may not
177 // re-define R6 so it's not safe to change it since the last R6 use cannot be
179 bool Special = MI->isCall() ||
180 MI->hasExtraSrcRegAllocReq() ||
181 TII->isPredicated(MI);
183 // Scan the register operands for this instruction and update
184 // Classes and RegRefs.
185 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
186 MachineOperand &MO = MI->getOperand(i);
187 if (!MO.isReg()) continue;
188 unsigned Reg = MO.getReg();
189 if (Reg == 0) continue;
190 const TargetRegisterClass *NewRC = 0;
192 if (i < MI->getDesc().getNumOperands())
193 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
195 // For now, only allow the register to be changed if its register
196 // class is consistent across all uses.
197 if (!Classes[Reg] && NewRC)
198 Classes[Reg] = NewRC;
199 else if (!NewRC || Classes[Reg] != NewRC)
200 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
202 // Now check for aliases.
203 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
204 // If an alias of the reg is used during the live range, give up.
205 // Note that this allows us to skip checking if AntiDepReg
206 // overlaps with any of the aliases, among other things.
207 unsigned AliasReg = *AI;
208 if (Classes[AliasReg]) {
209 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
210 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
214 // If we're still willing to consider this register, note the reference.
215 if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
216 RegRefs.insert(std::make_pair(Reg, &MO));
218 if (MO.isUse() && Special) {
219 if (!KeepRegs.test(Reg)) {
221 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
222 KeepRegs.set(*SubRegs);
228 void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
231 // Proceeding upwards, registers that are defed but not used in this
232 // instruction are now dead.
234 if (!TII->isPredicated(MI)) {
235 // Predicated defs are modeled as read + write, i.e. similar to two
237 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
238 MachineOperand &MO = MI->getOperand(i);
241 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
242 if (MO.clobbersPhysReg(i)) {
243 DefIndices[i] = Count;
244 KillIndices[i] = ~0u;
250 if (!MO.isReg()) continue;
251 unsigned Reg = MO.getReg();
252 if (Reg == 0) continue;
253 if (!MO.isDef()) continue;
254 // Ignore two-addr defs.
255 if (MI->isRegTiedToUseOperand(i)) continue;
257 DefIndices[Reg] = Count;
258 KillIndices[Reg] = ~0u;
259 assert(((KillIndices[Reg] == ~0u) !=
260 (DefIndices[Reg] == ~0u)) &&
261 "Kill and Def maps aren't consistent for Reg!");
265 // Repeat, for all subregs.
266 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
267 unsigned SubregReg = *SubRegs;
268 DefIndices[SubregReg] = Count;
269 KillIndices[SubregReg] = ~0u;
270 KeepRegs.reset(SubregReg);
271 Classes[SubregReg] = 0;
272 RegRefs.erase(SubregReg);
274 // Conservatively mark super-registers as unusable.
275 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR)
276 Classes[*SR] = reinterpret_cast<TargetRegisterClass *>(-1);
279 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
280 MachineOperand &MO = MI->getOperand(i);
281 if (!MO.isReg()) continue;
282 unsigned Reg = MO.getReg();
283 if (Reg == 0) continue;
284 if (!MO.isUse()) continue;
286 const TargetRegisterClass *NewRC = 0;
287 if (i < MI->getDesc().getNumOperands())
288 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
290 // For now, only allow the register to be changed if its register
291 // class is consistent across all uses.
292 if (!Classes[Reg] && NewRC)
293 Classes[Reg] = NewRC;
294 else if (!NewRC || Classes[Reg] != NewRC)
295 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
297 RegRefs.insert(std::make_pair(Reg, &MO));
299 // It wasn't previously live but now it is, this is a kill.
300 if (KillIndices[Reg] == ~0u) {
301 KillIndices[Reg] = Count;
302 DefIndices[Reg] = ~0u;
303 assert(((KillIndices[Reg] == ~0u) !=
304 (DefIndices[Reg] == ~0u)) &&
305 "Kill and Def maps aren't consistent for Reg!");
307 // Repeat, for all aliases.
308 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
309 unsigned AliasReg = *AI;
310 if (KillIndices[AliasReg] == ~0u) {
311 KillIndices[AliasReg] = Count;
312 DefIndices[AliasReg] = ~0u;
318 // Check all machine operands that reference the antidependent register and must
319 // be replaced by NewReg. Return true if any of their parent instructions may
320 // clobber the new register.
322 // Note: AntiDepReg may be referenced by a two-address instruction such that
323 // it's use operand is tied to a def operand. We guard against the case in which
324 // the two-address instruction also defines NewReg, as may happen with
325 // pre/postincrement loads. In this case, both the use and def operands are in
326 // RegRefs because the def is inserted by PrescanInstruction and not erased
327 // during ScanInstruction. So checking for an instructions with definitions of
328 // both NewReg and AntiDepReg covers it.
330 CriticalAntiDepBreaker::isNewRegClobberedByRefs(RegRefIter RegRefBegin,
331 RegRefIter RegRefEnd,
334 for (RegRefIter I = RegRefBegin; I != RegRefEnd; ++I ) {
335 MachineOperand *RefOper = I->second;
337 // Don't allow the instruction defining AntiDepReg to earlyclobber its
338 // operands, in case they may be assigned to NewReg. In this case antidep
339 // breaking must fail, but it's too rare to bother optimizing.
340 if (RefOper->isDef() && RefOper->isEarlyClobber())
343 // Handle cases in which this instructions defines NewReg.
344 MachineInstr *MI = RefOper->getParent();
345 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
346 const MachineOperand &CheckOper = MI->getOperand(i);
348 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg))
351 if (!CheckOper.isReg() || !CheckOper.isDef() ||
352 CheckOper.getReg() != NewReg)
355 // Don't allow the instruction to define NewReg and AntiDepReg.
356 // When AntiDepReg is renamed it will be an illegal op.
357 if (RefOper->isDef())
360 // Don't allow an instruction using AntiDepReg to be earlyclobbered by
362 if (CheckOper.isEarlyClobber())
365 // Don't allow inline asm to define NewReg at all. Who know what it's
367 if (MI->isInlineAsm())
374 unsigned CriticalAntiDepBreaker::
375 findSuitableFreeRegister(RegRefIter RegRefBegin,
376 RegRefIter RegRefEnd,
379 const TargetRegisterClass *RC,
380 SmallVector<unsigned, 2> &Forbid)
382 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
383 for (unsigned i = 0; i != Order.size(); ++i) {
384 unsigned NewReg = Order[i];
385 // Don't replace a register with itself.
386 if (NewReg == AntiDepReg) continue;
387 // Don't replace a register with one that was recently used to repair
388 // an anti-dependence with this AntiDepReg, because that would
389 // re-introduce that anti-dependence.
390 if (NewReg == LastNewReg) continue;
391 // If any instructions that define AntiDepReg also define the NewReg, it's
392 // not suitable. For example, Instruction with multiple definitions can
393 // result in this condition.
394 if (isNewRegClobberedByRefs(RegRefBegin, RegRefEnd, NewReg)) continue;
395 // If NewReg is dead and NewReg's most recent def is not before
396 // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
397 assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u))
398 && "Kill and Def maps aren't consistent for AntiDepReg!");
399 assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u))
400 && "Kill and Def maps aren't consistent for NewReg!");
401 if (KillIndices[NewReg] != ~0u ||
402 Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
403 KillIndices[AntiDepReg] > DefIndices[NewReg])
405 // If NewReg overlaps any of the forbidden registers, we can't use it.
406 bool Forbidden = false;
407 for (SmallVector<unsigned, 2>::iterator it = Forbid.begin(),
408 ite = Forbid.end(); it != ite; ++it)
409 if (TRI->regsOverlap(NewReg, *it)) {
413 if (Forbidden) continue;
417 // No registers are free and available!
421 unsigned CriticalAntiDepBreaker::
422 BreakAntiDependencies(const std::vector<SUnit>& SUnits,
423 MachineBasicBlock::iterator Begin,
424 MachineBasicBlock::iterator End,
425 unsigned InsertPosIndex,
426 DbgValueVector &DbgValues) {
427 // The code below assumes that there is at least one instruction,
428 // so just duck out immediately if the block is empty.
429 if (SUnits.empty()) return 0;
431 // Keep a map of the MachineInstr*'s back to the SUnit representing them.
432 // This is used for updating debug information.
434 // FIXME: Replace this with the existing map in ScheduleDAGInstrs::MISUnitMap
435 DenseMap<MachineInstr*,const SUnit*> MISUnitMap;
437 // Find the node at the bottom of the critical path.
438 const SUnit *Max = 0;
439 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
440 const SUnit *SU = &SUnits[i];
441 MISUnitMap[SU->getInstr()] = SU;
442 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
448 DEBUG(dbgs() << "Critical path has total latency "
449 << (Max->getDepth() + Max->Latency) << "\n");
450 DEBUG(dbgs() << "Available regs:");
451 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
452 if (KillIndices[Reg] == ~0u)
453 DEBUG(dbgs() << " " << TRI->getName(Reg));
455 DEBUG(dbgs() << '\n');
459 // Track progress along the critical path through the SUnit graph as we walk
461 const SUnit *CriticalPathSU = Max;
462 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
464 // Consider this pattern:
473 // There are three anti-dependencies here, and without special care,
474 // we'd break all of them using the same register:
483 // because at each anti-dependence, B is the first register that
484 // isn't A which is free. This re-introduces anti-dependencies
485 // at all but one of the original anti-dependencies that we were
486 // trying to break. To avoid this, keep track of the most recent
487 // register that each register was replaced with, avoid
488 // using it to repair an anti-dependence on the same register.
489 // This lets us produce this:
498 // This still has an anti-dependence on B, but at least it isn't on the
499 // original critical path.
501 // TODO: If we tracked more than one register here, we could potentially
502 // fix that remaining critical edge too. This is a little more involved,
503 // because unlike the most recent register, less recent registers should
504 // still be considered, though only if no other registers are available.
505 std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0);
507 // Attempt to break anti-dependence edges on the critical path. Walk the
508 // instructions from the bottom up, tracking information about liveness
509 // as we go to help determine which registers are available.
511 unsigned Count = InsertPosIndex - 1;
512 for (MachineBasicBlock::iterator I = End, E = Begin;
514 MachineInstr *MI = --I;
515 if (MI->isDebugValue())
518 // Check if this instruction has a dependence on the critical path that
519 // is an anti-dependence that we may be able to break. If it is, set
520 // AntiDepReg to the non-zero register associated with the anti-dependence.
522 // We limit our attention to the critical path as a heuristic to avoid
523 // breaking anti-dependence edges that aren't going to significantly
524 // impact the overall schedule. There are a limited number of registers
525 // and we want to save them for the important edges.
527 // TODO: Instructions with multiple defs could have multiple
528 // anti-dependencies. The current code here only knows how to break one
529 // edge per instruction. Note that we'd have to be able to break all of
530 // the anti-dependencies in an instruction in order to be effective.
531 unsigned AntiDepReg = 0;
532 if (MI == CriticalPathMI) {
533 if (const SDep *Edge = CriticalPathStep(CriticalPathSU)) {
534 const SUnit *NextSU = Edge->getSUnit();
536 // Only consider anti-dependence edges.
537 if (Edge->getKind() == SDep::Anti) {
538 AntiDepReg = Edge->getReg();
539 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
540 if (!MRI.isAllocatable(AntiDepReg))
541 // Don't break anti-dependencies on non-allocatable registers.
543 else if (KeepRegs.test(AntiDepReg))
544 // Don't break anti-dependencies if an use down below requires
545 // this exact register.
548 // If the SUnit has other dependencies on the SUnit that it
549 // anti-depends on, don't bother breaking the anti-dependency
550 // since those edges would prevent such units from being
551 // scheduled past each other regardless.
553 // Also, if there are dependencies on other SUnits with the
554 // same register as the anti-dependency, don't attempt to
556 for (SUnit::const_pred_iterator P = CriticalPathSU->Preds.begin(),
557 PE = CriticalPathSU->Preds.end(); P != PE; ++P)
558 if (P->getSUnit() == NextSU ?
559 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
560 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
566 CriticalPathSU = NextSU;
567 CriticalPathMI = CriticalPathSU->getInstr();
569 // We've reached the end of the critical path.
575 PrescanInstruction(MI);
577 SmallVector<unsigned, 2> ForbidRegs;
579 // If MI's defs have a special allocation requirement, don't allow
580 // any def registers to be changed. Also assume all registers
581 // defined in a call must not be changed (ABI).
582 if (MI->isCall() || MI->hasExtraDefRegAllocReq() ||
583 TII->isPredicated(MI))
584 // If this instruction's defs have special allocation requirement, don't
585 // break this anti-dependency.
587 else if (AntiDepReg) {
588 // If this instruction has a use of AntiDepReg, breaking it
589 // is invalid. If the instruction defines other registers,
590 // save a list of them so that we don't pick a new register
591 // that overlaps any of them.
592 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
593 MachineOperand &MO = MI->getOperand(i);
594 if (!MO.isReg()) continue;
595 unsigned Reg = MO.getReg();
596 if (Reg == 0) continue;
597 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) {
601 if (MO.isDef() && Reg != AntiDepReg)
602 ForbidRegs.push_back(Reg);
606 // Determine AntiDepReg's register class, if it is live and is
607 // consistently used within a single class.
608 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0;
609 assert((AntiDepReg == 0 || RC != NULL) &&
610 "Register should be live if it's causing an anti-dependence!");
611 if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
614 // Look for a suitable register to use to break the anti-depenence.
616 // TODO: Instead of picking the first free register, consider which might
618 if (AntiDepReg != 0) {
619 std::pair<std::multimap<unsigned, MachineOperand *>::iterator,
620 std::multimap<unsigned, MachineOperand *>::iterator>
621 Range = RegRefs.equal_range(AntiDepReg);
622 if (unsigned NewReg = findSuitableFreeRegister(Range.first, Range.second,
624 LastNewReg[AntiDepReg],
626 DEBUG(dbgs() << "Breaking anti-dependence edge on "
627 << TRI->getName(AntiDepReg)
628 << " with " << RegRefs.count(AntiDepReg) << " references"
629 << " using " << TRI->getName(NewReg) << "!\n");
631 // Update the references to the old register to refer to the new
633 for (std::multimap<unsigned, MachineOperand *>::iterator
634 Q = Range.first, QE = Range.second; Q != QE; ++Q) {
635 Q->second->setReg(NewReg);
636 // If the SU for the instruction being updated has debug information
637 // related to the anti-dependency register, make sure to update that
639 const SUnit *SU = MISUnitMap[Q->second->getParent()];
641 for (DbgValueVector::iterator DVI = DbgValues.begin(),
642 DVE = DbgValues.end(); DVI != DVE; ++DVI)
643 if (DVI->second == Q->second->getParent())
644 UpdateDbgValue(DVI->first, AntiDepReg, NewReg);
647 // We just went back in time and modified history; the
648 // liveness information for the anti-dependence reg is now
649 // inconsistent. Set the state as if it were dead.
650 Classes[NewReg] = Classes[AntiDepReg];
651 DefIndices[NewReg] = DefIndices[AntiDepReg];
652 KillIndices[NewReg] = KillIndices[AntiDepReg];
653 assert(((KillIndices[NewReg] == ~0u) !=
654 (DefIndices[NewReg] == ~0u)) &&
655 "Kill and Def maps aren't consistent for NewReg!");
657 Classes[AntiDepReg] = 0;
658 DefIndices[AntiDepReg] = KillIndices[AntiDepReg];
659 KillIndices[AntiDepReg] = ~0u;
660 assert(((KillIndices[AntiDepReg] == ~0u) !=
661 (DefIndices[AntiDepReg] == ~0u)) &&
662 "Kill and Def maps aren't consistent for AntiDepReg!");
664 RegRefs.erase(AntiDepReg);
665 LastNewReg[AntiDepReg] = NewReg;
670 ScanInstruction(MI, Count);