1 //=- llvm/CodeGen/DFAPacketizer.cpp - DFA Packetizer for VLIW -*- C++ -*-=====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This class implements a deterministic finite automaton (DFA) based
10 // packetizing mechanism for VLIW architectures. It provides APIs to
11 // determine whether there exists a legal mapping of instructions to
12 // functional unit assignments in a packet. The DFA is auto-generated from
13 // the target's Schedule.td file.
15 // A DFA consists of 3 major elements: states, inputs, and transitions. For
16 // the packetizing mechanism, the input is the set of instruction classes for
17 // a target. The state models all possible combinations of functional unit
18 // consumption for a given set of instructions in a packet. A transition
19 // models the addition of an instruction to a packet. In the DFA constructed
20 // by this class, if an instruction can be added to a packet, then a valid
21 // transition exists from the corresponding state. Invalid transitions
22 // indicate that the instruction cannot be added to the current packet.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/CodeGen/DFAPacketizer.h"
27 #include "llvm/CodeGen/MachineInstr.h"
28 #include "llvm/CodeGen/MachineInstrBundle.h"
29 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
30 #include "llvm/MC/MCInstrItineraries.h"
31 #include "llvm/Target/TargetInstrInfo.h"
34 DFAPacketizer::DFAPacketizer(const InstrItineraryData *I,
35 const DFAStateInput (*SIT)[2],
37 InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
38 DFAStateEntryTable(SET) {
39 // Make sure DFA types are large enough for the number of terms & resources.
40 assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 * sizeof(DFAInput))
41 && "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAInput");
42 assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 * sizeof(DFAStateInput))
43 && "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAStateInput");
48 // ReadTable - Read the DFA transition table and update CachedTable.
50 // Format of the transition tables:
51 // DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
53 // DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable
56 void DFAPacketizer::ReadTable(unsigned int state) {
57 unsigned ThisState = DFAStateEntryTable[state];
58 unsigned NextStateInTable = DFAStateEntryTable[state+1];
59 // Early exit in case CachedTable has already contains this
60 // state's transitions.
61 if (CachedTable.count(UnsignPair(state,
62 DFAStateInputTable[ThisState][0])))
65 for (unsigned i = ThisState; i < NextStateInTable; i++)
66 CachedTable[UnsignPair(state, DFAStateInputTable[i][0])] =
67 DFAStateInputTable[i][1];
71 // getInsnInput - Return the DFAInput for an instruction class.
73 DFAInput DFAPacketizer::getInsnInput(unsigned InsnClass) {
74 // note: this logic must match that in DFAPacketizer.h for input vectors
75 DFAInput InsnInput = 0;
77 for (const InstrStage *IS = InstrItins->beginStage(InsnClass),
78 *IE = InstrItins->endStage(InsnClass); IS != IE; ++IS, ++i) {
79 unsigned FuncUnits = IS->getUnits();
80 InsnInput <<= DFA_MAX_RESOURCES; // Shift over any previous AND'ed terms.
81 InsnInput |= FuncUnits;
82 assert ((i < DFA_MAX_RESTERMS) && "Exceeded maximum number of DFA inputs");
88 // canReserveResources - Check if the resources occupied by a MCInstrDesc
89 // are available in the current state.
90 bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) {
91 unsigned InsnClass = MID->getSchedClass();
92 DFAInput InsnInput = getInsnInput(InsnClass);
93 UnsignPair StateTrans = UnsignPair(CurrentState, InsnInput);
94 ReadTable(CurrentState);
95 return (CachedTable.count(StateTrans) != 0);
98 // reserveResources - Reserve the resources occupied by a MCInstrDesc and
99 // change the current state to reflect that change.
100 void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) {
101 unsigned InsnClass = MID->getSchedClass();
102 DFAInput InsnInput = getInsnInput(InsnClass);
103 UnsignPair StateTrans = UnsignPair(CurrentState, InsnInput);
104 ReadTable(CurrentState);
105 assert(CachedTable.count(StateTrans) != 0);
106 CurrentState = CachedTable[StateTrans];
110 // canReserveResources - Check if the resources occupied by a machine
111 // instruction are available in the current state.
112 bool DFAPacketizer::canReserveResources(llvm::MachineInstr *MI) {
113 const llvm::MCInstrDesc &MID = MI->getDesc();
114 return canReserveResources(&MID);
117 // reserveResources - Reserve the resources occupied by a machine
118 // instruction and change the current state to reflect that change.
119 void DFAPacketizer::reserveResources(llvm::MachineInstr *MI) {
120 const llvm::MCInstrDesc &MID = MI->getDesc();
121 reserveResources(&MID);
125 // DefaultVLIWScheduler - This class extends ScheduleDAGInstrs and overrides
126 // Schedule method to build the dependence graph.
127 class DefaultVLIWScheduler : public ScheduleDAGInstrs {
129 DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI);
130 // Schedule - Actual scheduling work.
131 void schedule() override;
135 DefaultVLIWScheduler::DefaultVLIWScheduler(MachineFunction &MF,
136 MachineLoopInfo &MLI)
137 : ScheduleDAGInstrs(MF, &MLI) {
138 CanHandleTerminators = true;
141 void DefaultVLIWScheduler::schedule() {
142 // Build the scheduling graph.
143 buildSchedGraph(nullptr);
146 // VLIWPacketizerList Ctor
147 VLIWPacketizerList::VLIWPacketizerList(MachineFunction &MF,
148 MachineLoopInfo &MLI)
150 TII = MF.getSubtarget().getInstrInfo();
151 ResourceTracker = TII->CreateTargetScheduleState(MF.getSubtarget());
152 VLIWScheduler = new DefaultVLIWScheduler(MF, MLI);
155 // VLIWPacketizerList Dtor
156 VLIWPacketizerList::~VLIWPacketizerList() {
158 delete VLIWScheduler;
161 delete ResourceTracker;
164 // endPacket - End the current packet, bundle packet instructions and reset
166 void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
168 if (CurrentPacketMIs.size() > 1) {
169 MachineInstr *MIFirst = CurrentPacketMIs.front();
170 finalizeBundle(*MBB, MIFirst->getIterator(), MI->getIterator());
172 CurrentPacketMIs.clear();
173 ResourceTracker->clearResources();
176 // PacketizeMIs - Bundle machine instructions into packets.
177 void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
178 MachineBasicBlock::iterator BeginItr,
179 MachineBasicBlock::iterator EndItr) {
180 assert(VLIWScheduler && "VLIW Scheduler is not initialized!");
181 VLIWScheduler->startBlock(MBB);
182 VLIWScheduler->enterRegion(MBB, BeginItr, EndItr,
183 std::distance(BeginItr, EndItr));
184 VLIWScheduler->schedule();
186 // Generate MI -> SU map.
188 for (unsigned i = 0, e = VLIWScheduler->SUnits.size(); i != e; ++i) {
189 SUnit *SU = &VLIWScheduler->SUnits[i];
190 MIToSUnit[SU->getInstr()] = SU;
193 // The main packetizer loop.
194 for (; BeginItr != EndItr; ++BeginItr) {
195 MachineInstr *MI = BeginItr;
197 this->initPacketizerState();
199 // End the current packet if needed.
200 if (this->isSoloInstruction(MI)) {
205 // Ignore pseudo instructions.
206 if (this->ignorePseudoInstruction(MI, MBB))
209 SUnit *SUI = MIToSUnit[MI];
210 assert(SUI && "Missing SUnit Info!");
212 // Ask DFA if machine resource is available for MI.
213 bool ResourceAvail = ResourceTracker->canReserveResources(MI);
215 // Dependency check for MI with instructions in CurrentPacketMIs.
216 for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
217 VE = CurrentPacketMIs.end(); VI != VE; ++VI) {
218 MachineInstr *MJ = *VI;
219 SUnit *SUJ = MIToSUnit[MJ];
220 assert(SUJ && "Missing SUnit Info!");
222 // Is it legal to packetize SUI and SUJ together.
223 if (!this->isLegalToPacketizeTogether(SUI, SUJ)) {
224 // Allow packetization if dependency can be pruned.
225 if (!this->isLegalToPruneDependencies(SUI, SUJ)) {
226 // End the packet if dependency cannot be pruned.
229 } // !isLegalToPruneDependencies.
230 } // !isLegalToPacketizeTogether.
231 } // For all instructions in CurrentPacketMIs.
233 // End the packet if resource is not available.
237 // Add MI to the current packet.
238 BeginItr = this->addToPacket(MI);
239 } // For all instructions in BB.
241 // End any packet left behind.
242 endPacket(MBB, EndItr);
243 VLIWScheduler->exitRegion();
244 VLIWScheduler->finishBlock();