1 //=- llvm/CodeGen/DFAPacketizer.cpp - DFA Packetizer for VLIW -*- C++ -*-=====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This class implements a deterministic finite automaton (DFA) based
10 // packetizing mechanism for VLIW architectures. It provides APIs to
11 // determine whether there exists a legal mapping of instructions to
12 // functional unit assignments in a packet. The DFA is auto-generated from
13 // the target's Schedule.td file.
15 // A DFA consists of 3 major elements: states, inputs, and transitions. For
16 // the packetizing mechanism, the input is the set of instruction classes for
17 // a target. The state models all possible combinations of functional unit
18 // consumption for a given set of instructions in a packet. A transition
19 // models the addition of an instruction to a packet. In the DFA constructed
20 // by this class, if an instruction can be added to a packet, then a valid
21 // transition exists from the corresponding state. Invalid transitions
22 // indicate that the instruction cannot be added to the current packet.
24 //===----------------------------------------------------------------------===//
26 #include "ScheduleDAGInstrs.h"
27 #include "llvm/CodeGen/DFAPacketizer.h"
28 #include "llvm/CodeGen/MachineInstr.h"
29 #include "llvm/CodeGen/MachineInstrBundle.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/MC/MCInstrItineraries.h"
34 DFAPacketizer::DFAPacketizer(const InstrItineraryData *I, const int (*SIT)[2],
36 InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
37 DFAStateEntryTable(SET) {}
41 // ReadTable - Read the DFA transition table and update CachedTable.
43 // Format of the transition tables:
44 // DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
46 // DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable
49 void DFAPacketizer::ReadTable(unsigned int state) {
50 unsigned ThisState = DFAStateEntryTable[state];
51 unsigned NextStateInTable = DFAStateEntryTable[state+1];
52 // Early exit in case CachedTable has already contains this
53 // state's transitions.
54 if (CachedTable.count(UnsignPair(state,
55 DFAStateInputTable[ThisState][0])))
58 for (unsigned i = ThisState; i < NextStateInTable; i++)
59 CachedTable[UnsignPair(state, DFAStateInputTable[i][0])] =
60 DFAStateInputTable[i][1];
64 // canReserveResources - Check if the resources occupied by a MCInstrDesc
65 // are available in the current state.
66 bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) {
67 unsigned InsnClass = MID->getSchedClass();
68 const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
69 unsigned FuncUnits = IS->getUnits();
70 UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits);
71 ReadTable(CurrentState);
72 return (CachedTable.count(StateTrans) != 0);
76 // reserveResources - Reserve the resources occupied by a MCInstrDesc and
77 // change the current state to reflect that change.
78 void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) {
79 unsigned InsnClass = MID->getSchedClass();
80 const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
81 unsigned FuncUnits = IS->getUnits();
82 UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits);
83 ReadTable(CurrentState);
84 assert(CachedTable.count(StateTrans) != 0);
85 CurrentState = CachedTable[StateTrans];
89 // canReserveResources - Check if the resources occupied by a machine
90 // instruction are available in the current state.
91 bool DFAPacketizer::canReserveResources(llvm::MachineInstr *MI) {
92 const llvm::MCInstrDesc &MID = MI->getDesc();
93 return canReserveResources(&MID);
96 // reserveResources - Reserve the resources occupied by a machine
97 // instruction and change the current state to reflect that change.
98 void DFAPacketizer::reserveResources(llvm::MachineInstr *MI) {
99 const llvm::MCInstrDesc &MID = MI->getDesc();
100 reserveResources(&MID);
104 // DefaultVLIWScheduler - This class extends ScheduleDAGInstrs and overrides
105 // Schedule method to build the dependence graph.
107 // ScheduleDAGInstrs has LLVM_LIBRARY_VISIBILITY so we have to reference it as
108 // an opaque pointer in VLIWPacketizerList.
109 class DefaultVLIWScheduler : public ScheduleDAGInstrs {
111 DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI,
112 MachineDominatorTree &MDT, bool IsPostRA);
113 // Schedule - Actual scheduling work.
116 } // end anonymous namespace
118 DefaultVLIWScheduler::DefaultVLIWScheduler(
119 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
121 ScheduleDAGInstrs(MF, MLI, MDT, IsPostRA) {
124 void DefaultVLIWScheduler::Schedule() {
125 // Build the scheduling graph.
129 // VLIWPacketizerList Ctor
130 VLIWPacketizerList::VLIWPacketizerList(
131 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
132 bool IsPostRA) : TM(MF.getTarget()), MF(MF) {
133 TII = TM.getInstrInfo();
134 ResourceTracker = TII->CreateTargetScheduleState(&TM, 0);
135 SchedulerImpl = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA);
138 // VLIWPacketizerList Dtor
139 VLIWPacketizerList::~VLIWPacketizerList() {
140 delete (DefaultVLIWScheduler *)SchedulerImpl;
141 delete ResourceTracker;
144 // ignorePseudoInstruction - ignore pseudo instructions.
145 bool VLIWPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
146 MachineBasicBlock *MBB) {
147 if (MI->isDebugValue())
150 if (TII->isSchedulingBoundary(MI, MBB, MF))
156 // isSoloInstruction - return true if instruction I must end previous
158 bool VLIWPacketizerList::isSoloInstruction(MachineInstr *I) {
159 if (I->isInlineAsm())
165 // addToPacket - Add I to the current packet and reserve resource.
166 void VLIWPacketizerList::addToPacket(MachineInstr *MI) {
167 CurrentPacketMIs.push_back(MI);
168 ResourceTracker->reserveResources(MI);
171 // endPacket - End the current packet, bundle packet instructions and reset
173 void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
175 if (CurrentPacketMIs.size() > 1) {
176 MachineInstr *MIFirst = CurrentPacketMIs.front();
177 finalizeBundle(*MBB, MIFirst, I);
179 CurrentPacketMIs.clear();
180 ResourceTracker->clearResources();
183 // PacketizeMIs - Bundle machine instructions into packets.
184 void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
185 MachineBasicBlock::iterator BeginItr,
186 MachineBasicBlock::iterator EndItr) {
187 DefaultVLIWScheduler *Scheduler = (DefaultVLIWScheduler *)SchedulerImpl;
188 Scheduler->Run(MBB, BeginItr, EndItr, MBB->size());
190 // Remember scheduling units.
191 SUnits = Scheduler->SUnits;
193 // Generate MI -> SU map.
194 std::map <MachineInstr*, SUnit*> MIToSUnit;
195 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
196 SUnit *SU = &SUnits[i];
197 MIToSUnit[SU->getInstr()] = SU;
200 // The main packetizer loop.
201 for (; BeginItr != EndItr; ++BeginItr) {
202 MachineInstr *MI = BeginItr;
204 // Ignore pseudo instructions.
205 if (ignorePseudoInstruction(MI, MBB))
208 // End the current packet if needed.
209 if (isSoloInstruction(MI)) {
214 SUnit *SUI = MIToSUnit[MI];
215 assert(SUI && "Missing SUnit Info!");
217 // Ask DFA if machine resource is available for MI.
218 bool ResourceAvail = ResourceTracker->canReserveResources(MI);
220 // Dependency check for MI with instructions in CurrentPacketMIs.
221 for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
222 VE = CurrentPacketMIs.end(); VI != VE; ++VI) {
223 MachineInstr *MJ = *VI;
224 SUnit *SUJ = MIToSUnit[MJ];
225 assert(SUJ && "Missing SUnit Info!");
227 // Is it legal to packetize SUI and SUJ together.
228 if (!isLegalToPacketizeTogether(SUI, SUJ)) {
229 // Allow packetization if dependency can be pruned.
230 if (!isLegalToPruneDependencies(SUI, SUJ)) {
231 // End the packet if dependency cannot be pruned.
234 } // !isLegalToPruneDependencies.
235 } // !isLegalToPacketizeTogether.
236 } // For all instructions in CurrentPacketMIs.
238 // End the packet if resource is not available.
242 // Add MI to the current packet.
244 } // For all instructions in BB.
246 // End any packet left behind.
247 endPacket(MBB, EndItr);