1 //===- DeadMachineInstructionElim.cpp - Remove dead machine instructions --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is an extremely simple MachineInstr-level dead-code-elimination pass.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "codegen-dce"
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/Pass.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/ADT/Statistic.h"
26 STATISTIC(NumDeletes, "Number of dead instructions deleted");
29 class DeadMachineInstructionElim : public MachineFunctionPass {
30 virtual bool runOnMachineFunction(MachineFunction &MF);
32 const TargetRegisterInfo *TRI;
33 const MachineRegisterInfo *MRI;
34 const TargetInstrInfo *TII;
35 BitVector LivePhysRegs;
38 static char ID; // Pass identification, replacement for typeid
39 DeadMachineInstructionElim() : MachineFunctionPass(ID) {}
42 bool isDead(const MachineInstr *MI) const;
45 char DeadMachineInstructionElim::ID = 0;
47 INITIALIZE_PASS(DeadMachineInstructionElim, "dead-mi-elimination",
48 "Remove dead machine instructions", false, false);
50 FunctionPass *llvm::createDeadMachineInstructionElimPass() {
51 return new DeadMachineInstructionElim();
54 bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
55 // Don't delete instructions with side effects.
56 bool SawStore = false;
57 if (!MI->isSafeToMove(TII, 0, SawStore) && !MI->isPHI())
60 // Examine each operand.
61 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
62 const MachineOperand &MO = MI->getOperand(i);
63 if (MO.isReg() && MO.isDef()) {
64 unsigned Reg = MO.getReg();
65 if (TargetRegisterInfo::isPhysicalRegister(Reg) ?
66 LivePhysRegs[Reg] : !MRI->use_nodbg_empty(Reg)) {
67 // This def has a non-debug use. Don't delete the instruction!
73 // If there are no defs with uses, the instruction is dead.
77 bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
78 bool AnyChanges = false;
79 MRI = &MF.getRegInfo();
80 TRI = MF.getTarget().getRegisterInfo();
81 TII = MF.getTarget().getInstrInfo();
83 // Compute a bitvector to represent all non-allocatable physregs.
84 BitVector NonAllocatableRegs = TRI->getAllocatableSet(MF);
85 NonAllocatableRegs.flip();
87 // Loop over all instructions in all blocks, from bottom to top, so that it's
88 // more likely that chains of dependent but ultimately dead instructions will
90 for (MachineFunction::reverse_iterator I = MF.rbegin(), E = MF.rend();
92 MachineBasicBlock *MBB = &*I;
94 // Start out assuming that all non-allocatable registers are live
96 LivePhysRegs = NonAllocatableRegs;
98 // Also add any explicit live-out physregs for this block.
99 if (!MBB->empty() && MBB->back().getDesc().isReturn())
100 for (MachineRegisterInfo::liveout_iterator LOI = MRI->liveout_begin(),
101 LOE = MRI->liveout_end(); LOI != LOE; ++LOI) {
103 if (TargetRegisterInfo::isPhysicalRegister(Reg))
104 LivePhysRegs.set(Reg);
107 // Now scan the instructions and delete dead ones, tracking physreg
108 // liveness as we go.
109 for (MachineBasicBlock::reverse_iterator MII = MBB->rbegin(),
110 MIE = MBB->rend(); MII != MIE; ) {
111 MachineInstr *MI = &*MII;
113 // If the instruction is dead, delete it!
115 DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI);
116 // It is possible that some DBG_VALUE instructions refer to this
117 // instruction. Examine each def operand for such references;
118 // if found, mark the DBG_VALUE as undef (but don't delete it).
119 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
120 const MachineOperand &MO = MI->getOperand(i);
121 if (!MO.isReg() || !MO.isDef())
123 unsigned Reg = MO.getReg();
124 if (!TargetRegisterInfo::isVirtualRegister(Reg))
126 MachineRegisterInfo::use_iterator nextI;
127 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
128 E = MRI->use_end(); I!=E; I=nextI) {
129 nextI = llvm::next(I); // I is invalidated by the setReg
130 MachineOperand& Use = I.getOperand();
131 MachineInstr *UseMI = Use.getParent();
134 assert(Use.isDebug());
135 UseMI->getOperand(0).setReg(0U);
139 MI->eraseFromParent();
142 // MII is now pointing to the next instruction to process,
143 // so don't increment it.
147 // Record the physreg defs.
148 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
149 const MachineOperand &MO = MI->getOperand(i);
150 if (MO.isReg() && MO.isDef()) {
151 unsigned Reg = MO.getReg();
152 if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
153 LivePhysRegs.reset(Reg);
154 // Check the subreg set, not the alias set, because a def
155 // of a super-register may still be partially live after
157 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
159 LivePhysRegs.reset(*SubRegs);
163 // Record the physreg uses, after the defs, in case a physreg is
164 // both defined and used in the same instruction.
165 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
166 const MachineOperand &MO = MI->getOperand(i);
167 if (MO.isReg() && MO.isUse()) {
168 unsigned Reg = MO.getReg();
169 if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
170 LivePhysRegs.set(Reg);
171 for (const unsigned *AliasSet = TRI->getAliasSet(Reg);
172 *AliasSet; ++AliasSet)
173 LivePhysRegs.set(*AliasSet);
178 // We didn't delete the current instruction, so increment MII to
184 LivePhysRegs.clear();