1 //===- ExecutionDepsFix.cpp - Fix execution dependecy issues ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the execution dependency fix pass.
12 // Some X86 SSE instructions like mov, and, or, xor are available in different
13 // variants for different operand types. These variant instructions are
14 // equivalent, but on Nehalem and newer cpus there is extra latency
15 // transferring data between integer and floating point domains. ARM cores
16 // have similar issues when they are configured with both VFP and NEON
19 // This pass changes the variant instructions to minimize domain crossings.
21 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "execution-fix"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/ADT/DepthFirstIterator.h"
30 #include "llvm/Support/Allocator.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/raw_ostream.h"
35 /// A DomainValue is a bit like LiveIntervals' ValNo, but it also keeps track
36 /// of execution domains.
38 /// An open DomainValue represents a set of instructions that can still switch
39 /// execution domain. Multiple registers may refer to the same open
40 /// DomainValue - they will eventually be collapsed to the same execution
43 /// A collapsed DomainValue represents a single register that has been forced
44 /// into one of more execution domains. There is a separate collapsed
45 /// DomainValue for each register, but it may contain multiple execution
46 /// domains. A register value is initially created in a single execution
47 /// domain, but if we were forced to pay the penalty of a domain crossing, we
48 /// keep track of the fact the the register is now available in multiple
52 // Basic reference counting.
55 // Bitmask of available domains. For an open DomainValue, it is the still
56 // possible domains for collapsing. For a collapsed DomainValue it is the
57 // domains where the register is available for free.
58 unsigned AvailableDomains;
60 // Position of the last defining instruction.
63 // Twiddleable instructions using or defining these registers.
64 SmallVector<MachineInstr*, 8> Instrs;
66 // A collapsed DomainValue has no instructions to twiddle - it simply keeps
67 // track of the domains where the registers are already available.
68 bool isCollapsed() const { return Instrs.empty(); }
70 // Is domain available?
71 bool hasDomain(unsigned domain) const {
72 return AvailableDomains & (1u << domain);
75 // Mark domain as available.
76 void addDomain(unsigned domain) {
77 AvailableDomains |= 1u << domain;
80 // Restrict to a single domain available.
81 void setSingleDomain(unsigned domain) {
82 AvailableDomains = 1u << domain;
85 // Return bitmask of domains that are available and in mask.
86 unsigned getCommonDomains(unsigned mask) const {
87 return AvailableDomains & mask;
90 // First domain available.
91 unsigned getFirstDomain() const {
92 return CountTrailingZeros_32(AvailableDomains);
95 DomainValue() { clear(); }
98 Refs = AvailableDomains = Dist = 0;
105 class ExeDepsFix : public MachineFunctionPass {
107 SpecificBumpPtrAllocator<DomainValue> Allocator;
108 SmallVector<DomainValue*,16> Avail;
110 const TargetRegisterClass *const RC;
112 const TargetInstrInfo *TII;
113 const TargetRegisterInfo *TRI;
114 MachineBasicBlock *MBB;
115 std::vector<int> AliasMap;
116 const unsigned NumRegs;
117 DomainValue **LiveRegs;
118 typedef DenseMap<MachineBasicBlock*,DomainValue**> LiveOutMap;
123 ExeDepsFix(const TargetRegisterClass *rc)
124 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
126 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
127 AU.setPreservesAll();
128 MachineFunctionPass::getAnalysisUsage(AU);
131 virtual bool runOnMachineFunction(MachineFunction &MF);
133 virtual const char *getPassName() const {
134 return "SSE execution domain fixup";
139 int RegIndex(unsigned Reg);
141 // DomainValue allocation.
142 DomainValue *Alloc(int domain = -1);
143 void Recycle(DomainValue*);
145 // LiveRegs manipulations.
146 void SetLiveReg(int rx, DomainValue *DV);
148 void Force(int rx, unsigned domain);
149 void Collapse(DomainValue *dv, unsigned domain);
150 bool Merge(DomainValue *A, DomainValue *B);
152 void enterBasicBlock();
153 void visitGenericInstr(MachineInstr*);
154 void visitSoftInstr(MachineInstr*, unsigned mask);
155 void visitHardInstr(MachineInstr*, unsigned domain);
159 char ExeDepsFix::ID = 0;
161 /// Translate TRI register number to an index into our smaller tables of
162 /// interesting registers. Return -1 for boring registers.
163 int ExeDepsFix::RegIndex(unsigned Reg) {
164 assert(Reg < AliasMap.size() && "Invalid register");
165 return AliasMap[Reg];
168 DomainValue *ExeDepsFix::Alloc(int domain) {
169 DomainValue *dv = Avail.empty() ?
170 new(Allocator.Allocate()) DomainValue :
171 Avail.pop_back_val();
174 dv->addDomain(domain);
178 void ExeDepsFix::Recycle(DomainValue *dv) {
179 assert(dv && "Cannot recycle NULL");
184 /// Set LiveRegs[rx] = dv, updating reference counts.
185 void ExeDepsFix::SetLiveReg(int rx, DomainValue *dv) {
186 assert(unsigned(rx) < NumRegs && "Invalid index");
188 LiveRegs = new DomainValue*[NumRegs];
189 std::fill(LiveRegs, LiveRegs+NumRegs, (DomainValue*)0);
192 if (LiveRegs[rx] == dv)
195 assert(LiveRegs[rx]->Refs && "Bad refcount");
196 if (--LiveRegs[rx]->Refs == 0) Recycle(LiveRegs[rx]);
202 // Kill register rx, recycle or collapse any DomainValue.
203 void ExeDepsFix::Kill(int rx) {
204 assert(unsigned(rx) < NumRegs && "Invalid index");
205 if (!LiveRegs || !LiveRegs[rx]) return;
207 // Before killing the last reference to an open DomainValue, collapse it to
208 // the first available domain.
209 if (LiveRegs[rx]->Refs == 1 && !LiveRegs[rx]->isCollapsed())
210 Collapse(LiveRegs[rx], LiveRegs[rx]->getFirstDomain());
215 /// Force register rx into domain.
216 void ExeDepsFix::Force(int rx, unsigned domain) {
217 assert(unsigned(rx) < NumRegs && "Invalid index");
219 if (LiveRegs && (dv = LiveRegs[rx])) {
220 if (dv->isCollapsed())
221 dv->addDomain(domain);
222 else if (dv->hasDomain(domain))
223 Collapse(dv, domain);
225 // This is an incompatible open DomainValue. Collapse it to whatever and
226 // force the new value into domain. This costs a domain crossing.
227 Collapse(dv, dv->getFirstDomain());
228 assert(LiveRegs[rx] && "Not live after collapse?");
229 LiveRegs[rx]->addDomain(domain);
232 // Set up basic collapsed DomainValue.
233 SetLiveReg(rx, Alloc(domain));
237 /// Collapse open DomainValue into given domain. If there are multiple
238 /// registers using dv, they each get a unique collapsed DomainValue.
239 void ExeDepsFix::Collapse(DomainValue *dv, unsigned domain) {
240 assert(dv->hasDomain(domain) && "Cannot collapse");
242 // Collapse all the instructions.
243 while (!dv->Instrs.empty())
244 TII->setExecutionDomain(dv->Instrs.pop_back_val(), domain);
245 dv->setSingleDomain(domain);
247 // If there are multiple users, give them new, unique DomainValues.
248 if (LiveRegs && dv->Refs > 1)
249 for (unsigned rx = 0; rx != NumRegs; ++rx)
250 if (LiveRegs[rx] == dv)
251 SetLiveReg(rx, Alloc(domain));
254 /// Merge - All instructions and registers in B are moved to A, and B is
256 bool ExeDepsFix::Merge(DomainValue *A, DomainValue *B) {
257 assert(!A->isCollapsed() && "Cannot merge into collapsed");
258 assert(!B->isCollapsed() && "Cannot merge from collapsed");
261 // Restrict to the domains that A and B have in common.
262 unsigned common = A->getCommonDomains(B->AvailableDomains);
265 A->AvailableDomains = common;
266 A->Dist = std::max(A->Dist, B->Dist);
267 A->Instrs.append(B->Instrs.begin(), B->Instrs.end());
268 for (unsigned rx = 0; rx != NumRegs; ++rx)
269 if (LiveRegs[rx] == B)
274 void ExeDepsFix::enterBasicBlock() {
275 // Try to coalesce live-out registers from predecessors.
276 for (MachineBasicBlock::livein_iterator i = MBB->livein_begin(),
277 e = MBB->livein_end(); i != e; ++i) {
278 int rx = RegIndex(*i);
279 if (rx < 0) continue;
280 for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(),
281 pe = MBB->pred_end(); pi != pe; ++pi) {
282 LiveOutMap::const_iterator fi = LiveOuts.find(*pi);
283 if (fi == LiveOuts.end()) continue;
284 DomainValue *pdv = fi->second[rx];
286 if (!LiveRegs || !LiveRegs[rx]) {
291 // We have a live DomainValue from more than one predecessor.
292 if (LiveRegs[rx]->isCollapsed()) {
293 // We are already collapsed, but predecessor is not. Force him.
294 unsigned domain = LiveRegs[rx]->getFirstDomain();
295 if (!pdv->isCollapsed() && pdv->hasDomain(domain))
296 Collapse(pdv, domain);
300 // Currently open, merge in predecessor.
301 if (!pdv->isCollapsed())
302 Merge(LiveRegs[rx], pdv);
304 Force(rx, pdv->getFirstDomain());
309 // A hard instruction only works in one domain. All input registers will be
310 // forced into that domain.
311 void ExeDepsFix::visitHardInstr(MachineInstr *mi, unsigned domain) {
312 // Collapse all uses.
313 for (unsigned i = mi->getDesc().getNumDefs(),
314 e = mi->getDesc().getNumOperands(); i != e; ++i) {
315 MachineOperand &mo = mi->getOperand(i);
316 if (!mo.isReg()) continue;
317 int rx = RegIndex(mo.getReg());
318 if (rx < 0) continue;
322 // Kill all defs and force them.
323 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
324 MachineOperand &mo = mi->getOperand(i);
325 if (!mo.isReg()) continue;
326 int rx = RegIndex(mo.getReg());
327 if (rx < 0) continue;
333 // A soft instruction can be changed to work in other domains given by mask.
334 void ExeDepsFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
335 // Bitmask of available domains for this instruction after taking collapsed
336 // operands into account.
337 unsigned available = mask;
339 // Scan the explicit use operands for incoming domains.
340 SmallVector<int, 4> used;
342 for (unsigned i = mi->getDesc().getNumDefs(),
343 e = mi->getDesc().getNumOperands(); i != e; ++i) {
344 MachineOperand &mo = mi->getOperand(i);
345 if (!mo.isReg()) continue;
346 int rx = RegIndex(mo.getReg());
347 if (rx < 0) continue;
348 if (DomainValue *dv = LiveRegs[rx]) {
349 // Bitmask of domains that dv and available have in common.
350 unsigned common = dv->getCommonDomains(available);
351 // Is it possible to use this collapsed register for free?
352 if (dv->isCollapsed()) {
353 // Restrict available domains to the ones in common with the operand.
354 // If there are no common domains, we must pay the cross-domain
355 // penalty for this operand.
356 if (common) available = common;
358 // Open DomainValue is compatible, save it for merging.
361 // Open DomainValue is not compatible with instruction. It is useless
367 // If the collapsed operands force a single domain, propagate the collapse.
368 if (isPowerOf2_32(available)) {
369 unsigned domain = CountTrailingZeros_32(available);
370 TII->setExecutionDomain(mi, domain);
371 visitHardInstr(mi, domain);
375 // Kill off any remaining uses that don't match available, and build a list of
376 // incoming DomainValues that we want to merge.
377 SmallVector<DomainValue*,4> doms;
378 for (SmallVector<int, 4>::iterator i=used.begin(), e=used.end(); i!=e; ++i) {
380 DomainValue *dv = LiveRegs[rx];
381 // This useless DomainValue could have been missed above.
382 if (!dv->getCommonDomains(available)) {
386 // sorted, uniqued insert.
387 bool inserted = false;
388 for (SmallVector<DomainValue*,4>::iterator i = doms.begin(), e = doms.end();
389 i != e && !inserted; ++i) {
392 else if (dv->Dist < (*i)->Dist) {
401 // doms are now sorted in order of appearance. Try to merge them all, giving
402 // priority to the latest ones.
404 while (!doms.empty()) {
406 dv = doms.pop_back_val();
410 DomainValue *latest = doms.pop_back_val();
411 if (Merge(dv, latest)) continue;
413 // If latest didn't merge, it is useless now. Kill all registers using it.
414 for (SmallVector<int,4>::iterator i=used.begin(), e=used.end(); i != e; ++i)
415 if (LiveRegs[*i] == latest)
419 // dv is the DomainValue we are going to use for this instruction.
423 dv->AvailableDomains = available;
424 dv->Instrs.push_back(mi);
426 // Finally set all defs and non-collapsed uses to dv.
427 for (unsigned i = 0, e = mi->getDesc().getNumOperands(); i != e; ++i) {
428 MachineOperand &mo = mi->getOperand(i);
429 if (!mo.isReg()) continue;
430 int rx = RegIndex(mo.getReg());
431 if (rx < 0) continue;
432 if (!LiveRegs || !LiveRegs[rx] || (mo.isDef() && LiveRegs[rx]!=dv)) {
439 void ExeDepsFix::visitGenericInstr(MachineInstr *mi) {
440 // Process explicit defs, kill any relevant registers redefined.
441 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
442 MachineOperand &mo = mi->getOperand(i);
443 if (!mo.isReg()) continue;
444 int rx = RegIndex(mo.getReg());
445 if (rx < 0) continue;
450 bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) {
452 TII = MF->getTarget().getInstrInfo();
453 TRI = MF->getTarget().getRegisterInfo();
457 assert(NumRegs == RC->getNumRegs() && "Bad regclass");
459 // If no relevant registers are used in the function, we can skip it
461 bool anyregs = false;
462 for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end();
464 if (MF->getRegInfo().isPhysRegUsed(*I)) {
468 if (!anyregs) return false;
470 // Initialize the AliasMap on the first use.
471 if (AliasMap.empty()) {
472 // Given a PhysReg, AliasMap[PhysReg] is either the relevant index into RC,
474 AliasMap.resize(TRI->getNumRegs(), -1);
475 for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i)
476 for (const unsigned *AI = TRI->getOverlaps(RC->getRegister(i)); *AI; ++AI)
480 MachineBasicBlock *Entry = MF->begin();
481 SmallPtrSet<MachineBasicBlock*, 16> Visited;
482 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 16> >
483 DFI = df_ext_begin(Entry, Visited), DFE = df_ext_end(Entry, Visited);
487 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
489 MachineInstr *mi = I;
490 if (mi->isDebugValue()) continue;
492 std::pair<uint16_t, uint16_t> domp = TII->getExecutionDomain(mi);
495 visitSoftInstr(mi, domp.second);
497 visitHardInstr(mi, domp.first);
499 visitGenericInstr(mi);
502 // Save live registers at end of MBB - used by enterBasicBlock().
504 LiveOuts.insert(std::make_pair(MBB, LiveRegs));
508 // Clear the LiveOuts vectors. Should we also collapse any remaining
510 for (LiveOutMap::const_iterator i = LiveOuts.begin(), e = LiveOuts.end();
515 Allocator.DestroyAll();
521 llvm::createExecutionDependencyFixPass(const TargetRegisterClass *RC) {
522 return new ExeDepsFix(RC);