1 //===- ExecutionDepsFix.cpp - Fix execution dependecy issues ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the execution dependency fix pass.
12 // Some X86 SSE instructions like mov, and, or, xor are available in different
13 // variants for different operand types. These variant instructions are
14 // equivalent, but on Nehalem and newer cpus there is extra latency
15 // transferring data between integer and floating point domains. ARM cores
16 // have similar issues when they are configured with both VFP and NEON
19 // This pass changes the variant instructions to minimize domain crossings.
21 //===----------------------------------------------------------------------===//
23 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/ADT/PostOrderIterator.h"
25 #include "llvm/CodeGen/LivePhysRegs.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/Support/Allocator.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetSubtargetInfo.h"
36 #define DEBUG_TYPE "execution-fix"
38 /// A DomainValue is a bit like LiveIntervals' ValNo, but it also keeps track
39 /// of execution domains.
41 /// An open DomainValue represents a set of instructions that can still switch
42 /// execution domain. Multiple registers may refer to the same open
43 /// DomainValue - they will eventually be collapsed to the same execution
46 /// A collapsed DomainValue represents a single register that has been forced
47 /// into one of more execution domains. There is a separate collapsed
48 /// DomainValue for each register, but it may contain multiple execution
49 /// domains. A register value is initially created in a single execution
50 /// domain, but if we were forced to pay the penalty of a domain crossing, we
51 /// keep track of the fact that the register is now available in multiple
55 // Basic reference counting.
58 // Bitmask of available domains. For an open DomainValue, it is the still
59 // possible domains for collapsing. For a collapsed DomainValue it is the
60 // domains where the register is available for free.
61 unsigned AvailableDomains;
63 // Pointer to the next DomainValue in a chain. When two DomainValues are
64 // merged, Victim.Next is set to point to Victor, so old DomainValue
65 // references can be updated by following the chain.
68 // Twiddleable instructions using or defining these registers.
69 SmallVector<MachineInstr*, 8> Instrs;
71 // A collapsed DomainValue has no instructions to twiddle - it simply keeps
72 // track of the domains where the registers are already available.
73 bool isCollapsed() const { return Instrs.empty(); }
75 // Is domain available?
76 bool hasDomain(unsigned domain) const {
78 static_cast<unsigned>(std::numeric_limits<unsigned>::digits) &&
79 "undefined behavior");
80 return AvailableDomains & (1u << domain);
83 // Mark domain as available.
84 void addDomain(unsigned domain) {
85 AvailableDomains |= 1u << domain;
88 // Restrict to a single domain available.
89 void setSingleDomain(unsigned domain) {
90 AvailableDomains = 1u << domain;
93 // Return bitmask of domains that are available and in mask.
94 unsigned getCommonDomains(unsigned mask) const {
95 return AvailableDomains & mask;
98 // First domain available.
99 unsigned getFirstDomain() const {
100 return countTrailingZeros(AvailableDomains);
103 DomainValue() : Refs(0) { clear(); }
105 // Clear this DomainValue and point to next which has all its data.
107 AvailableDomains = 0;
115 /// LiveReg - Information about a live register.
117 /// Value currently in this register, or NULL when no value is being tracked.
118 /// This counts as a DomainValue reference.
121 /// Instruction that defined this register, relative to the beginning of the
122 /// current basic block. When a LiveReg is used to represent a live-out
123 /// register, this value is relative to the end of the basic block, so it
124 /// will be a negative number.
127 } // anonynous namespace
130 class ExeDepsFix : public MachineFunctionPass {
132 SpecificBumpPtrAllocator<DomainValue> Allocator;
133 SmallVector<DomainValue*,16> Avail;
135 const TargetRegisterClass *const RC;
137 const TargetInstrInfo *TII;
138 const TargetRegisterInfo *TRI;
139 std::vector<int> AliasMap;
140 const unsigned NumRegs;
142 typedef DenseMap<MachineBasicBlock*, LiveReg*> LiveOutMap;
145 /// List of undefined register reads in this block in forward order.
146 std::vector<std::pair<MachineInstr*, unsigned> > UndefReads;
148 /// Storage for register unit liveness.
149 LivePhysRegs LiveRegSet;
151 /// Current instruction number.
152 /// The first instruction in each basic block is 0.
155 /// True when the current block has a predecessor that hasn't been visited
157 bool SeenUnknownBackEdge;
160 ExeDepsFix(const TargetRegisterClass *rc)
161 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
163 void getAnalysisUsage(AnalysisUsage &AU) const override {
164 AU.setPreservesAll();
165 MachineFunctionPass::getAnalysisUsage(AU);
168 bool runOnMachineFunction(MachineFunction &MF) override;
170 const char *getPassName() const override {
171 return "Execution dependency fix";
176 int regIndex(unsigned Reg);
178 // DomainValue allocation.
179 DomainValue *alloc(int domain = -1);
180 DomainValue *retain(DomainValue *DV) {
184 void release(DomainValue*);
185 DomainValue *resolve(DomainValue*&);
187 // LiveRegs manipulations.
188 void setLiveReg(int rx, DomainValue *DV);
190 void force(int rx, unsigned domain);
191 void collapse(DomainValue *dv, unsigned domain);
192 bool merge(DomainValue *A, DomainValue *B);
194 void enterBasicBlock(MachineBasicBlock*);
195 void leaveBasicBlock(MachineBasicBlock*);
196 void visitInstr(MachineInstr*);
197 void processDefs(MachineInstr*, bool Kill);
198 void visitSoftInstr(MachineInstr*, unsigned mask);
199 void visitHardInstr(MachineInstr*, unsigned domain);
200 bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref);
201 void processUndefReads(MachineBasicBlock*);
205 char ExeDepsFix::ID = 0;
207 /// Translate TRI register number to an index into our smaller tables of
208 /// interesting registers. Return -1 for boring registers.
209 int ExeDepsFix::regIndex(unsigned Reg) {
210 assert(Reg < AliasMap.size() && "Invalid register");
211 return AliasMap[Reg];
214 DomainValue *ExeDepsFix::alloc(int domain) {
215 DomainValue *dv = Avail.empty() ?
216 new(Allocator.Allocate()) DomainValue :
217 Avail.pop_back_val();
219 dv->addDomain(domain);
220 assert(dv->Refs == 0 && "Reference count wasn't cleared");
221 assert(!dv->Next && "Chained DomainValue shouldn't have been recycled");
225 /// release - Release a reference to DV. When the last reference is released,
226 /// collapse if needed.
227 void ExeDepsFix::release(DomainValue *DV) {
229 assert(DV->Refs && "Bad DomainValue");
233 // There are no more DV references. Collapse any contained instructions.
234 if (DV->AvailableDomains && !DV->isCollapsed())
235 collapse(DV, DV->getFirstDomain());
237 DomainValue *Next = DV->Next;
240 // Also release the next DomainValue in the chain.
245 /// resolve - Follow the chain of dead DomainValues until a live DomainValue is
246 /// reached. Update the referenced pointer when necessary.
247 DomainValue *ExeDepsFix::resolve(DomainValue *&DVRef) {
248 DomainValue *DV = DVRef;
249 if (!DV || !DV->Next)
252 // DV has a chain. Find the end.
256 // Update DVRef to point to DV.
263 /// Set LiveRegs[rx] = dv, updating reference counts.
264 void ExeDepsFix::setLiveReg(int rx, DomainValue *dv) {
265 assert(unsigned(rx) < NumRegs && "Invalid index");
266 assert(LiveRegs && "Must enter basic block first.");
268 if (LiveRegs[rx].Value == dv)
270 if (LiveRegs[rx].Value)
271 release(LiveRegs[rx].Value);
272 LiveRegs[rx].Value = retain(dv);
275 // Kill register rx, recycle or collapse any DomainValue.
276 void ExeDepsFix::kill(int rx) {
277 assert(unsigned(rx) < NumRegs && "Invalid index");
278 assert(LiveRegs && "Must enter basic block first.");
279 if (!LiveRegs[rx].Value)
282 release(LiveRegs[rx].Value);
283 LiveRegs[rx].Value = nullptr;
286 /// Force register rx into domain.
287 void ExeDepsFix::force(int rx, unsigned domain) {
288 assert(unsigned(rx) < NumRegs && "Invalid index");
289 assert(LiveRegs && "Must enter basic block first.");
290 if (DomainValue *dv = LiveRegs[rx].Value) {
291 if (dv->isCollapsed())
292 dv->addDomain(domain);
293 else if (dv->hasDomain(domain))
294 collapse(dv, domain);
296 // This is an incompatible open DomainValue. Collapse it to whatever and
297 // force the new value into domain. This costs a domain crossing.
298 collapse(dv, dv->getFirstDomain());
299 assert(LiveRegs[rx].Value && "Not live after collapse?");
300 LiveRegs[rx].Value->addDomain(domain);
303 // Set up basic collapsed DomainValue.
304 setLiveReg(rx, alloc(domain));
308 /// Collapse open DomainValue into given domain. If there are multiple
309 /// registers using dv, they each get a unique collapsed DomainValue.
310 void ExeDepsFix::collapse(DomainValue *dv, unsigned domain) {
311 assert(dv->hasDomain(domain) && "Cannot collapse");
313 // Collapse all the instructions.
314 while (!dv->Instrs.empty())
315 TII->setExecutionDomain(dv->Instrs.pop_back_val(), domain);
316 dv->setSingleDomain(domain);
318 // If there are multiple users, give them new, unique DomainValues.
319 if (LiveRegs && dv->Refs > 1)
320 for (unsigned rx = 0; rx != NumRegs; ++rx)
321 if (LiveRegs[rx].Value == dv)
322 setLiveReg(rx, alloc(domain));
325 /// Merge - All instructions and registers in B are moved to A, and B is
327 bool ExeDepsFix::merge(DomainValue *A, DomainValue *B) {
328 assert(!A->isCollapsed() && "Cannot merge into collapsed");
329 assert(!B->isCollapsed() && "Cannot merge from collapsed");
332 // Restrict to the domains that A and B have in common.
333 unsigned common = A->getCommonDomains(B->AvailableDomains);
336 A->AvailableDomains = common;
337 A->Instrs.append(B->Instrs.begin(), B->Instrs.end());
339 // Clear the old DomainValue so we won't try to swizzle instructions twice.
341 // All uses of B are referred to A.
344 for (unsigned rx = 0; rx != NumRegs; ++rx) {
345 assert(LiveRegs && "no space allocated for live registers");
346 if (LiveRegs[rx].Value == B)
352 // enterBasicBlock - Set up LiveRegs by merging predecessor live-out values.
353 void ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) {
354 // Detect back-edges from predecessors we haven't processed yet.
355 SeenUnknownBackEdge = false;
357 // Reset instruction counter in each basic block.
360 // Set up UndefReads to track undefined register reads.
364 // Set up LiveRegs to represent registers entering MBB.
366 LiveRegs = new LiveReg[NumRegs];
368 // Default values are 'nothing happened a long time ago'.
369 for (unsigned rx = 0; rx != NumRegs; ++rx) {
370 LiveRegs[rx].Value = nullptr;
371 LiveRegs[rx].Def = -(1 << 20);
374 // This is the entry block.
375 if (MBB->pred_empty()) {
376 for (MachineBasicBlock::livein_iterator i = MBB->livein_begin(),
377 e = MBB->livein_end(); i != e; ++i) {
378 int rx = regIndex(*i);
381 // Treat function live-ins as if they were defined just before the first
382 // instruction. Usually, function arguments are set up immediately
384 LiveRegs[rx].Def = -1;
386 DEBUG(dbgs() << "BB#" << MBB->getNumber() << ": entry\n");
390 // Try to coalesce live-out registers from predecessors.
391 for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(),
392 pe = MBB->pred_end(); pi != pe; ++pi) {
393 LiveOutMap::const_iterator fi = LiveOuts.find(*pi);
394 if (fi == LiveOuts.end()) {
395 SeenUnknownBackEdge = true;
398 assert(fi->second && "Can't have NULL entries");
400 for (unsigned rx = 0; rx != NumRegs; ++rx) {
401 // Use the most recent predecessor def for each register.
402 LiveRegs[rx].Def = std::max(LiveRegs[rx].Def, fi->second[rx].Def);
404 DomainValue *pdv = resolve(fi->second[rx].Value);
407 if (!LiveRegs[rx].Value) {
412 // We have a live DomainValue from more than one predecessor.
413 if (LiveRegs[rx].Value->isCollapsed()) {
414 // We are already collapsed, but predecessor is not. Force it.
415 unsigned Domain = LiveRegs[rx].Value->getFirstDomain();
416 if (!pdv->isCollapsed() && pdv->hasDomain(Domain))
417 collapse(pdv, Domain);
421 // Currently open, merge in predecessor.
422 if (!pdv->isCollapsed())
423 merge(LiveRegs[rx].Value, pdv);
425 force(rx, pdv->getFirstDomain());
428 DEBUG(dbgs() << "BB#" << MBB->getNumber()
429 << (SeenUnknownBackEdge ? ": incomplete\n" : ": all preds known\n"));
432 void ExeDepsFix::leaveBasicBlock(MachineBasicBlock *MBB) {
433 assert(LiveRegs && "Must enter basic block first.");
434 // Save live registers at end of MBB - used by enterBasicBlock().
435 // Also use LiveOuts as a visited set to detect back-edges.
436 bool First = LiveOuts.insert(std::make_pair(MBB, LiveRegs)).second;
439 // LiveRegs was inserted in LiveOuts. Adjust all defs to be relative to
440 // the end of this block instead of the beginning.
441 for (unsigned i = 0, e = NumRegs; i != e; ++i)
442 LiveRegs[i].Def -= CurInstr;
444 // Insertion failed, this must be the second pass.
445 // Release all the DomainValues instead of keeping them.
446 for (unsigned i = 0, e = NumRegs; i != e; ++i)
447 release(LiveRegs[i].Value);
453 void ExeDepsFix::visitInstr(MachineInstr *MI) {
454 if (MI->isDebugValue())
457 // Update instructions with explicit execution domains.
458 std::pair<uint16_t, uint16_t> DomP = TII->getExecutionDomain(MI);
461 visitSoftInstr(MI, DomP.second);
463 visitHardInstr(MI, DomP.first);
466 // Process defs to track register ages, and kill values clobbered by generic
468 processDefs(MI, !DomP.first);
471 /// \brief Return true to if it makes sense to break dependence on a partial def
473 bool ExeDepsFix::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,
475 int rx = regIndex(MI->getOperand(OpIdx).getReg());
479 unsigned Clearance = CurInstr - LiveRegs[rx].Def;
480 DEBUG(dbgs() << "Clearance: " << Clearance << ", want " << Pref);
482 if (Pref > Clearance) {
483 DEBUG(dbgs() << ": Break dependency.\n");
486 // The current clearance seems OK, but we may be ignoring a def from a
488 if (!SeenUnknownBackEdge || Pref <= unsigned(CurInstr)) {
489 DEBUG(dbgs() << ": OK .\n");
492 // A def from an unprocessed back-edge may make us break this dependency.
493 DEBUG(dbgs() << ": Wait for back-edge to resolve.\n");
497 // Update def-ages for registers defined by MI.
498 // If Kill is set, also kill off DomainValues clobbered by the defs.
500 // Also break dependencies on partial defs and undef uses.
501 void ExeDepsFix::processDefs(MachineInstr *MI, bool Kill) {
502 assert(!MI->isDebugValue() && "Won't process debug values");
504 // Break dependence on undef uses. Do this before updating LiveRegs below.
506 unsigned Pref = TII->getUndefRegClearance(MI, OpNum, TRI);
508 if (shouldBreakDependence(MI, OpNum, Pref))
509 UndefReads.push_back(std::make_pair(MI, OpNum));
511 const MCInstrDesc &MCID = MI->getDesc();
513 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
515 MachineOperand &MO = MI->getOperand(i);
522 int rx = regIndex(MO.getReg());
526 // This instruction explicitly defines rx.
527 DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr
530 // Check clearance before partial register updates.
531 // Call breakDependence before setting LiveRegs[rx].Def.
532 unsigned Pref = TII->getPartialRegUpdateClearance(MI, i, TRI);
533 if (Pref && shouldBreakDependence(MI, i, Pref))
534 TII->breakPartialRegDependency(MI, i, TRI);
536 // How many instructions since rx was last written?
537 LiveRegs[rx].Def = CurInstr;
539 // Kill off domains redefined by generic instructions.
546 /// \break Break false dependencies on undefined register reads.
548 /// Walk the block backward computing precise liveness. This is expensive, so we
549 /// only do it on demand. Note that the occurrence of undefined register reads
550 /// that should be broken is very rare, but when they occur we may have many in
552 void ExeDepsFix::processUndefReads(MachineBasicBlock *MBB) {
553 if (UndefReads.empty())
556 // Collect this block's live out register units.
557 LiveRegSet.init(TRI);
558 LiveRegSet.addLiveOuts(MBB);
560 MachineInstr *UndefMI = UndefReads.back().first;
561 unsigned OpIdx = UndefReads.back().second;
563 for (MachineBasicBlock::reverse_iterator I = MBB->rbegin(), E = MBB->rend();
565 // Update liveness, including the current instruction's defs.
566 LiveRegSet.stepBackward(*I);
568 if (UndefMI == &*I) {
569 if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg()))
570 TII->breakPartialRegDependency(UndefMI, OpIdx, TRI);
572 UndefReads.pop_back();
573 if (UndefReads.empty())
576 UndefMI = UndefReads.back().first;
577 OpIdx = UndefReads.back().second;
582 // A hard instruction only works in one domain. All input registers will be
583 // forced into that domain.
584 void ExeDepsFix::visitHardInstr(MachineInstr *mi, unsigned domain) {
585 // Collapse all uses.
586 for (unsigned i = mi->getDesc().getNumDefs(),
587 e = mi->getDesc().getNumOperands(); i != e; ++i) {
588 MachineOperand &mo = mi->getOperand(i);
589 if (!mo.isReg()) continue;
590 int rx = regIndex(mo.getReg());
591 if (rx < 0) continue;
595 // Kill all defs and force them.
596 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
597 MachineOperand &mo = mi->getOperand(i);
598 if (!mo.isReg()) continue;
599 int rx = regIndex(mo.getReg());
600 if (rx < 0) continue;
606 // A soft instruction can be changed to work in other domains given by mask.
607 void ExeDepsFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
608 // Bitmask of available domains for this instruction after taking collapsed
609 // operands into account.
610 unsigned available = mask;
612 // Scan the explicit use operands for incoming domains.
613 SmallVector<int, 4> used;
615 for (unsigned i = mi->getDesc().getNumDefs(),
616 e = mi->getDesc().getNumOperands(); i != e; ++i) {
617 MachineOperand &mo = mi->getOperand(i);
618 if (!mo.isReg()) continue;
619 int rx = regIndex(mo.getReg());
620 if (rx < 0) continue;
621 if (DomainValue *dv = LiveRegs[rx].Value) {
622 // Bitmask of domains that dv and available have in common.
623 unsigned common = dv->getCommonDomains(available);
624 // Is it possible to use this collapsed register for free?
625 if (dv->isCollapsed()) {
626 // Restrict available domains to the ones in common with the operand.
627 // If there are no common domains, we must pay the cross-domain
628 // penalty for this operand.
629 if (common) available = common;
631 // Open DomainValue is compatible, save it for merging.
634 // Open DomainValue is not compatible with instruction. It is useless
640 // If the collapsed operands force a single domain, propagate the collapse.
641 if (isPowerOf2_32(available)) {
642 unsigned domain = countTrailingZeros(available);
643 TII->setExecutionDomain(mi, domain);
644 visitHardInstr(mi, domain);
648 // Kill off any remaining uses that don't match available, and build a list of
649 // incoming DomainValues that we want to merge.
650 SmallVector<LiveReg, 4> Regs;
651 for (SmallVectorImpl<int>::iterator i=used.begin(), e=used.end(); i!=e; ++i) {
653 assert(LiveRegs && "no space allocated for live registers");
654 const LiveReg &LR = LiveRegs[rx];
655 // This useless DomainValue could have been missed above.
656 if (!LR.Value->getCommonDomains(available)) {
661 bool Inserted = false;
662 for (SmallVectorImpl<LiveReg>::iterator i = Regs.begin(), e = Regs.end();
663 i != e && !Inserted; ++i) {
664 if (LR.Def < i->Def) {
673 // doms are now sorted in order of appearance. Try to merge them all, giving
674 // priority to the latest ones.
675 DomainValue *dv = nullptr;
676 while (!Regs.empty()) {
678 dv = Regs.pop_back_val().Value;
679 // Force the first dv to match the current instruction.
680 dv->AvailableDomains = dv->getCommonDomains(available);
681 assert(dv->AvailableDomains && "Domain should have been filtered");
685 DomainValue *Latest = Regs.pop_back_val().Value;
686 // Skip already merged values.
687 if (Latest == dv || Latest->Next)
689 if (merge(dv, Latest))
692 // If latest didn't merge, it is useless now. Kill all registers using it.
694 assert(LiveRegs && "no space allocated for live registers");
695 if (LiveRegs[i].Value == Latest)
700 // dv is the DomainValue we are going to use for this instruction.
703 dv->AvailableDomains = available;
705 dv->Instrs.push_back(mi);
707 // Finally set all defs and non-collapsed uses to dv. We must iterate through
708 // all the operators, including imp-def ones.
709 for (MachineInstr::mop_iterator ii = mi->operands_begin(),
710 ee = mi->operands_end();
712 MachineOperand &mo = *ii;
713 if (!mo.isReg()) continue;
714 int rx = regIndex(mo.getReg());
715 if (rx < 0) continue;
716 if (!LiveRegs[rx].Value || (mo.isDef() && LiveRegs[rx].Value != dv)) {
723 bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) {
725 TII = MF->getSubtarget().getInstrInfo();
726 TRI = MF->getSubtarget().getRegisterInfo();
728 assert(NumRegs == RC->getNumRegs() && "Bad regclass");
730 DEBUG(dbgs() << "********** FIX EXECUTION DEPENDENCIES: "
731 << TRI->getRegClassName(RC) << " **********\n");
733 // If no relevant registers are used in the function, we can skip it
735 bool anyregs = false;
736 for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end();
738 if (MF->getRegInfo().isPhysRegUsed(*I)) {
742 if (!anyregs) return false;
744 // Initialize the AliasMap on the first use.
745 if (AliasMap.empty()) {
746 // Given a PhysReg, AliasMap[PhysReg] is either the relevant index into RC,
748 AliasMap.resize(TRI->getNumRegs(), -1);
749 for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i)
750 for (MCRegAliasIterator AI(RC->getRegister(i), TRI, true);
755 MachineBasicBlock *Entry = MF->begin();
756 ReversePostOrderTraversal<MachineBasicBlock*> RPOT(Entry);
757 SmallVector<MachineBasicBlock*, 16> Loops;
758 for (ReversePostOrderTraversal<MachineBasicBlock*>::rpo_iterator
759 MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) {
760 MachineBasicBlock *MBB = *MBBI;
761 enterBasicBlock(MBB);
762 if (SeenUnknownBackEdge)
763 Loops.push_back(MBB);
764 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
767 processUndefReads(MBB);
768 leaveBasicBlock(MBB);
771 // Visit all the loop blocks again in order to merge DomainValues from
773 for (unsigned i = 0, e = Loops.size(); i != e; ++i) {
774 MachineBasicBlock *MBB = Loops[i];
775 enterBasicBlock(MBB);
776 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
778 if (!I->isDebugValue())
779 processDefs(I, false);
780 processUndefReads(MBB);
781 leaveBasicBlock(MBB);
784 // Clear the LiveOuts vectors and collapse any remaining DomainValues.
785 for (ReversePostOrderTraversal<MachineBasicBlock*>::rpo_iterator
786 MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) {
787 LiveOutMap::const_iterator FI = LiveOuts.find(*MBBI);
788 if (FI == LiveOuts.end() || !FI->second)
790 for (unsigned i = 0, e = NumRegs; i != e; ++i)
791 if (FI->second[i].Value)
792 release(FI->second[i].Value);
798 Allocator.DestroyAll();
804 llvm::createExecutionDependencyFixPass(const TargetRegisterClass *RC) {
805 return new ExeDepsFix(RC);