1 //===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
11 // instructions after register allocation.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/CodeGen/MachineFunctionPass.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
29 #define DEBUG_TYPE "postrapseudos"
32 struct ExpandPostRA : public MachineFunctionPass {
34 const TargetRegisterInfo *TRI;
35 const TargetInstrInfo *TII;
38 static char ID; // Pass identification, replacement for typeid
39 ExpandPostRA() : MachineFunctionPass(ID) {}
41 void getAnalysisUsage(AnalysisUsage &AU) const override {
43 AU.addPreservedID(MachineLoopInfoID);
44 AU.addPreservedID(MachineDominatorsID);
45 MachineFunctionPass::getAnalysisUsage(AU);
48 /// runOnMachineFunction - pass entry point
49 bool runOnMachineFunction(MachineFunction&) override;
52 bool LowerSubregToReg(MachineInstr *MI);
53 bool LowerCopy(MachineInstr *MI);
55 void TransferImplicitDefs(MachineInstr *MI);
57 } // end anonymous namespace
59 char ExpandPostRA::ID = 0;
60 char &llvm::ExpandPostRAPseudosID = ExpandPostRA::ID;
62 INITIALIZE_PASS(ExpandPostRA, "postrapseudos",
63 "Post-RA pseudo instruction expansion pass", false, false)
65 /// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
66 /// replacement instructions immediately precede it. Copy any implicit-def
67 /// operands from MI to the replacement instruction.
69 ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) {
70 MachineBasicBlock::iterator CopyMI = MI;
73 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
74 MachineOperand &MO = MI->getOperand(i);
75 if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
77 CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
81 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
82 MachineBasicBlock *MBB = MI->getParent();
83 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
84 MI->getOperand(1).isImm() &&
85 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
86 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
88 unsigned DstReg = MI->getOperand(0).getReg();
89 unsigned InsReg = MI->getOperand(2).getReg();
90 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
91 unsigned SubIdx = MI->getOperand(3).getImm();
93 assert(SubIdx != 0 && "Invalid index for insert_subreg");
94 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
96 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
97 "Insert destination must be in a physical register");
98 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
99 "Inserted value must be in a physical register");
101 DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
103 if (MI->allDefsAreDead()) {
104 MI->setDesc(TII->get(TargetOpcode::KILL));
105 DEBUG(dbgs() << "subreg: replaced by: " << *MI);
109 if (DstSubReg == InsReg) {
110 // No need to insert an identity copy instruction.
111 // Watch out for case like this:
112 // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
113 // We must leave %RAX live.
114 if (DstReg != InsReg) {
115 MI->setDesc(TII->get(TargetOpcode::KILL));
116 MI->RemoveOperand(3); // SubIdx
117 MI->RemoveOperand(1); // Imm
118 DEBUG(dbgs() << "subreg: replace by: " << *MI);
121 DEBUG(dbgs() << "subreg: eliminated!");
123 TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
124 MI->getOperand(2).isKill());
126 // Implicitly define DstReg for subsequent uses.
127 MachineBasicBlock::iterator CopyMI = MI;
129 CopyMI->addRegisterDefined(DstReg);
130 DEBUG(dbgs() << "subreg: " << *CopyMI);
133 DEBUG(dbgs() << '\n');
138 bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
140 if (MI->allDefsAreDead()) {
141 DEBUG(dbgs() << "dead copy: " << *MI);
142 MI->setDesc(TII->get(TargetOpcode::KILL));
143 DEBUG(dbgs() << "replaced by: " << *MI);
147 MachineOperand &DstMO = MI->getOperand(0);
148 MachineOperand &SrcMO = MI->getOperand(1);
150 if (SrcMO.getReg() == DstMO.getReg()) {
151 DEBUG(dbgs() << "identity copy: " << *MI);
152 // No need to insert an identity copy instruction, but replace with a KILL
153 // if liveness is changed.
154 if (SrcMO.isUndef() || MI->getNumOperands() > 2) {
155 // We must make sure the super-register gets killed. Replace the
156 // instruction with KILL.
157 MI->setDesc(TII->get(TargetOpcode::KILL));
158 DEBUG(dbgs() << "replaced by: " << *MI);
161 // Vanilla identity copy.
162 MI->eraseFromParent();
166 DEBUG(dbgs() << "real copy: " << *MI);
167 TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
168 DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
170 if (MI->getNumOperands() > 2)
171 TransferImplicitDefs(MI);
173 MachineBasicBlock::iterator dMI = MI;
174 dbgs() << "replaced by: " << *(--dMI);
176 MI->eraseFromParent();
180 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
183 bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {
184 DEBUG(dbgs() << "Machine Function\n"
185 << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
186 << "********** Function: " << MF.getName() << '\n');
187 TRI = MF.getSubtarget().getRegisterInfo();
188 TII = MF.getSubtarget().getInstrInfo();
190 bool MadeChange = false;
192 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
193 mbbi != mbbe; ++mbbi) {
194 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
196 MachineInstr *MI = mi;
197 // Advance iterator here because MI may be erased.
200 // Only expand pseudos.
204 // Give targets a chance to expand even standard pseudos.
205 if (TII->expandPostRAPseudo(MI)) {
210 // Expand standard pseudos.
211 switch (MI->getOpcode()) {
212 case TargetOpcode::SUBREG_TO_REG:
213 MadeChange |= LowerSubregToReg(MI);
215 case TargetOpcode::COPY:
216 MadeChange |= LowerCopy(MI);
218 case TargetOpcode::DBG_VALUE:
220 case TargetOpcode::INSERT_SUBREG:
221 case TargetOpcode::EXTRACT_SUBREG:
222 llvm_unreachable("Sub-register pseudos should have been eliminated.");