1 //===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The inline spiller modifies the machine function directly instead of
11 // inserting spills and restores in VirtRegMap.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
17 #include "LiveRangeEdit.h"
18 #include "VirtRegMap.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/LiveStackAnalysis.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/raw_ostream.h"
34 VerifySpills("verify-spills", cl::desc("Verify after each spill/split"));
37 class InlineSpiller : public Spiller {
38 MachineFunctionPass &pass_;
44 MachineFrameInfo &mfi_;
45 MachineRegisterInfo &mri_;
46 const TargetInstrInfo &tii_;
47 const TargetRegisterInfo &tri_;
48 const BitVector reserved_;
50 // Variables that are valid during spill(), but used by multiple methods.
52 const TargetRegisterClass *rc_;
55 // Values that failed to remat at some point.
56 SmallPtrSet<VNInfo*, 8> usedValues_;
61 InlineSpiller(MachineFunctionPass &pass,
66 lis_(pass.getAnalysis<LiveIntervals>()),
67 lss_(pass.getAnalysis<LiveStacks>()),
68 aa_(&pass.getAnalysis<AliasAnalysis>()),
70 mfi_(*mf.getFrameInfo()),
71 mri_(mf.getRegInfo()),
72 tii_(*mf.getTarget().getInstrInfo()),
73 tri_(*mf.getTarget().getRegisterInfo()),
74 reserved_(tri_.getReservedRegs(mf_)) {}
76 void spill(LiveInterval *li,
77 SmallVectorImpl<LiveInterval*> &newIntervals,
78 const SmallVectorImpl<LiveInterval*> &spillIs);
80 void spill(LiveRangeEdit &);
83 bool reMaterializeFor(MachineBasicBlock::iterator MI);
84 void reMaterializeAll();
86 bool coalesceStackAccess(MachineInstr *MI);
87 bool foldMemoryOperand(MachineBasicBlock::iterator MI,
88 const SmallVectorImpl<unsigned> &Ops,
89 MachineInstr *LoadMI = 0);
90 void insertReload(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
91 void insertSpill(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
96 Spiller *createInlineSpiller(MachineFunctionPass &pass,
100 mf.verify(&pass, "When creating inline spiller");
101 return new InlineSpiller(pass, mf, vrm);
105 /// reMaterializeFor - Attempt to rematerialize edit_->getReg() before MI instead of
107 bool InlineSpiller::reMaterializeFor(MachineBasicBlock::iterator MI) {
108 SlotIndex UseIdx = lis_.getInstructionIndex(MI).getUseIndex();
109 VNInfo *OrigVNI = edit_->getParent().getVNInfoAt(UseIdx);
112 DEBUG(dbgs() << "\tadding <undef> flags: ");
113 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
114 MachineOperand &MO = MI->getOperand(i);
115 if (MO.isReg() && MO.isUse() && MO.getReg() == edit_->getReg())
118 DEBUG(dbgs() << UseIdx << '\t' << *MI);
122 LiveRangeEdit::Remat RM(OrigVNI);
123 if (!edit_->canRematerializeAt(RM, UseIdx, false, lis_)) {
124 usedValues_.insert(OrigVNI);
125 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
129 // If the instruction also writes edit_->getReg(), it had better not require
130 // the same register for uses and defs.
132 SmallVector<unsigned, 8> Ops;
133 tie(Reads, Writes) = MI->readsWritesVirtualRegister(edit_->getReg(), &Ops);
135 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
136 MachineOperand &MO = MI->getOperand(Ops[i]);
137 if (MO.isUse() ? MI->isRegTiedToDefOperand(Ops[i]) : MO.getSubReg()) {
138 usedValues_.insert(OrigVNI);
139 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
145 // Before rematerializing into a register for a single instruction, try to
146 // fold a load into the instruction. That avoids allocating a new register.
147 if (RM.OrigMI->getDesc().canFoldAsLoad() &&
148 foldMemoryOperand(MI, Ops, RM.OrigMI)) {
149 edit_->markRematerialized(RM.ParentVNI);
153 // Alocate a new register for the remat.
154 LiveInterval &NewLI = edit_->create(mri_, lis_, vrm_);
155 NewLI.markNotSpillable();
157 // Finally we can rematerialize OrigMI before MI.
158 SlotIndex DefIdx = edit_->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM,
160 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'
161 << *lis_.getInstructionFromIndex(DefIdx));
164 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
165 MachineOperand &MO = MI->getOperand(Ops[i]);
166 if (MO.isReg() && MO.isUse() && MO.getReg() == edit_->getReg()) {
167 MO.setReg(NewLI.reg);
171 DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI);
173 VNInfo *DefVNI = NewLI.getNextValue(DefIdx, 0, lis_.getVNInfoAllocator());
174 NewLI.addRange(LiveRange(DefIdx, UseIdx.getDefIndex(), DefVNI));
175 DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
179 /// reMaterializeAll - Try to rematerialize as many uses as possible,
180 /// and trim the live ranges after.
181 void InlineSpiller::reMaterializeAll() {
182 // Do a quick scan of the interval values to find if any are remattable.
183 if (!edit_->anyRematerializable(lis_, tii_, aa_))
188 // Try to remat before all uses of edit_->getReg().
189 bool anyRemat = false;
190 for (MachineRegisterInfo::use_nodbg_iterator
191 RI = mri_.use_nodbg_begin(edit_->getReg());
192 MachineInstr *MI = RI.skipInstruction();)
193 anyRemat |= reMaterializeFor(MI);
198 // Remove any values that were completely rematted.
199 bool anyRemoved = false;
200 for (LiveInterval::vni_iterator I = edit_->getParent().vni_begin(),
201 E = edit_->getParent().vni_end(); I != E; ++I) {
203 if (VNI->hasPHIKill() || !edit_->didRematerialize(VNI) ||
204 usedValues_.count(VNI))
206 MachineInstr *DefMI = lis_.getInstructionFromIndex(VNI->def);
207 DEBUG(dbgs() << "\tremoving dead def: " << VNI->def << '\t' << *DefMI);
208 lis_.RemoveMachineInstrFromMaps(DefMI);
209 vrm_.RemoveMachineInstrFromMaps(DefMI);
210 DefMI->eraseFromParent();
211 VNI->def = SlotIndex();
218 // Removing values may cause debug uses where parent is not live.
219 for (MachineRegisterInfo::use_iterator RI = mri_.use_begin(edit_->getReg());
220 MachineInstr *MI = RI.skipInstruction();) {
221 if (!MI->isDebugValue())
223 // Try to preserve the debug value if parent is live immediately after it.
224 MachineBasicBlock::iterator NextMI = MI;
226 if (NextMI != MI->getParent()->end() && !lis_.isNotInMIMap(NextMI)) {
227 SlotIndex Idx = lis_.getInstructionIndex(NextMI);
228 VNInfo *VNI = edit_->getParent().getVNInfoAt(Idx);
229 if (VNI && (VNI->hasPHIKill() || usedValues_.count(VNI)))
232 DEBUG(dbgs() << "Removing debug info due to remat:" << "\t" << *MI);
233 MI->eraseFromParent();
237 /// If MI is a load or store of stackSlot_, it can be removed.
238 bool InlineSpiller::coalesceStackAccess(MachineInstr *MI) {
241 if (!(reg = tii_.isLoadFromStackSlot(MI, FI)) &&
242 !(reg = tii_.isStoreToStackSlot(MI, FI)))
245 // We have a stack access. Is it the right register and slot?
246 if (reg != edit_->getReg() || FI != stackSlot_)
249 DEBUG(dbgs() << "Coalescing stack access: " << *MI);
250 lis_.RemoveMachineInstrFromMaps(MI);
251 MI->eraseFromParent();
255 /// foldMemoryOperand - Try folding stack slot references in Ops into MI.
256 /// @param MI Instruction using or defining the current register.
257 /// @param Ops Operand indices from readsWritesVirtualRegister().
258 /// @param LoadMI Load instruction to use instead of stack slot when non-null.
259 /// @return True on success, and MI will be erased.
260 bool InlineSpiller::foldMemoryOperand(MachineBasicBlock::iterator MI,
261 const SmallVectorImpl<unsigned> &Ops,
262 MachineInstr *LoadMI) {
263 // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
265 SmallVector<unsigned, 8> FoldOps;
266 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
267 unsigned Idx = Ops[i];
268 MachineOperand &MO = MI->getOperand(Idx);
271 // FIXME: Teach targets to deal with subregs.
274 // We cannot fold a load instruction into a def.
275 if (LoadMI && MO.isDef())
277 // Tied use operands should not be passed to foldMemoryOperand.
278 if (!MI->isRegTiedToDefOperand(Idx))
279 FoldOps.push_back(Idx);
282 MachineInstr *FoldMI =
283 LoadMI ? tii_.foldMemoryOperand(MI, FoldOps, LoadMI)
284 : tii_.foldMemoryOperand(MI, FoldOps, stackSlot_);
287 lis_.ReplaceMachineInstrInMaps(MI, FoldMI);
289 vrm_.addSpillSlotUse(stackSlot_, FoldMI);
290 MI->eraseFromParent();
291 DEBUG(dbgs() << "\tfolded: " << *FoldMI);
295 /// insertReload - Insert a reload of NewLI.reg before MI.
296 void InlineSpiller::insertReload(LiveInterval &NewLI,
297 MachineBasicBlock::iterator MI) {
298 MachineBasicBlock &MBB = *MI->getParent();
299 SlotIndex Idx = lis_.getInstructionIndex(MI).getDefIndex();
300 tii_.loadRegFromStackSlot(MBB, MI, NewLI.reg, stackSlot_, rc_, &tri_);
301 --MI; // Point to load instruction.
302 SlotIndex LoadIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex();
303 vrm_.addSpillSlotUse(stackSlot_, MI);
304 DEBUG(dbgs() << "\treload: " << LoadIdx << '\t' << *MI);
305 VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0,
306 lis_.getVNInfoAllocator());
307 NewLI.addRange(LiveRange(LoadIdx, Idx, LoadVNI));
310 /// insertSpill - Insert a spill of NewLI.reg after MI.
311 void InlineSpiller::insertSpill(LiveInterval &NewLI,
312 MachineBasicBlock::iterator MI) {
313 MachineBasicBlock &MBB = *MI->getParent();
315 // Get the defined value. It could be an early clobber so keep the def index.
316 SlotIndex Idx = lis_.getInstructionIndex(MI).getDefIndex();
317 VNInfo *VNI = edit_->getParent().getVNInfoAt(Idx);
318 assert(VNI && VNI->def.getDefIndex() == Idx && "Inconsistent VNInfo");
321 tii_.storeRegToStackSlot(MBB, ++MI, NewLI.reg, true, stackSlot_, rc_, &tri_);
322 --MI; // Point to store instruction.
323 SlotIndex StoreIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex();
324 vrm_.addSpillSlotUse(stackSlot_, MI);
325 DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MI);
326 VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, lis_.getVNInfoAllocator());
327 NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
330 void InlineSpiller::spill(LiveInterval *li,
331 SmallVectorImpl<LiveInterval*> &newIntervals,
332 const SmallVectorImpl<LiveInterval*> &spillIs) {
333 LiveRangeEdit edit(*li, newIntervals, spillIs);
336 mf_.verify(&pass_, "After inline spill");
339 void InlineSpiller::spill(LiveRangeEdit &edit) {
341 assert(!TargetRegisterInfo::isStackSlot(edit.getReg())
342 && "Trying to spill a stack slot.");
343 DEBUG(dbgs() << "Inline spilling "
344 << mri_.getRegClass(edit.getReg())->getName()
345 << ':' << edit.getParent() << "\n");
346 assert(edit.getParent().isSpillable() &&
347 "Attempting to spill already spilled value.");
351 // Remat may handle everything.
352 if (edit_->getParent().empty())
355 rc_ = mri_.getRegClass(edit.getReg());
356 stackSlot_ = vrm_.assignVirt2StackSlot(edit_->getReg());
358 // Update LiveStacks now that we are committed to spilling.
359 LiveInterval &stacklvr = lss_.getOrCreateInterval(stackSlot_, rc_);
360 assert(stacklvr.empty() && "Just created stack slot not empty");
361 stacklvr.getNextValue(SlotIndex(), 0, lss_.getVNInfoAllocator());
362 stacklvr.MergeRangesInAsValue(edit_->getParent(), stacklvr.getValNumInfo(0));
364 // Iterate over instructions using register.
365 for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(edit.getReg());
366 MachineInstr *MI = RI.skipInstruction();) {
368 // Debug values are not allowed to affect codegen.
369 if (MI->isDebugValue()) {
370 // Modify DBG_VALUE now that the value is in a spill slot.
371 uint64_t Offset = MI->getOperand(1).getImm();
372 const MDNode *MDPtr = MI->getOperand(2).getMetadata();
373 DebugLoc DL = MI->getDebugLoc();
374 if (MachineInstr *NewDV = tii_.emitFrameIndexDebugValue(mf_, stackSlot_,
375 Offset, MDPtr, DL)) {
376 DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
377 MachineBasicBlock *MBB = MI->getParent();
378 MBB->insert(MBB->erase(MI), NewDV);
380 DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI);
381 MI->eraseFromParent();
386 // Stack slot accesses may coalesce away.
387 if (coalesceStackAccess(MI))
390 // Analyze instruction.
392 SmallVector<unsigned, 8> Ops;
393 tie(Reads, Writes) = MI->readsWritesVirtualRegister(edit.getReg(), &Ops);
395 // Attempt to fold memory ops.
396 if (foldMemoryOperand(MI, Ops))
399 // Allocate interval around instruction.
400 // FIXME: Infer regclass from instruction alone.
401 LiveInterval &NewLI = edit.create(mri_, lis_, vrm_);
402 NewLI.markNotSpillable();
405 insertReload(NewLI, MI);
407 // Rewrite instruction operands.
408 bool hasLiveDef = false;
409 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
410 MachineOperand &MO = MI->getOperand(Ops[i]);
411 MO.setReg(NewLI.reg);
413 if (!MI->isRegTiedToDefOperand(Ops[i]))
421 // FIXME: Use a second vreg if instruction has no tied ops.
422 if (Writes && hasLiveDef)
423 insertSpill(NewLI, MI);
425 DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');