1 //===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The inline spiller modifies the machine function directly instead of
11 // inserting spills and restores in VirtRegMap.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
17 #include "llvm/ADT/SetVector.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/ADT/TinyPtrVector.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/LiveRangeEdit.h"
23 #include "llvm/CodeGen/LiveStackAnalysis.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineInstrBundle.h"
30 #include "llvm/CodeGen/MachineLoopInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/VirtRegMap.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
41 STATISTIC(NumSpilledRanges, "Number of spilled live ranges");
42 STATISTIC(NumSnippets, "Number of spilled snippets");
43 STATISTIC(NumSpills, "Number of spills inserted");
44 STATISTIC(NumSpillsRemoved, "Number of spills removed");
45 STATISTIC(NumReloads, "Number of reloads inserted");
46 STATISTIC(NumReloadsRemoved, "Number of reloads removed");
47 STATISTIC(NumFolded, "Number of folded stack accesses");
48 STATISTIC(NumFoldedLoads, "Number of folded loads");
49 STATISTIC(NumRemats, "Number of rematerialized defs for spilling");
50 STATISTIC(NumOmitReloadSpill, "Number of omitted spills of reloads");
51 STATISTIC(NumHoists, "Number of hoisted spills");
53 static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden,
54 cl::desc("Disable inline spill hoisting"));
57 class InlineSpiller : public Spiller {
62 MachineDominatorTree &MDT;
63 MachineLoopInfo &Loops;
65 MachineFrameInfo &MFI;
66 MachineRegisterInfo &MRI;
67 const TargetInstrInfo &TII;
68 const TargetRegisterInfo &TRI;
69 const MachineBlockFrequencyInfo &MBFI;
71 // Variables that are valid during spill(), but used by multiple methods.
73 LiveInterval *StackInt;
77 // All registers to spill to StackSlot, including the main register.
78 SmallVector<unsigned, 8> RegsToSpill;
80 // All COPY instructions to/from snippets.
81 // They are ignored since both operands refer to the same stack slot.
82 SmallPtrSet<MachineInstr*, 8> SnippetCopies;
84 // Values that failed to remat at some point.
85 SmallPtrSet<VNInfo*, 8> UsedValues;
88 // Information about a value that was defined by a copy from a sibling
91 // True when all reaching defs were reloads: No spill is necessary.
92 bool AllDefsAreReloads;
94 // True when value is defined by an original PHI not from splitting.
97 // True when the COPY defining this value killed its source.
100 // The preferred register to spill.
103 // The value of SpillReg that should be spilled.
106 // The block where SpillVNI should be spilled. Currently, this must be the
107 // block containing SpillVNI->def.
108 MachineBasicBlock *SpillMBB;
110 // A defining instruction that is not a sibling copy or a reload, or NULL.
111 // This can be used as a template for rematerialization.
114 // List of values that depend on this one. These values are actually the
115 // same, but live range splitting has placed them in different registers,
116 // or SSA update needed to insert PHI-defs to preserve SSA form. This is
117 // copies of the current value and phi-kills. Usually only phi-kills cause
118 // more than one dependent value.
119 TinyPtrVector<VNInfo*> Deps;
121 SibValueInfo(unsigned Reg, VNInfo *VNI)
122 : AllDefsAreReloads(true), DefByOrigPHI(false), KillsSource(false),
123 SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {}
125 // Returns true when a def has been found.
126 bool hasDef() const { return DefByOrigPHI || DefMI; }
130 // Values in RegsToSpill defined by sibling copies.
131 typedef DenseMap<VNInfo*, SibValueInfo> SibValueMap;
132 SibValueMap SibValues;
134 // Dead defs generated during spilling.
135 SmallVector<MachineInstr*, 8> DeadDefs;
140 InlineSpiller(MachineFunctionPass &pass,
144 LIS(pass.getAnalysis<LiveIntervals>()),
145 LSS(pass.getAnalysis<LiveStacks>()),
146 AA(&pass.getAnalysis<AliasAnalysis>()),
147 MDT(pass.getAnalysis<MachineDominatorTree>()),
148 Loops(pass.getAnalysis<MachineLoopInfo>()),
150 MFI(*mf.getFrameInfo()),
151 MRI(mf.getRegInfo()),
152 TII(*mf.getTarget().getInstrInfo()),
153 TRI(*mf.getTarget().getRegisterInfo()),
154 MBFI(pass.getAnalysis<MachineBlockFrequencyInfo>()) {}
156 void spill(LiveRangeEdit &);
159 bool isSnippet(const LiveInterval &SnipLI);
160 void collectRegsToSpill();
162 bool isRegToSpill(unsigned Reg) {
163 return std::find(RegsToSpill.begin(),
164 RegsToSpill.end(), Reg) != RegsToSpill.end();
167 bool isSibling(unsigned Reg);
168 MachineInstr *traceSiblingValue(unsigned, VNInfo*, VNInfo*);
169 void propagateSiblingValue(SibValueMap::iterator, VNInfo *VNI = 0);
170 void analyzeSiblingValues();
172 bool hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI);
173 void eliminateRedundantSpills(LiveInterval &LI, VNInfo *VNI);
175 void markValueUsed(LiveInterval*, VNInfo*);
176 bool reMaterializeFor(LiveInterval&, MachineBasicBlock::iterator MI);
177 void reMaterializeAll();
179 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
180 bool foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> >,
181 MachineInstr *LoadMI = 0);
182 void insertReload(unsigned VReg, SlotIndex, MachineBasicBlock::iterator MI);
183 void insertSpill(unsigned VReg, bool isKill, MachineBasicBlock::iterator MI);
185 void spillAroundUses(unsigned Reg);
191 Spiller *createInlineSpiller(MachineFunctionPass &pass,
194 return new InlineSpiller(pass, mf, vrm);
198 //===----------------------------------------------------------------------===//
200 //===----------------------------------------------------------------------===//
202 // When spilling a virtual register, we also spill any snippets it is connected
203 // to. The snippets are small live ranges that only have a single real use,
204 // leftovers from live range splitting. Spilling them enables memory operand
205 // folding or tightens the live range around the single use.
207 // This minimizes register pressure and maximizes the store-to-load distance for
208 // spill slots which can be important in tight loops.
210 /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
211 /// otherwise return 0.
212 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) {
213 if (!MI->isFullCopy())
215 if (MI->getOperand(0).getReg() == Reg)
216 return MI->getOperand(1).getReg();
217 if (MI->getOperand(1).getReg() == Reg)
218 return MI->getOperand(0).getReg();
222 /// isSnippet - Identify if a live interval is a snippet that should be spilled.
223 /// It is assumed that SnipLI is a virtual register with the same original as
225 bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
226 unsigned Reg = Edit->getReg();
228 // A snippet is a tiny live range with only a single instruction using it
229 // besides copies to/from Reg or spills/fills. We accept:
231 // %snip = COPY %Reg / FILL fi#
233 // %Reg = COPY %snip / SPILL %snip, fi#
235 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
238 MachineInstr *UseMI = 0;
240 // Check that all uses satisfy our criteria.
241 for (MachineRegisterInfo::reg_nodbg_iterator
242 RI = MRI.reg_nodbg_begin(SnipLI.reg);
243 MachineInstr *MI = RI.skipInstruction();) {
245 // Allow copies to/from Reg.
246 if (isFullCopyOf(MI, Reg))
249 // Allow stack slot loads.
251 if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot)
254 // Allow stack slot stores.
255 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
258 // Allow a single additional instruction.
259 if (UseMI && MI != UseMI)
266 /// collectRegsToSpill - Collect live range snippets that only have a single
268 void InlineSpiller::collectRegsToSpill() {
269 unsigned Reg = Edit->getReg();
271 // Main register always spills.
272 RegsToSpill.assign(1, Reg);
273 SnippetCopies.clear();
275 // Snippets all have the same original, so there can't be any for an original
280 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg);
281 MachineInstr *MI = RI.skipInstruction();) {
282 unsigned SnipReg = isFullCopyOf(MI, Reg);
283 if (!isSibling(SnipReg))
285 LiveInterval &SnipLI = LIS.getInterval(SnipReg);
286 if (!isSnippet(SnipLI))
288 SnippetCopies.insert(MI);
289 if (isRegToSpill(SnipReg))
291 RegsToSpill.push_back(SnipReg);
292 DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n');
298 //===----------------------------------------------------------------------===//
300 //===----------------------------------------------------------------------===//
302 // After live range splitting, some values to be spilled may be defined by
303 // copies from sibling registers. We trace the sibling copies back to the
304 // original value if it still exists. We need it for rematerialization.
306 // Even when the value can't be rematerialized, we still want to determine if
307 // the value has already been spilled, or we may want to hoist the spill from a
310 bool InlineSpiller::isSibling(unsigned Reg) {
311 return TargetRegisterInfo::isVirtualRegister(Reg) &&
312 VRM.getOriginal(Reg) == Original;
316 static raw_ostream &operator<<(raw_ostream &OS,
317 const InlineSpiller::SibValueInfo &SVI) {
318 OS << "spill " << PrintReg(SVI.SpillReg) << ':'
319 << SVI.SpillVNI->id << '@' << SVI.SpillVNI->def;
321 OS << " in BB#" << SVI.SpillMBB->getNumber();
322 if (SVI.AllDefsAreReloads)
323 OS << " all-reloads";
324 if (SVI.DefByOrigPHI)
329 for (unsigned i = 0, e = SVI.Deps.size(); i != e; ++i)
330 OS << ' ' << SVI.Deps[i]->id << '@' << SVI.Deps[i]->def;
333 OS << " def: " << *SVI.DefMI;
340 /// propagateSiblingValue - Propagate the value in SVI to dependents if it is
341 /// known. Otherwise remember the dependency for later.
343 /// @param SVIIter SibValues entry to propagate.
344 /// @param VNI Dependent value, or NULL to propagate to all saved dependents.
345 void InlineSpiller::propagateSiblingValue(SibValueMap::iterator SVIIter,
347 SibValueMap::value_type *SVI = &*SVIIter;
349 // When VNI is non-NULL, add it to SVI's deps, and only propagate to that.
350 TinyPtrVector<VNInfo*> FirstDeps;
352 FirstDeps.push_back(VNI);
353 SVI->second.Deps.push_back(VNI);
356 // Has the value been completely determined yet? If not, defer propagation.
357 if (!SVI->second.hasDef())
360 // Work list of values to propagate.
361 SmallSetVector<SibValueMap::value_type *, 8> WorkList;
362 WorkList.insert(SVI);
365 SVI = WorkList.pop_back_val();
366 TinyPtrVector<VNInfo*> *Deps = VNI ? &FirstDeps : &SVI->second.Deps;
369 SibValueInfo &SV = SVI->second;
371 SV.SpillMBB = LIS.getMBBFromIndex(SV.SpillVNI->def);
373 DEBUG(dbgs() << " prop to " << Deps->size() << ": "
374 << SVI->first->id << '@' << SVI->first->def << ":\t" << SV);
376 assert(SV.hasDef() && "Propagating undefined value");
378 // Should this value be propagated as a preferred spill candidate? We don't
379 // propagate values of registers that are about to spill.
380 bool PropSpill = !DisableHoisting && !isRegToSpill(SV.SpillReg);
381 unsigned SpillDepth = ~0u;
383 for (TinyPtrVector<VNInfo*>::iterator DepI = Deps->begin(),
384 DepE = Deps->end(); DepI != DepE; ++DepI) {
385 SibValueMap::iterator DepSVI = SibValues.find(*DepI);
386 assert(DepSVI != SibValues.end() && "Dependent value not in SibValues");
387 SibValueInfo &DepSV = DepSVI->second;
389 DepSV.SpillMBB = LIS.getMBBFromIndex(DepSV.SpillVNI->def);
391 bool Changed = false;
393 // Propagate defining instruction.
394 if (!DepSV.hasDef()) {
396 DepSV.DefMI = SV.DefMI;
397 DepSV.DefByOrigPHI = SV.DefByOrigPHI;
400 // Propagate AllDefsAreReloads. For PHI values, this computes an AND of
402 if (!SV.AllDefsAreReloads && DepSV.AllDefsAreReloads) {
404 DepSV.AllDefsAreReloads = false;
407 // Propagate best spill value.
408 if (PropSpill && SV.SpillVNI != DepSV.SpillVNI) {
409 if (SV.SpillMBB == DepSV.SpillMBB) {
410 // DepSV is in the same block. Hoist when dominated.
411 if (DepSV.KillsSource && SV.SpillVNI->def < DepSV.SpillVNI->def) {
412 // This is an alternative def earlier in the same MBB.
413 // Hoist the spill as far as possible in SpillMBB. This can ease
414 // register pressure:
420 // Hoisting the spill of s to immediately after the def removes the
421 // interference between x and y:
427 // This hoist only helps when the DepSV copy kills its source.
429 DepSV.SpillReg = SV.SpillReg;
430 DepSV.SpillVNI = SV.SpillVNI;
431 DepSV.SpillMBB = SV.SpillMBB;
434 // DepSV is in a different block.
435 if (SpillDepth == ~0u)
436 SpillDepth = Loops.getLoopDepth(SV.SpillMBB);
438 // Also hoist spills to blocks with smaller loop depth, but make sure
439 // that the new value dominates. Non-phi dependents are always
440 // dominated, phis need checking.
441 if ((Loops.getLoopDepth(DepSV.SpillMBB) > SpillDepth) &&
442 (!DepSVI->first->isPHIDef() ||
443 MDT.dominates(SV.SpillMBB, DepSV.SpillMBB))) {
445 DepSV.SpillReg = SV.SpillReg;
446 DepSV.SpillVNI = SV.SpillVNI;
447 DepSV.SpillMBB = SV.SpillMBB;
455 // Something changed in DepSVI. Propagate to dependents.
456 WorkList.insert(&*DepSVI);
458 DEBUG(dbgs() << " update " << DepSVI->first->id << '@'
459 << DepSVI->first->def << " to:\t" << DepSV);
461 } while (!WorkList.empty());
464 /// traceSiblingValue - Trace a value that is about to be spilled back to the
465 /// real defining instructions by looking through sibling copies. Always stay
466 /// within the range of OrigVNI so the registers are known to carry the same
469 /// Determine if the value is defined by all reloads, so spilling isn't
470 /// necessary - the value is already in the stack slot.
472 /// Return a defining instruction that may be a candidate for rematerialization.
474 MachineInstr *InlineSpiller::traceSiblingValue(unsigned UseReg, VNInfo *UseVNI,
476 // Check if a cached value already exists.
477 SibValueMap::iterator SVI;
480 SibValues.insert(std::make_pair(UseVNI, SibValueInfo(UseReg, UseVNI)));
482 DEBUG(dbgs() << "Cached value " << PrintReg(UseReg) << ':'
483 << UseVNI->id << '@' << UseVNI->def << ' ' << SVI->second);
484 return SVI->second.DefMI;
487 DEBUG(dbgs() << "Tracing value " << PrintReg(UseReg) << ':'
488 << UseVNI->id << '@' << UseVNI->def << '\n');
490 // List of (Reg, VNI) that have been inserted into SibValues, but need to be
492 SmallVector<std::pair<unsigned, VNInfo*>, 8> WorkList;
493 WorkList.push_back(std::make_pair(UseReg, UseVNI));
498 tie(Reg, VNI) = WorkList.pop_back_val();
499 DEBUG(dbgs() << " " << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def
502 // First check if this value has already been computed.
503 SVI = SibValues.find(VNI);
504 assert(SVI != SibValues.end() && "Missing SibValues entry");
506 // Trace through PHI-defs created by live range splitting.
507 if (VNI->isPHIDef()) {
508 // Stop at original PHIs. We don't know the value at the predecessors.
509 if (VNI->def == OrigVNI->def) {
510 DEBUG(dbgs() << "orig phi value\n");
511 SVI->second.DefByOrigPHI = true;
512 SVI->second.AllDefsAreReloads = false;
513 propagateSiblingValue(SVI);
517 // This is a PHI inserted by live range splitting. We could trace the
518 // live-out value from predecessor blocks, but that search can be very
519 // expensive if there are many predecessors and many more PHIs as
520 // generated by tail-dup when it sees an indirectbr. Instead, look at
521 // all the non-PHI defs that have the same value as OrigVNI. They must
522 // jointly dominate VNI->def. This is not optimal since VNI may actually
523 // be jointly dominated by a smaller subset of defs, so there is a change
524 // we will miss a AllDefsAreReloads optimization.
526 // Separate all values dominated by OrigVNI into PHIs and non-PHIs.
527 SmallVector<VNInfo*, 8> PHIs, NonPHIs;
528 LiveInterval &LI = LIS.getInterval(Reg);
529 LiveInterval &OrigLI = LIS.getInterval(Original);
531 for (LiveInterval::vni_iterator VI = LI.vni_begin(), VE = LI.vni_end();
534 if (VNI2->isUnused())
536 if (!OrigLI.containsOneValue() &&
537 OrigLI.getVNInfoAt(VNI2->def) != OrigVNI)
539 if (VNI2->isPHIDef() && VNI2->def != OrigVNI->def)
540 PHIs.push_back(VNI2);
542 NonPHIs.push_back(VNI2);
544 DEBUG(dbgs() << "split phi value, checking " << PHIs.size()
545 << " phi-defs, and " << NonPHIs.size()
546 << " non-phi/orig defs\n");
548 // Create entries for all the PHIs. Don't add them to the worklist, we
549 // are processing all of them in one go here.
550 for (unsigned i = 0, e = PHIs.size(); i != e; ++i)
551 SibValues.insert(std::make_pair(PHIs[i], SibValueInfo(Reg, PHIs[i])));
553 // Add every PHI as a dependent of all the non-PHIs.
554 for (unsigned i = 0, e = NonPHIs.size(); i != e; ++i) {
555 VNInfo *NonPHI = NonPHIs[i];
556 // Known value? Try an insertion.
558 SibValues.insert(std::make_pair(NonPHI, SibValueInfo(Reg, NonPHI)));
559 // Add all the PHIs as dependents of NonPHI.
560 for (unsigned pi = 0, pe = PHIs.size(); pi != pe; ++pi)
561 SVI->second.Deps.push_back(PHIs[pi]);
562 // This is the first time we see NonPHI, add it to the worklist.
564 WorkList.push_back(std::make_pair(Reg, NonPHI));
566 // Propagate to all inserted PHIs, not just VNI.
567 propagateSiblingValue(SVI);
570 // Next work list item.
574 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
575 assert(MI && "Missing def");
577 // Trace through sibling copies.
578 if (unsigned SrcReg = isFullCopyOf(MI, Reg)) {
579 if (isSibling(SrcReg)) {
580 LiveInterval &SrcLI = LIS.getInterval(SrcReg);
581 LiveQueryResult SrcQ = SrcLI.Query(VNI->def);
582 assert(SrcQ.valueIn() && "Copy from non-existing value");
583 // Check if this COPY kills its source.
584 SVI->second.KillsSource = SrcQ.isKill();
585 VNInfo *SrcVNI = SrcQ.valueIn();
586 DEBUG(dbgs() << "copy of " << PrintReg(SrcReg) << ':'
587 << SrcVNI->id << '@' << SrcVNI->def
588 << " kill=" << unsigned(SVI->second.KillsSource) << '\n');
589 // Known sibling source value? Try an insertion.
590 tie(SVI, Inserted) = SibValues.insert(std::make_pair(SrcVNI,
591 SibValueInfo(SrcReg, SrcVNI)));
592 // This is the first time we see Src, add it to the worklist.
594 WorkList.push_back(std::make_pair(SrcReg, SrcVNI));
595 propagateSiblingValue(SVI, VNI);
596 // Next work list item.
601 // Track reachable reloads.
602 SVI->second.DefMI = MI;
603 SVI->second.SpillMBB = MI->getParent();
605 if (Reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) {
606 DEBUG(dbgs() << "reload\n");
607 propagateSiblingValue(SVI);
608 // Next work list item.
612 // Potential remat candidate.
613 DEBUG(dbgs() << "def " << *MI);
614 SVI->second.AllDefsAreReloads = false;
615 propagateSiblingValue(SVI);
616 } while (!WorkList.empty());
618 // Look up the value we were looking for. We already did this lookup at the
619 // top of the function, but SibValues may have been invalidated.
620 SVI = SibValues.find(UseVNI);
621 assert(SVI != SibValues.end() && "Didn't compute requested info");
622 DEBUG(dbgs() << " traced to:\t" << SVI->second);
623 return SVI->second.DefMI;
626 /// analyzeSiblingValues - Trace values defined by sibling copies back to
627 /// something that isn't a sibling copy.
629 /// Keep track of values that may be rematerializable.
630 void InlineSpiller::analyzeSiblingValues() {
633 // No siblings at all?
634 if (Edit->getReg() == Original)
637 LiveInterval &OrigLI = LIS.getInterval(Original);
638 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
639 unsigned Reg = RegsToSpill[i];
640 LiveInterval &LI = LIS.getInterval(Reg);
641 for (LiveInterval::const_vni_iterator VI = LI.vni_begin(),
642 VE = LI.vni_end(); VI != VE; ++VI) {
646 MachineInstr *DefMI = 0;
647 if (!VNI->isPHIDef()) {
648 DefMI = LIS.getInstructionFromIndex(VNI->def);
649 assert(DefMI && "No defining instruction");
651 // Check possible sibling copies.
652 if (VNI->isPHIDef() || DefMI->isCopy()) {
653 VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
654 assert(OrigVNI && "Def outside original live range");
655 if (OrigVNI->def != VNI->def)
656 DefMI = traceSiblingValue(Reg, VNI, OrigVNI);
658 if (DefMI && Edit->checkRematerializable(VNI, DefMI, AA)) {
659 DEBUG(dbgs() << "Value " << PrintReg(Reg) << ':' << VNI->id << '@'
660 << VNI->def << " may remat from " << *DefMI);
666 /// hoistSpill - Given a sibling copy that defines a value to be spilled, insert
667 /// a spill at a better location.
668 bool InlineSpiller::hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI) {
669 SlotIndex Idx = LIS.getInstructionIndex(CopyMI);
670 VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getRegSlot());
671 assert(VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy");
672 SibValueMap::iterator I = SibValues.find(VNI);
673 if (I == SibValues.end())
676 const SibValueInfo &SVI = I->second;
678 // Let the normal folding code deal with the boring case.
679 if (!SVI.AllDefsAreReloads && SVI.SpillVNI == VNI)
682 // SpillReg may have been deleted by remat and DCE.
683 if (!LIS.hasInterval(SVI.SpillReg)) {
684 DEBUG(dbgs() << "Stale interval: " << PrintReg(SVI.SpillReg) << '\n');
689 LiveInterval &SibLI = LIS.getInterval(SVI.SpillReg);
690 if (!SibLI.containsValue(SVI.SpillVNI)) {
691 DEBUG(dbgs() << "Stale value: " << PrintReg(SVI.SpillReg) << '\n');
696 // Conservatively extend the stack slot range to the range of the original
697 // value. We may be able to do better with stack slot coloring by being more
699 assert(StackInt && "No stack slot assigned yet.");
700 LiveInterval &OrigLI = LIS.getInterval(Original);
701 VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
702 StackInt->MergeValueInAsValue(OrigLI, OrigVNI, StackInt->getValNumInfo(0));
703 DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": "
704 << *StackInt << '\n');
706 // Already spilled everywhere.
707 if (SVI.AllDefsAreReloads) {
708 DEBUG(dbgs() << "\tno spill needed: " << SVI);
709 ++NumOmitReloadSpill;
712 // We are going to spill SVI.SpillVNI immediately after its def, so clear out
713 // any later spills of the same value.
714 eliminateRedundantSpills(SibLI, SVI.SpillVNI);
716 MachineBasicBlock *MBB = LIS.getMBBFromIndex(SVI.SpillVNI->def);
717 MachineBasicBlock::iterator MII;
718 if (SVI.SpillVNI->isPHIDef())
719 MII = MBB->SkipPHIsAndLabels(MBB->begin());
721 MachineInstr *DefMI = LIS.getInstructionFromIndex(SVI.SpillVNI->def);
722 assert(DefMI && "Defining instruction disappeared");
726 // Insert spill without kill flag immediately after def.
727 TII.storeRegToStackSlot(*MBB, MII, SVI.SpillReg, false, StackSlot,
728 MRI.getRegClass(SVI.SpillReg), &TRI);
729 --MII; // Point to store instruction.
730 LIS.InsertMachineInstrInMaps(MII);
731 DEBUG(dbgs() << "\thoisted: " << SVI.SpillVNI->def << '\t' << *MII);
738 /// eliminateRedundantSpills - SLI:VNI is known to be on the stack. Remove any
739 /// redundant spills of this value in SLI.reg and sibling copies.
740 void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
741 assert(VNI && "Missing value");
742 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
743 WorkList.push_back(std::make_pair(&SLI, VNI));
744 assert(StackInt && "No stack slot assigned yet.");
748 tie(LI, VNI) = WorkList.pop_back_val();
749 unsigned Reg = LI->reg;
750 DEBUG(dbgs() << "Checking redundant spills for "
751 << VNI->id << '@' << VNI->def << " in " << *LI << '\n');
753 // Regs to spill are taken care of.
754 if (isRegToSpill(Reg))
757 // Add all of VNI's live range to StackInt.
758 StackInt->MergeValueInAsValue(*LI, VNI, StackInt->getValNumInfo(0));
759 DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n');
761 // Find all spills and copies of VNI.
762 for (MachineRegisterInfo::use_nodbg_iterator UI = MRI.use_nodbg_begin(Reg);
763 MachineInstr *MI = UI.skipInstruction();) {
764 if (!MI->isCopy() && !MI->mayStore())
766 SlotIndex Idx = LIS.getInstructionIndex(MI);
767 if (LI->getVNInfoAt(Idx) != VNI)
770 // Follow sibling copies down the dominator tree.
771 if (unsigned DstReg = isFullCopyOf(MI, Reg)) {
772 if (isSibling(DstReg)) {
773 LiveInterval &DstLI = LIS.getInterval(DstReg);
774 VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getRegSlot());
775 assert(DstVNI && "Missing defined value");
776 assert(DstVNI->def == Idx.getRegSlot() && "Wrong copy def slot");
777 WorkList.push_back(std::make_pair(&DstLI, DstVNI));
784 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
785 DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << *MI);
786 // eliminateDeadDefs won't normally remove stores, so switch opcode.
787 MI->setDesc(TII.get(TargetOpcode::KILL));
788 DeadDefs.push_back(MI);
793 } while (!WorkList.empty());
797 //===----------------------------------------------------------------------===//
799 //===----------------------------------------------------------------------===//
801 /// markValueUsed - Remember that VNI failed to rematerialize, so its defining
802 /// instruction cannot be eliminated. See through snippet copies
803 void InlineSpiller::markValueUsed(LiveInterval *LI, VNInfo *VNI) {
804 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
805 WorkList.push_back(std::make_pair(LI, VNI));
807 tie(LI, VNI) = WorkList.pop_back_val();
808 if (!UsedValues.insert(VNI))
811 if (VNI->isPHIDef()) {
812 MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
813 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
814 PE = MBB->pred_end(); PI != PE; ++PI) {
815 VNInfo *PVNI = LI->getVNInfoBefore(LIS.getMBBEndIdx(*PI));
817 WorkList.push_back(std::make_pair(LI, PVNI));
822 // Follow snippet copies.
823 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
824 if (!SnippetCopies.count(MI))
826 LiveInterval &SnipLI = LIS.getInterval(MI->getOperand(1).getReg());
827 assert(isRegToSpill(SnipLI.reg) && "Unexpected register in copy");
828 VNInfo *SnipVNI = SnipLI.getVNInfoAt(VNI->def.getRegSlot(true));
829 assert(SnipVNI && "Snippet undefined before copy");
830 WorkList.push_back(std::make_pair(&SnipLI, SnipVNI));
831 } while (!WorkList.empty());
834 /// reMaterializeFor - Attempt to rematerialize before MI instead of reloading.
835 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg,
836 MachineBasicBlock::iterator MI) {
837 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
838 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
841 DEBUG(dbgs() << "\tadding <undef> flags: ");
842 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
843 MachineOperand &MO = MI->getOperand(i);
844 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
847 DEBUG(dbgs() << UseIdx << '\t' << *MI);
851 if (SnippetCopies.count(MI))
854 // Use an OrigVNI from traceSiblingValue when ParentVNI is a sibling copy.
855 LiveRangeEdit::Remat RM(ParentVNI);
856 SibValueMap::const_iterator SibI = SibValues.find(ParentVNI);
857 if (SibI != SibValues.end())
858 RM.OrigMI = SibI->second.DefMI;
859 if (!Edit->canRematerializeAt(RM, UseIdx, false)) {
860 markValueUsed(&VirtReg, ParentVNI);
861 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
865 // If the instruction also writes VirtReg.reg, it had better not require the
866 // same register for uses and defs.
867 SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops;
868 MIBundleOperands::VirtRegInfo RI =
869 MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops);
871 markValueUsed(&VirtReg, ParentVNI);
872 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
876 // Before rematerializing into a register for a single instruction, try to
877 // fold a load into the instruction. That avoids allocating a new register.
878 if (RM.OrigMI->canFoldAsLoad() &&
879 foldMemoryOperand(Ops, RM.OrigMI)) {
880 Edit->markRematerialized(RM.ParentVNI);
885 // Alocate a new register for the remat.
886 unsigned NewVReg = Edit->createFrom(Original);
888 // Finally we can rematerialize OrigMI before MI.
889 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewVReg, RM,
892 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'
893 << *LIS.getInstructionFromIndex(DefIdx));
896 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
897 MachineOperand &MO = MI->getOperand(Ops[i].second);
898 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
903 DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI << '\n');
909 /// reMaterializeAll - Try to rematerialize as many uses as possible,
910 /// and trim the live ranges after.
911 void InlineSpiller::reMaterializeAll() {
912 // analyzeSiblingValues has already tested all relevant defining instructions.
913 if (!Edit->anyRematerializable(AA))
918 // Try to remat before all uses of snippets.
919 bool anyRemat = false;
920 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
921 unsigned Reg = RegsToSpill[i];
922 LiveInterval &LI = LIS.getInterval(Reg);
923 for (MachineRegisterInfo::use_nodbg_iterator
924 RI = MRI.use_nodbg_begin(Reg);
925 MachineInstr *MI = RI.skipBundle();)
926 anyRemat |= reMaterializeFor(LI, MI);
931 // Remove any values that were completely rematted.
932 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
933 unsigned Reg = RegsToSpill[i];
934 LiveInterval &LI = LIS.getInterval(Reg);
935 for (LiveInterval::vni_iterator I = LI.vni_begin(), E = LI.vni_end();
938 if (VNI->isUnused() || VNI->isPHIDef() || UsedValues.count(VNI))
940 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
941 MI->addRegisterDead(Reg, &TRI);
942 if (!MI->allDefsAreDead())
944 DEBUG(dbgs() << "All defs dead: " << *MI);
945 DeadDefs.push_back(MI);
949 // Eliminate dead code after remat. Note that some snippet copies may be
951 if (DeadDefs.empty())
953 DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n");
954 Edit->eliminateDeadDefs(DeadDefs, RegsToSpill);
956 // Get rid of deleted and empty intervals.
957 unsigned ResultPos = 0;
958 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
959 unsigned Reg = RegsToSpill[i];
960 if (!LIS.hasInterval(Reg))
963 LiveInterval &LI = LIS.getInterval(Reg);
965 Edit->eraseVirtReg(Reg);
969 RegsToSpill[ResultPos++] = Reg;
971 RegsToSpill.erase(RegsToSpill.begin() + ResultPos, RegsToSpill.end());
972 DEBUG(dbgs() << RegsToSpill.size() << " registers to spill after remat.\n");
976 //===----------------------------------------------------------------------===//
978 //===----------------------------------------------------------------------===//
980 /// If MI is a load or store of StackSlot, it can be removed.
981 bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
983 unsigned InstrReg = TII.isLoadFromStackSlot(MI, FI);
984 bool IsLoad = InstrReg;
986 InstrReg = TII.isStoreToStackSlot(MI, FI);
988 // We have a stack access. Is it the right register and slot?
989 if (InstrReg != Reg || FI != StackSlot)
992 DEBUG(dbgs() << "Coalescing stack access: " << *MI);
993 LIS.RemoveMachineInstrFromMaps(MI);
994 MI->eraseFromParent();
1007 #if !defined(NDEBUG)
1008 // Dump the range of instructions from B to E with their slot indexes.
1009 static void dumpMachineInstrRangeWithSlotIndex(MachineBasicBlock::iterator B,
1010 MachineBasicBlock::iterator E,
1011 LiveIntervals const &LIS,
1012 const char *const header,
1014 char NextLine = '\n';
1015 char SlotIndent = '\t';
1017 if (llvm::next(B) == E) {
1022 dbgs() << '\t' << header << ": " << NextLine;
1024 for (MachineBasicBlock::iterator I = B; I != E; ++I) {
1025 SlotIndex Idx = LIS.getInstructionIndex(I).getRegSlot();
1027 // If a register was passed in and this instruction has it as a
1028 // destination that is marked as an early clobber, print the
1029 // early-clobber slot index.
1031 MachineOperand *MO = I->findRegisterDefOperand(VReg);
1032 if (MO && MO->isEarlyClobber())
1033 Idx = Idx.getRegSlot(true);
1036 dbgs() << SlotIndent << Idx << '\t' << *I;
1041 /// foldMemoryOperand - Try folding stack slot references in Ops into their
1044 /// @param Ops Operand indices from analyzeVirtReg().
1045 /// @param LoadMI Load instruction to use instead of stack slot when non-null.
1046 /// @return True on success.
1047 bool InlineSpiller::
1048 foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> > Ops,
1049 MachineInstr *LoadMI) {
1052 // Don't attempt folding in bundles.
1053 MachineInstr *MI = Ops.front().first;
1054 if (Ops.back().first != MI || MI->isBundled())
1057 bool WasCopy = MI->isCopy();
1058 unsigned ImpReg = 0;
1060 // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
1062 SmallVector<unsigned, 8> FoldOps;
1063 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
1064 unsigned Idx = Ops[i].second;
1065 MachineOperand &MO = MI->getOperand(Idx);
1066 if (MO.isImplicit()) {
1067 ImpReg = MO.getReg();
1070 // FIXME: Teach targets to deal with subregs.
1073 // We cannot fold a load instruction into a def.
1074 if (LoadMI && MO.isDef())
1076 // Tied use operands should not be passed to foldMemoryOperand.
1077 if (!MI->isRegTiedToDefOperand(Idx))
1078 FoldOps.push_back(Idx);
1081 MachineInstrSpan MIS(MI);
1083 MachineInstr *FoldMI =
1084 LoadMI ? TII.foldMemoryOperand(MI, FoldOps, LoadMI)
1085 : TII.foldMemoryOperand(MI, FoldOps, StackSlot);
1089 // Remove LIS for any dead defs in the original MI not in FoldMI.
1090 for (MIBundleOperands MO(MI); MO.isValid(); ++MO) {
1093 unsigned Reg = MO->getReg();
1094 if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) ||
1095 MRI.isReserved(Reg)) {
1098 MIBundleOperands::PhysRegInfo RI =
1099 MIBundleOperands(FoldMI).analyzePhysReg(Reg, &TRI);
1100 if (MO->readsReg()) {
1101 assert(RI.Reads && "Cannot fold physreg reader");
1106 // FoldMI does not define this physreg. Remove the LI segment.
1107 assert(MO->isDead() && "Cannot fold physreg def");
1108 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units) {
1109 if (LiveRange *LR = LIS.getCachedRegUnit(*Units)) {
1110 SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
1111 if (VNInfo *VNI = LR->getVNInfoAt(Idx))
1112 LR->removeValNo(VNI);
1117 LIS.ReplaceMachineInstrInMaps(MI, FoldMI);
1118 MI->eraseFromParent();
1120 // Insert any new instructions other than FoldMI into the LIS maps.
1121 assert(!MIS.empty() && "Unexpected empty span of instructions!");
1122 for (MachineBasicBlock::iterator MII = MIS.begin(), End = MIS.end();
1124 if (&*MII != FoldMI)
1125 LIS.InsertMachineInstrInMaps(&*MII);
1127 // TII.foldMemoryOperand may have left some implicit operands on the
1128 // instruction. Strip them.
1130 for (unsigned i = FoldMI->getNumOperands(); i; --i) {
1131 MachineOperand &MO = FoldMI->getOperand(i - 1);
1132 if (!MO.isReg() || !MO.isImplicit())
1134 if (MO.getReg() == ImpReg)
1135 FoldMI->RemoveOperand(i - 1);
1138 DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MIS.end(), LIS,
1143 else if (Ops.front().second == 0)
1150 void InlineSpiller::insertReload(unsigned NewVReg,
1152 MachineBasicBlock::iterator MI) {
1153 MachineBasicBlock &MBB = *MI->getParent();
1155 MachineInstrSpan MIS(MI);
1156 TII.loadRegFromStackSlot(MBB, MI, NewVReg, StackSlot,
1157 MRI.getRegClass(NewVReg), &TRI);
1159 LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MI);
1161 DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MI, LIS, "reload",
1166 /// insertSpill - Insert a spill of NewVReg after MI.
1167 void InlineSpiller::insertSpill(unsigned NewVReg, bool isKill,
1168 MachineBasicBlock::iterator MI) {
1169 MachineBasicBlock &MBB = *MI->getParent();
1171 MachineInstrSpan MIS(MI);
1172 TII.storeRegToStackSlot(MBB, llvm::next(MI), NewVReg, isKill, StackSlot,
1173 MRI.getRegClass(NewVReg), &TRI);
1175 LIS.InsertMachineInstrRangeInMaps(llvm::next(MI), MIS.end());
1177 DEBUG(dumpMachineInstrRangeWithSlotIndex(llvm::next(MI), MIS.end(), LIS,
1182 /// spillAroundUses - insert spill code around each use of Reg.
1183 void InlineSpiller::spillAroundUses(unsigned Reg) {
1184 DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n');
1185 LiveInterval &OldLI = LIS.getInterval(Reg);
1187 // Iterate over instructions using Reg.
1188 for (MachineRegisterInfo::reg_iterator RegI = MRI.reg_begin(Reg);
1189 MachineInstr *MI = RegI.skipBundle();) {
1191 // Debug values are not allowed to affect codegen.
1192 if (MI->isDebugValue()) {
1193 // Modify DBG_VALUE now that the value is in a spill slot.
1194 bool IsIndirect = MI->isIndirectDebugValue();
1195 uint64_t Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
1196 const MDNode *MDPtr = MI->getOperand(2).getMetadata();
1197 DebugLoc DL = MI->getDebugLoc();
1198 DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
1199 MachineBasicBlock *MBB = MI->getParent();
1200 BuildMI(*MBB, MBB->erase(MI), DL, TII.get(TargetOpcode::DBG_VALUE))
1201 .addFrameIndex(StackSlot).addImm(Offset).addMetadata(MDPtr);
1205 // Ignore copies to/from snippets. We'll delete them.
1206 if (SnippetCopies.count(MI))
1209 // Stack slot accesses may coalesce away.
1210 if (coalesceStackAccess(MI, Reg))
1213 // Analyze instruction.
1214 SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops;
1215 MIBundleOperands::VirtRegInfo RI =
1216 MIBundleOperands(MI).analyzeVirtReg(Reg, &Ops);
1218 // Find the slot index where this instruction reads and writes OldLI.
1219 // This is usually the def slot, except for tied early clobbers.
1220 SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
1221 if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getRegSlot(true)))
1222 if (SlotIndex::isSameInstr(Idx, VNI->def))
1225 // Check for a sibling copy.
1226 unsigned SibReg = isFullCopyOf(MI, Reg);
1227 if (SibReg && isSibling(SibReg)) {
1228 // This may actually be a copy between snippets.
1229 if (isRegToSpill(SibReg)) {
1230 DEBUG(dbgs() << "Found new snippet copy: " << *MI);
1231 SnippetCopies.insert(MI);
1235 // Hoist the spill of a sib-reg copy.
1236 if (hoistSpill(OldLI, MI)) {
1237 // This COPY is now dead, the value is already in the stack slot.
1238 MI->getOperand(0).setIsDead();
1239 DeadDefs.push_back(MI);
1243 // This is a reload for a sib-reg copy. Drop spills downstream.
1244 LiveInterval &SibLI = LIS.getInterval(SibReg);
1245 eliminateRedundantSpills(SibLI, SibLI.getVNInfoAt(Idx));
1246 // The COPY will fold to a reload below.
1250 // Attempt to fold memory ops.
1251 if (foldMemoryOperand(Ops))
1254 // Create a new virtual register for spill/fill.
1255 // FIXME: Infer regclass from instruction alone.
1256 unsigned NewVReg = Edit->createFrom(Reg);
1259 insertReload(NewVReg, Idx, MI);
1261 // Rewrite instruction operands.
1262 bool hasLiveDef = false;
1263 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
1264 MachineOperand &MO = Ops[i].first->getOperand(Ops[i].second);
1267 if (!Ops[i].first->isRegTiedToDefOperand(Ops[i].second))
1274 DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI << '\n');
1276 // FIXME: Use a second vreg if instruction has no tied ops.
1279 insertSpill(NewVReg, true, MI);
1283 /// spillAll - Spill all registers remaining after rematerialization.
1284 void InlineSpiller::spillAll() {
1285 // Update LiveStacks now that we are committed to spilling.
1286 if (StackSlot == VirtRegMap::NO_STACK_SLOT) {
1287 StackSlot = VRM.assignVirt2StackSlot(Original);
1288 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original));
1289 StackInt->getNextValue(SlotIndex(), LSS.getVNInfoAllocator());
1291 StackInt = &LSS.getInterval(StackSlot);
1293 if (Original != Edit->getReg())
1294 VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot);
1296 assert(StackInt->getNumValNums() == 1 && "Bad stack interval values");
1297 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
1298 StackInt->MergeSegmentsInAsValue(LIS.getInterval(RegsToSpill[i]),
1299 StackInt->getValNumInfo(0));
1300 DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n');
1302 // Spill around uses of all RegsToSpill.
1303 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
1304 spillAroundUses(RegsToSpill[i]);
1306 // Hoisted spills may cause dead code.
1307 if (!DeadDefs.empty()) {
1308 DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n");
1309 Edit->eliminateDeadDefs(DeadDefs, RegsToSpill);
1312 // Finally delete the SnippetCopies.
1313 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
1314 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(RegsToSpill[i]);
1315 MachineInstr *MI = RI.skipInstruction();) {
1316 assert(SnippetCopies.count(MI) && "Remaining use wasn't a snippet copy");
1317 // FIXME: Do this with a LiveRangeEdit callback.
1318 LIS.RemoveMachineInstrFromMaps(MI);
1319 MI->eraseFromParent();
1323 // Delete all spilled registers.
1324 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
1325 Edit->eraseVirtReg(RegsToSpill[i]);
1328 void InlineSpiller::spill(LiveRangeEdit &edit) {
1331 assert(!TargetRegisterInfo::isStackSlot(edit.getReg())
1332 && "Trying to spill a stack slot.");
1333 // Share a stack slot among all descendants of Original.
1334 Original = VRM.getOriginal(edit.getReg());
1335 StackSlot = VRM.getStackSlot(Original);
1338 DEBUG(dbgs() << "Inline spilling "
1339 << MRI.getRegClass(edit.getReg())->getName()
1340 << ':' << PrintReg(edit.getReg()) << ' ' << edit.getParent()
1341 << "\nFrom original " << PrintReg(Original) << '\n');
1342 assert(edit.getParent().isSpillable() &&
1343 "Attempting to spill already spilled value.");
1344 assert(DeadDefs.empty() && "Previous spill didn't remove dead defs");
1346 collectRegsToSpill();
1347 analyzeSiblingValues();
1350 // Remat may handle everything.
1351 if (!RegsToSpill.empty())
1354 Edit->calculateRegClassAndHint(MF, Loops, MBFI);