1 //===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The inline spiller modifies the machine function directly instead of
11 // inserting spills and restores in VirtRegMap.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
17 #include "llvm/ADT/SetVector.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/ADT/TinyPtrVector.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/LiveRangeEdit.h"
23 #include "llvm/CodeGen/LiveStackAnalysis.h"
24 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineInstrBundle.h"
30 #include "llvm/CodeGen/MachineLoopInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/VirtRegMap.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
41 STATISTIC(NumSpilledRanges, "Number of spilled live ranges");
42 STATISTIC(NumSnippets, "Number of spilled snippets");
43 STATISTIC(NumSpills, "Number of spills inserted");
44 STATISTIC(NumSpillsRemoved, "Number of spills removed");
45 STATISTIC(NumReloads, "Number of reloads inserted");
46 STATISTIC(NumReloadsRemoved, "Number of reloads removed");
47 STATISTIC(NumFolded, "Number of folded stack accesses");
48 STATISTIC(NumFoldedLoads, "Number of folded loads");
49 STATISTIC(NumRemats, "Number of rematerialized defs for spilling");
50 STATISTIC(NumOmitReloadSpill, "Number of omitted spills of reloads");
51 STATISTIC(NumHoists, "Number of hoisted spills");
53 static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden,
54 cl::desc("Disable inline spill hoisting"));
57 class InlineSpiller : public Spiller {
62 MachineDominatorTree &MDT;
63 MachineLoopInfo &Loops;
65 MachineFrameInfo &MFI;
66 MachineRegisterInfo &MRI;
67 const TargetInstrInfo &TII;
68 const TargetRegisterInfo &TRI;
69 const MachineBlockFrequencyInfo &MBFI;
71 // Variables that are valid during spill(), but used by multiple methods.
73 LiveInterval *StackInt;
77 // All registers to spill to StackSlot, including the main register.
78 SmallVector<unsigned, 8> RegsToSpill;
80 // All COPY instructions to/from snippets.
81 // They are ignored since both operands refer to the same stack slot.
82 SmallPtrSet<MachineInstr*, 8> SnippetCopies;
84 // Values that failed to remat at some point.
85 SmallPtrSet<VNInfo*, 8> UsedValues;
88 // Information about a value that was defined by a copy from a sibling
91 // True when all reaching defs were reloads: No spill is necessary.
92 bool AllDefsAreReloads;
94 // True when value is defined by an original PHI not from splitting.
97 // True when the COPY defining this value killed its source.
100 // The preferred register to spill.
103 // The value of SpillReg that should be spilled.
106 // The block where SpillVNI should be spilled. Currently, this must be the
107 // block containing SpillVNI->def.
108 MachineBasicBlock *SpillMBB;
110 // A defining instruction that is not a sibling copy or a reload, or NULL.
111 // This can be used as a template for rematerialization.
114 // List of values that depend on this one. These values are actually the
115 // same, but live range splitting has placed them in different registers,
116 // or SSA update needed to insert PHI-defs to preserve SSA form. This is
117 // copies of the current value and phi-kills. Usually only phi-kills cause
118 // more than one dependent value.
119 TinyPtrVector<VNInfo*> Deps;
121 SibValueInfo(unsigned Reg, VNInfo *VNI)
122 : AllDefsAreReloads(true), DefByOrigPHI(false), KillsSource(false),
123 SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {}
125 // Returns true when a def has been found.
126 bool hasDef() const { return DefByOrigPHI || DefMI; }
130 // Values in RegsToSpill defined by sibling copies.
131 typedef DenseMap<VNInfo*, SibValueInfo> SibValueMap;
132 SibValueMap SibValues;
134 // Dead defs generated during spilling.
135 SmallVector<MachineInstr*, 8> DeadDefs;
140 InlineSpiller(MachineFunctionPass &pass,
144 LIS(pass.getAnalysis<LiveIntervals>()),
145 LSS(pass.getAnalysis<LiveStacks>()),
146 AA(&pass.getAnalysis<AliasAnalysis>()),
147 MDT(pass.getAnalysis<MachineDominatorTree>()),
148 Loops(pass.getAnalysis<MachineLoopInfo>()),
150 MFI(*mf.getFrameInfo()),
151 MRI(mf.getRegInfo()),
152 TII(*mf.getTarget().getInstrInfo()),
153 TRI(*mf.getTarget().getRegisterInfo()),
154 MBFI(pass.getAnalysis<MachineBlockFrequencyInfo>()) {}
156 void spill(LiveRangeEdit &) override;
159 bool isSnippet(const LiveInterval &SnipLI);
160 void collectRegsToSpill();
162 bool isRegToSpill(unsigned Reg) {
163 return std::find(RegsToSpill.begin(),
164 RegsToSpill.end(), Reg) != RegsToSpill.end();
167 bool isSibling(unsigned Reg);
168 MachineInstr *traceSiblingValue(unsigned, VNInfo*, VNInfo*);
169 void propagateSiblingValue(SibValueMap::iterator, VNInfo *VNI = 0);
170 void analyzeSiblingValues();
172 bool hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI);
173 void eliminateRedundantSpills(LiveInterval &LI, VNInfo *VNI);
175 void markValueUsed(LiveInterval*, VNInfo*);
176 bool reMaterializeFor(LiveInterval&, MachineBasicBlock::iterator MI);
177 void reMaterializeAll();
179 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
180 bool foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> >,
181 MachineInstr *LoadMI = 0);
182 void insertReload(unsigned VReg, SlotIndex, MachineBasicBlock::iterator MI);
183 void insertSpill(unsigned VReg, bool isKill, MachineBasicBlock::iterator MI);
185 void spillAroundUses(unsigned Reg);
191 Spiller *createInlineSpiller(MachineFunctionPass &pass,
194 return new InlineSpiller(pass, mf, vrm);
198 //===----------------------------------------------------------------------===//
200 //===----------------------------------------------------------------------===//
202 // When spilling a virtual register, we also spill any snippets it is connected
203 // to. The snippets are small live ranges that only have a single real use,
204 // leftovers from live range splitting. Spilling them enables memory operand
205 // folding or tightens the live range around the single use.
207 // This minimizes register pressure and maximizes the store-to-load distance for
208 // spill slots which can be important in tight loops.
210 /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
211 /// otherwise return 0.
212 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) {
213 if (!MI->isFullCopy())
215 if (MI->getOperand(0).getReg() == Reg)
216 return MI->getOperand(1).getReg();
217 if (MI->getOperand(1).getReg() == Reg)
218 return MI->getOperand(0).getReg();
222 /// isSnippet - Identify if a live interval is a snippet that should be spilled.
223 /// It is assumed that SnipLI is a virtual register with the same original as
225 bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
226 unsigned Reg = Edit->getReg();
228 // A snippet is a tiny live range with only a single instruction using it
229 // besides copies to/from Reg or spills/fills. We accept:
231 // %snip = COPY %Reg / FILL fi#
233 // %Reg = COPY %snip / SPILL %snip, fi#
235 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
238 MachineInstr *UseMI = 0;
240 // Check that all uses satisfy our criteria.
241 for (MachineRegisterInfo::reg_instr_nodbg_iterator
242 RI = MRI.reg_instr_nodbg_begin(SnipLI.reg),
243 E = MRI.reg_instr_nodbg_end(); RI != E; ) {
244 MachineInstr *MI = &*(RI++);
246 // Allow copies to/from Reg.
247 if (isFullCopyOf(MI, Reg))
250 // Allow stack slot loads.
252 if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot)
255 // Allow stack slot stores.
256 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
259 // Allow a single additional instruction.
260 if (UseMI && MI != UseMI)
267 /// collectRegsToSpill - Collect live range snippets that only have a single
269 void InlineSpiller::collectRegsToSpill() {
270 unsigned Reg = Edit->getReg();
272 // Main register always spills.
273 RegsToSpill.assign(1, Reg);
274 SnippetCopies.clear();
276 // Snippets all have the same original, so there can't be any for an original
281 for (MachineRegisterInfo::reg_instr_iterator
282 RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end(); RI != E; ) {
283 MachineInstr *MI = &*(RI++);
284 unsigned SnipReg = isFullCopyOf(MI, Reg);
285 if (!isSibling(SnipReg))
287 LiveInterval &SnipLI = LIS.getInterval(SnipReg);
288 if (!isSnippet(SnipLI))
290 SnippetCopies.insert(MI);
291 if (isRegToSpill(SnipReg))
293 RegsToSpill.push_back(SnipReg);
294 DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n');
300 //===----------------------------------------------------------------------===//
302 //===----------------------------------------------------------------------===//
304 // After live range splitting, some values to be spilled may be defined by
305 // copies from sibling registers. We trace the sibling copies back to the
306 // original value if it still exists. We need it for rematerialization.
308 // Even when the value can't be rematerialized, we still want to determine if
309 // the value has already been spilled, or we may want to hoist the spill from a
312 bool InlineSpiller::isSibling(unsigned Reg) {
313 return TargetRegisterInfo::isVirtualRegister(Reg) &&
314 VRM.getOriginal(Reg) == Original;
318 static raw_ostream &operator<<(raw_ostream &OS,
319 const InlineSpiller::SibValueInfo &SVI) {
320 OS << "spill " << PrintReg(SVI.SpillReg) << ':'
321 << SVI.SpillVNI->id << '@' << SVI.SpillVNI->def;
323 OS << " in BB#" << SVI.SpillMBB->getNumber();
324 if (SVI.AllDefsAreReloads)
325 OS << " all-reloads";
326 if (SVI.DefByOrigPHI)
331 for (unsigned i = 0, e = SVI.Deps.size(); i != e; ++i)
332 OS << ' ' << SVI.Deps[i]->id << '@' << SVI.Deps[i]->def;
335 OS << " def: " << *SVI.DefMI;
342 /// propagateSiblingValue - Propagate the value in SVI to dependents if it is
343 /// known. Otherwise remember the dependency for later.
345 /// @param SVIIter SibValues entry to propagate.
346 /// @param VNI Dependent value, or NULL to propagate to all saved dependents.
347 void InlineSpiller::propagateSiblingValue(SibValueMap::iterator SVIIter,
349 SibValueMap::value_type *SVI = &*SVIIter;
351 // When VNI is non-NULL, add it to SVI's deps, and only propagate to that.
352 TinyPtrVector<VNInfo*> FirstDeps;
354 FirstDeps.push_back(VNI);
355 SVI->second.Deps.push_back(VNI);
358 // Has the value been completely determined yet? If not, defer propagation.
359 if (!SVI->second.hasDef())
362 // Work list of values to propagate.
363 SmallSetVector<SibValueMap::value_type *, 8> WorkList;
364 WorkList.insert(SVI);
367 SVI = WorkList.pop_back_val();
368 TinyPtrVector<VNInfo*> *Deps = VNI ? &FirstDeps : &SVI->second.Deps;
371 SibValueInfo &SV = SVI->second;
373 SV.SpillMBB = LIS.getMBBFromIndex(SV.SpillVNI->def);
375 DEBUG(dbgs() << " prop to " << Deps->size() << ": "
376 << SVI->first->id << '@' << SVI->first->def << ":\t" << SV);
378 assert(SV.hasDef() && "Propagating undefined value");
380 // Should this value be propagated as a preferred spill candidate? We don't
381 // propagate values of registers that are about to spill.
382 bool PropSpill = !DisableHoisting && !isRegToSpill(SV.SpillReg);
383 unsigned SpillDepth = ~0u;
385 for (TinyPtrVector<VNInfo*>::iterator DepI = Deps->begin(),
386 DepE = Deps->end(); DepI != DepE; ++DepI) {
387 SibValueMap::iterator DepSVI = SibValues.find(*DepI);
388 assert(DepSVI != SibValues.end() && "Dependent value not in SibValues");
389 SibValueInfo &DepSV = DepSVI->second;
391 DepSV.SpillMBB = LIS.getMBBFromIndex(DepSV.SpillVNI->def);
393 bool Changed = false;
395 // Propagate defining instruction.
396 if (!DepSV.hasDef()) {
398 DepSV.DefMI = SV.DefMI;
399 DepSV.DefByOrigPHI = SV.DefByOrigPHI;
402 // Propagate AllDefsAreReloads. For PHI values, this computes an AND of
404 if (!SV.AllDefsAreReloads && DepSV.AllDefsAreReloads) {
406 DepSV.AllDefsAreReloads = false;
409 // Propagate best spill value.
410 if (PropSpill && SV.SpillVNI != DepSV.SpillVNI) {
411 if (SV.SpillMBB == DepSV.SpillMBB) {
412 // DepSV is in the same block. Hoist when dominated.
413 if (DepSV.KillsSource && SV.SpillVNI->def < DepSV.SpillVNI->def) {
414 // This is an alternative def earlier in the same MBB.
415 // Hoist the spill as far as possible in SpillMBB. This can ease
416 // register pressure:
422 // Hoisting the spill of s to immediately after the def removes the
423 // interference between x and y:
429 // This hoist only helps when the DepSV copy kills its source.
431 DepSV.SpillReg = SV.SpillReg;
432 DepSV.SpillVNI = SV.SpillVNI;
433 DepSV.SpillMBB = SV.SpillMBB;
436 // DepSV is in a different block.
437 if (SpillDepth == ~0u)
438 SpillDepth = Loops.getLoopDepth(SV.SpillMBB);
440 // Also hoist spills to blocks with smaller loop depth, but make sure
441 // that the new value dominates. Non-phi dependents are always
442 // dominated, phis need checking.
443 if ((Loops.getLoopDepth(DepSV.SpillMBB) > SpillDepth) &&
444 (!DepSVI->first->isPHIDef() ||
445 MDT.dominates(SV.SpillMBB, DepSV.SpillMBB))) {
447 DepSV.SpillReg = SV.SpillReg;
448 DepSV.SpillVNI = SV.SpillVNI;
449 DepSV.SpillMBB = SV.SpillMBB;
457 // Something changed in DepSVI. Propagate to dependents.
458 WorkList.insert(&*DepSVI);
460 DEBUG(dbgs() << " update " << DepSVI->first->id << '@'
461 << DepSVI->first->def << " to:\t" << DepSV);
463 } while (!WorkList.empty());
466 /// traceSiblingValue - Trace a value that is about to be spilled back to the
467 /// real defining instructions by looking through sibling copies. Always stay
468 /// within the range of OrigVNI so the registers are known to carry the same
471 /// Determine if the value is defined by all reloads, so spilling isn't
472 /// necessary - the value is already in the stack slot.
474 /// Return a defining instruction that may be a candidate for rematerialization.
476 MachineInstr *InlineSpiller::traceSiblingValue(unsigned UseReg, VNInfo *UseVNI,
478 // Check if a cached value already exists.
479 SibValueMap::iterator SVI;
481 std::tie(SVI, Inserted) =
482 SibValues.insert(std::make_pair(UseVNI, SibValueInfo(UseReg, UseVNI)));
484 DEBUG(dbgs() << "Cached value " << PrintReg(UseReg) << ':'
485 << UseVNI->id << '@' << UseVNI->def << ' ' << SVI->second);
486 return SVI->second.DefMI;
489 DEBUG(dbgs() << "Tracing value " << PrintReg(UseReg) << ':'
490 << UseVNI->id << '@' << UseVNI->def << '\n');
492 // List of (Reg, VNI) that have been inserted into SibValues, but need to be
494 SmallVector<std::pair<unsigned, VNInfo*>, 8> WorkList;
495 WorkList.push_back(std::make_pair(UseReg, UseVNI));
500 std::tie(Reg, VNI) = WorkList.pop_back_val();
501 DEBUG(dbgs() << " " << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def
504 // First check if this value has already been computed.
505 SVI = SibValues.find(VNI);
506 assert(SVI != SibValues.end() && "Missing SibValues entry");
508 // Trace through PHI-defs created by live range splitting.
509 if (VNI->isPHIDef()) {
510 // Stop at original PHIs. We don't know the value at the predecessors.
511 if (VNI->def == OrigVNI->def) {
512 DEBUG(dbgs() << "orig phi value\n");
513 SVI->second.DefByOrigPHI = true;
514 SVI->second.AllDefsAreReloads = false;
515 propagateSiblingValue(SVI);
519 // This is a PHI inserted by live range splitting. We could trace the
520 // live-out value from predecessor blocks, but that search can be very
521 // expensive if there are many predecessors and many more PHIs as
522 // generated by tail-dup when it sees an indirectbr. Instead, look at
523 // all the non-PHI defs that have the same value as OrigVNI. They must
524 // jointly dominate VNI->def. This is not optimal since VNI may actually
525 // be jointly dominated by a smaller subset of defs, so there is a change
526 // we will miss a AllDefsAreReloads optimization.
528 // Separate all values dominated by OrigVNI into PHIs and non-PHIs.
529 SmallVector<VNInfo*, 8> PHIs, NonPHIs;
530 LiveInterval &LI = LIS.getInterval(Reg);
531 LiveInterval &OrigLI = LIS.getInterval(Original);
533 for (LiveInterval::vni_iterator VI = LI.vni_begin(), VE = LI.vni_end();
536 if (VNI2->isUnused())
538 if (!OrigLI.containsOneValue() &&
539 OrigLI.getVNInfoAt(VNI2->def) != OrigVNI)
541 if (VNI2->isPHIDef() && VNI2->def != OrigVNI->def)
542 PHIs.push_back(VNI2);
544 NonPHIs.push_back(VNI2);
546 DEBUG(dbgs() << "split phi value, checking " << PHIs.size()
547 << " phi-defs, and " << NonPHIs.size()
548 << " non-phi/orig defs\n");
550 // Create entries for all the PHIs. Don't add them to the worklist, we
551 // are processing all of them in one go here.
552 for (unsigned i = 0, e = PHIs.size(); i != e; ++i)
553 SibValues.insert(std::make_pair(PHIs[i], SibValueInfo(Reg, PHIs[i])));
555 // Add every PHI as a dependent of all the non-PHIs.
556 for (unsigned i = 0, e = NonPHIs.size(); i != e; ++i) {
557 VNInfo *NonPHI = NonPHIs[i];
558 // Known value? Try an insertion.
559 std::tie(SVI, Inserted) =
560 SibValues.insert(std::make_pair(NonPHI, SibValueInfo(Reg, NonPHI)));
561 // Add all the PHIs as dependents of NonPHI.
562 for (unsigned pi = 0, pe = PHIs.size(); pi != pe; ++pi)
563 SVI->second.Deps.push_back(PHIs[pi]);
564 // This is the first time we see NonPHI, add it to the worklist.
566 WorkList.push_back(std::make_pair(Reg, NonPHI));
568 // Propagate to all inserted PHIs, not just VNI.
569 propagateSiblingValue(SVI);
572 // Next work list item.
576 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
577 assert(MI && "Missing def");
579 // Trace through sibling copies.
580 if (unsigned SrcReg = isFullCopyOf(MI, Reg)) {
581 if (isSibling(SrcReg)) {
582 LiveInterval &SrcLI = LIS.getInterval(SrcReg);
583 LiveQueryResult SrcQ = SrcLI.Query(VNI->def);
584 assert(SrcQ.valueIn() && "Copy from non-existing value");
585 // Check if this COPY kills its source.
586 SVI->second.KillsSource = SrcQ.isKill();
587 VNInfo *SrcVNI = SrcQ.valueIn();
588 DEBUG(dbgs() << "copy of " << PrintReg(SrcReg) << ':'
589 << SrcVNI->id << '@' << SrcVNI->def
590 << " kill=" << unsigned(SVI->second.KillsSource) << '\n');
591 // Known sibling source value? Try an insertion.
592 std::tie(SVI, Inserted) = SibValues.insert(
593 std::make_pair(SrcVNI, SibValueInfo(SrcReg, SrcVNI)));
594 // This is the first time we see Src, add it to the worklist.
596 WorkList.push_back(std::make_pair(SrcReg, SrcVNI));
597 propagateSiblingValue(SVI, VNI);
598 // Next work list item.
603 // Track reachable reloads.
604 SVI->second.DefMI = MI;
605 SVI->second.SpillMBB = MI->getParent();
607 if (Reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) {
608 DEBUG(dbgs() << "reload\n");
609 propagateSiblingValue(SVI);
610 // Next work list item.
614 // Potential remat candidate.
615 DEBUG(dbgs() << "def " << *MI);
616 SVI->second.AllDefsAreReloads = false;
617 propagateSiblingValue(SVI);
618 } while (!WorkList.empty());
620 // Look up the value we were looking for. We already did this lookup at the
621 // top of the function, but SibValues may have been invalidated.
622 SVI = SibValues.find(UseVNI);
623 assert(SVI != SibValues.end() && "Didn't compute requested info");
624 DEBUG(dbgs() << " traced to:\t" << SVI->second);
625 return SVI->second.DefMI;
628 /// analyzeSiblingValues - Trace values defined by sibling copies back to
629 /// something that isn't a sibling copy.
631 /// Keep track of values that may be rematerializable.
632 void InlineSpiller::analyzeSiblingValues() {
635 // No siblings at all?
636 if (Edit->getReg() == Original)
639 LiveInterval &OrigLI = LIS.getInterval(Original);
640 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
641 unsigned Reg = RegsToSpill[i];
642 LiveInterval &LI = LIS.getInterval(Reg);
643 for (LiveInterval::const_vni_iterator VI = LI.vni_begin(),
644 VE = LI.vni_end(); VI != VE; ++VI) {
648 MachineInstr *DefMI = 0;
649 if (!VNI->isPHIDef()) {
650 DefMI = LIS.getInstructionFromIndex(VNI->def);
651 assert(DefMI && "No defining instruction");
653 // Check possible sibling copies.
654 if (VNI->isPHIDef() || DefMI->isCopy()) {
655 VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
656 assert(OrigVNI && "Def outside original live range");
657 if (OrigVNI->def != VNI->def)
658 DefMI = traceSiblingValue(Reg, VNI, OrigVNI);
660 if (DefMI && Edit->checkRematerializable(VNI, DefMI, AA)) {
661 DEBUG(dbgs() << "Value " << PrintReg(Reg) << ':' << VNI->id << '@'
662 << VNI->def << " may remat from " << *DefMI);
668 /// hoistSpill - Given a sibling copy that defines a value to be spilled, insert
669 /// a spill at a better location.
670 bool InlineSpiller::hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI) {
671 SlotIndex Idx = LIS.getInstructionIndex(CopyMI);
672 VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getRegSlot());
673 assert(VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy");
674 SibValueMap::iterator I = SibValues.find(VNI);
675 if (I == SibValues.end())
678 const SibValueInfo &SVI = I->second;
680 // Let the normal folding code deal with the boring case.
681 if (!SVI.AllDefsAreReloads && SVI.SpillVNI == VNI)
684 // SpillReg may have been deleted by remat and DCE.
685 if (!LIS.hasInterval(SVI.SpillReg)) {
686 DEBUG(dbgs() << "Stale interval: " << PrintReg(SVI.SpillReg) << '\n');
691 LiveInterval &SibLI = LIS.getInterval(SVI.SpillReg);
692 if (!SibLI.containsValue(SVI.SpillVNI)) {
693 DEBUG(dbgs() << "Stale value: " << PrintReg(SVI.SpillReg) << '\n');
698 // Conservatively extend the stack slot range to the range of the original
699 // value. We may be able to do better with stack slot coloring by being more
701 assert(StackInt && "No stack slot assigned yet.");
702 LiveInterval &OrigLI = LIS.getInterval(Original);
703 VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
704 StackInt->MergeValueInAsValue(OrigLI, OrigVNI, StackInt->getValNumInfo(0));
705 DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": "
706 << *StackInt << '\n');
708 // Already spilled everywhere.
709 if (SVI.AllDefsAreReloads) {
710 DEBUG(dbgs() << "\tno spill needed: " << SVI);
711 ++NumOmitReloadSpill;
714 // We are going to spill SVI.SpillVNI immediately after its def, so clear out
715 // any later spills of the same value.
716 eliminateRedundantSpills(SibLI, SVI.SpillVNI);
718 MachineBasicBlock *MBB = LIS.getMBBFromIndex(SVI.SpillVNI->def);
719 MachineBasicBlock::iterator MII;
720 if (SVI.SpillVNI->isPHIDef())
721 MII = MBB->SkipPHIsAndLabels(MBB->begin());
723 MachineInstr *DefMI = LIS.getInstructionFromIndex(SVI.SpillVNI->def);
724 assert(DefMI && "Defining instruction disappeared");
728 // Insert spill without kill flag immediately after def.
729 TII.storeRegToStackSlot(*MBB, MII, SVI.SpillReg, false, StackSlot,
730 MRI.getRegClass(SVI.SpillReg), &TRI);
731 --MII; // Point to store instruction.
732 LIS.InsertMachineInstrInMaps(MII);
733 DEBUG(dbgs() << "\thoisted: " << SVI.SpillVNI->def << '\t' << *MII);
740 /// eliminateRedundantSpills - SLI:VNI is known to be on the stack. Remove any
741 /// redundant spills of this value in SLI.reg and sibling copies.
742 void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
743 assert(VNI && "Missing value");
744 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
745 WorkList.push_back(std::make_pair(&SLI, VNI));
746 assert(StackInt && "No stack slot assigned yet.");
750 std::tie(LI, VNI) = WorkList.pop_back_val();
751 unsigned Reg = LI->reg;
752 DEBUG(dbgs() << "Checking redundant spills for "
753 << VNI->id << '@' << VNI->def << " in " << *LI << '\n');
755 // Regs to spill are taken care of.
756 if (isRegToSpill(Reg))
759 // Add all of VNI's live range to StackInt.
760 StackInt->MergeValueInAsValue(*LI, VNI, StackInt->getValNumInfo(0));
761 DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n');
763 // Find all spills and copies of VNI.
764 for (MachineRegisterInfo::use_instr_nodbg_iterator
765 UI = MRI.use_instr_nodbg_begin(Reg), E = MRI.use_instr_nodbg_end();
767 MachineInstr *MI = &*(UI++);
768 if (!MI->isCopy() && !MI->mayStore())
770 SlotIndex Idx = LIS.getInstructionIndex(MI);
771 if (LI->getVNInfoAt(Idx) != VNI)
774 // Follow sibling copies down the dominator tree.
775 if (unsigned DstReg = isFullCopyOf(MI, Reg)) {
776 if (isSibling(DstReg)) {
777 LiveInterval &DstLI = LIS.getInterval(DstReg);
778 VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getRegSlot());
779 assert(DstVNI && "Missing defined value");
780 assert(DstVNI->def == Idx.getRegSlot() && "Wrong copy def slot");
781 WorkList.push_back(std::make_pair(&DstLI, DstVNI));
788 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
789 DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << *MI);
790 // eliminateDeadDefs won't normally remove stores, so switch opcode.
791 MI->setDesc(TII.get(TargetOpcode::KILL));
792 DeadDefs.push_back(MI);
797 } while (!WorkList.empty());
801 //===----------------------------------------------------------------------===//
803 //===----------------------------------------------------------------------===//
805 /// markValueUsed - Remember that VNI failed to rematerialize, so its defining
806 /// instruction cannot be eliminated. See through snippet copies
807 void InlineSpiller::markValueUsed(LiveInterval *LI, VNInfo *VNI) {
808 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
809 WorkList.push_back(std::make_pair(LI, VNI));
811 std::tie(LI, VNI) = WorkList.pop_back_val();
812 if (!UsedValues.insert(VNI))
815 if (VNI->isPHIDef()) {
816 MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
817 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
818 PE = MBB->pred_end(); PI != PE; ++PI) {
819 VNInfo *PVNI = LI->getVNInfoBefore(LIS.getMBBEndIdx(*PI));
821 WorkList.push_back(std::make_pair(LI, PVNI));
826 // Follow snippet copies.
827 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
828 if (!SnippetCopies.count(MI))
830 LiveInterval &SnipLI = LIS.getInterval(MI->getOperand(1).getReg());
831 assert(isRegToSpill(SnipLI.reg) && "Unexpected register in copy");
832 VNInfo *SnipVNI = SnipLI.getVNInfoAt(VNI->def.getRegSlot(true));
833 assert(SnipVNI && "Snippet undefined before copy");
834 WorkList.push_back(std::make_pair(&SnipLI, SnipVNI));
835 } while (!WorkList.empty());
838 /// reMaterializeFor - Attempt to rematerialize before MI instead of reloading.
839 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg,
840 MachineBasicBlock::iterator MI) {
841 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
842 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
845 DEBUG(dbgs() << "\tadding <undef> flags: ");
846 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
847 MachineOperand &MO = MI->getOperand(i);
848 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
851 DEBUG(dbgs() << UseIdx << '\t' << *MI);
855 if (SnippetCopies.count(MI))
858 // Use an OrigVNI from traceSiblingValue when ParentVNI is a sibling copy.
859 LiveRangeEdit::Remat RM(ParentVNI);
860 SibValueMap::const_iterator SibI = SibValues.find(ParentVNI);
861 if (SibI != SibValues.end())
862 RM.OrigMI = SibI->second.DefMI;
863 if (!Edit->canRematerializeAt(RM, UseIdx, false)) {
864 markValueUsed(&VirtReg, ParentVNI);
865 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
869 // If the instruction also writes VirtReg.reg, it had better not require the
870 // same register for uses and defs.
871 SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops;
872 MIBundleOperands::VirtRegInfo RI =
873 MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops);
875 markValueUsed(&VirtReg, ParentVNI);
876 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
880 // Before rematerializing into a register for a single instruction, try to
881 // fold a load into the instruction. That avoids allocating a new register.
882 if (RM.OrigMI->canFoldAsLoad() &&
883 foldMemoryOperand(Ops, RM.OrigMI)) {
884 Edit->markRematerialized(RM.ParentVNI);
889 // Alocate a new register for the remat.
890 unsigned NewVReg = Edit->createFrom(Original);
892 // Finally we can rematerialize OrigMI before MI.
893 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewVReg, RM,
896 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'
897 << *LIS.getInstructionFromIndex(DefIdx));
900 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
901 MachineOperand &MO = MI->getOperand(Ops[i].second);
902 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
907 DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI << '\n');
913 /// reMaterializeAll - Try to rematerialize as many uses as possible,
914 /// and trim the live ranges after.
915 void InlineSpiller::reMaterializeAll() {
916 // analyzeSiblingValues has already tested all relevant defining instructions.
917 if (!Edit->anyRematerializable(AA))
922 // Try to remat before all uses of snippets.
923 bool anyRemat = false;
924 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
925 unsigned Reg = RegsToSpill[i];
926 LiveInterval &LI = LIS.getInterval(Reg);
927 for (MachineRegisterInfo::use_bundle_nodbg_iterator
928 RI = MRI.use_bundle_nodbg_begin(Reg), E = MRI.use_bundle_nodbg_end();
930 MachineInstr *MI = &*(RI++);
931 anyRemat |= reMaterializeFor(LI, MI);
937 // Remove any values that were completely rematted.
938 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
939 unsigned Reg = RegsToSpill[i];
940 LiveInterval &LI = LIS.getInterval(Reg);
941 for (LiveInterval::vni_iterator I = LI.vni_begin(), E = LI.vni_end();
944 if (VNI->isUnused() || VNI->isPHIDef() || UsedValues.count(VNI))
946 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
947 MI->addRegisterDead(Reg, &TRI);
948 if (!MI->allDefsAreDead())
950 DEBUG(dbgs() << "All defs dead: " << *MI);
951 DeadDefs.push_back(MI);
955 // Eliminate dead code after remat. Note that some snippet copies may be
957 if (DeadDefs.empty())
959 DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n");
960 Edit->eliminateDeadDefs(DeadDefs, RegsToSpill);
962 // Get rid of deleted and empty intervals.
963 unsigned ResultPos = 0;
964 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
965 unsigned Reg = RegsToSpill[i];
966 if (!LIS.hasInterval(Reg))
969 LiveInterval &LI = LIS.getInterval(Reg);
971 Edit->eraseVirtReg(Reg);
975 RegsToSpill[ResultPos++] = Reg;
977 RegsToSpill.erase(RegsToSpill.begin() + ResultPos, RegsToSpill.end());
978 DEBUG(dbgs() << RegsToSpill.size() << " registers to spill after remat.\n");
982 //===----------------------------------------------------------------------===//
984 //===----------------------------------------------------------------------===//
986 /// If MI is a load or store of StackSlot, it can be removed.
987 bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
989 unsigned InstrReg = TII.isLoadFromStackSlot(MI, FI);
990 bool IsLoad = InstrReg;
992 InstrReg = TII.isStoreToStackSlot(MI, FI);
994 // We have a stack access. Is it the right register and slot?
995 if (InstrReg != Reg || FI != StackSlot)
998 DEBUG(dbgs() << "Coalescing stack access: " << *MI);
999 LIS.RemoveMachineInstrFromMaps(MI);
1000 MI->eraseFromParent();
1003 ++NumReloadsRemoved;
1013 #if !defined(NDEBUG)
1014 // Dump the range of instructions from B to E with their slot indexes.
1015 static void dumpMachineInstrRangeWithSlotIndex(MachineBasicBlock::iterator B,
1016 MachineBasicBlock::iterator E,
1017 LiveIntervals const &LIS,
1018 const char *const header,
1020 char NextLine = '\n';
1021 char SlotIndent = '\t';
1023 if (std::next(B) == E) {
1028 dbgs() << '\t' << header << ": " << NextLine;
1030 for (MachineBasicBlock::iterator I = B; I != E; ++I) {
1031 SlotIndex Idx = LIS.getInstructionIndex(I).getRegSlot();
1033 // If a register was passed in and this instruction has it as a
1034 // destination that is marked as an early clobber, print the
1035 // early-clobber slot index.
1037 MachineOperand *MO = I->findRegisterDefOperand(VReg);
1038 if (MO && MO->isEarlyClobber())
1039 Idx = Idx.getRegSlot(true);
1042 dbgs() << SlotIndent << Idx << '\t' << *I;
1047 /// foldMemoryOperand - Try folding stack slot references in Ops into their
1050 /// @param Ops Operand indices from analyzeVirtReg().
1051 /// @param LoadMI Load instruction to use instead of stack slot when non-null.
1052 /// @return True on success.
1053 bool InlineSpiller::
1054 foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> > Ops,
1055 MachineInstr *LoadMI) {
1058 // Don't attempt folding in bundles.
1059 MachineInstr *MI = Ops.front().first;
1060 if (Ops.back().first != MI || MI->isBundled())
1063 bool WasCopy = MI->isCopy();
1064 unsigned ImpReg = 0;
1066 bool SpillSubRegs = (MI->getOpcode() == TargetOpcode::PATCHPOINT ||
1067 MI->getOpcode() == TargetOpcode::STACKMAP);
1069 // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
1071 SmallVector<unsigned, 8> FoldOps;
1072 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
1073 unsigned Idx = Ops[i].second;
1074 MachineOperand &MO = MI->getOperand(Idx);
1075 if (MO.isImplicit()) {
1076 ImpReg = MO.getReg();
1079 // FIXME: Teach targets to deal with subregs.
1080 if (!SpillSubRegs && MO.getSubReg())
1082 // We cannot fold a load instruction into a def.
1083 if (LoadMI && MO.isDef())
1085 // Tied use operands should not be passed to foldMemoryOperand.
1086 if (!MI->isRegTiedToDefOperand(Idx))
1087 FoldOps.push_back(Idx);
1090 MachineInstrSpan MIS(MI);
1092 MachineInstr *FoldMI =
1093 LoadMI ? TII.foldMemoryOperand(MI, FoldOps, LoadMI)
1094 : TII.foldMemoryOperand(MI, FoldOps, StackSlot);
1098 // Remove LIS for any dead defs in the original MI not in FoldMI.
1099 for (MIBundleOperands MO(MI); MO.isValid(); ++MO) {
1102 unsigned Reg = MO->getReg();
1103 if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) ||
1104 MRI.isReserved(Reg)) {
1107 // Skip non-Defs, including undef uses and internal reads.
1110 MIBundleOperands::PhysRegInfo RI =
1111 MIBundleOperands(FoldMI).analyzePhysReg(Reg, &TRI);
1114 // FoldMI does not define this physreg. Remove the LI segment.
1115 assert(MO->isDead() && "Cannot fold physreg def");
1116 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units) {
1117 if (LiveRange *LR = LIS.getCachedRegUnit(*Units)) {
1118 SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
1119 if (VNInfo *VNI = LR->getVNInfoAt(Idx))
1120 LR->removeValNo(VNI);
1125 LIS.ReplaceMachineInstrInMaps(MI, FoldMI);
1126 MI->eraseFromParent();
1128 // Insert any new instructions other than FoldMI into the LIS maps.
1129 assert(!MIS.empty() && "Unexpected empty span of instructions!");
1130 for (MachineBasicBlock::iterator MII = MIS.begin(), End = MIS.end();
1132 if (&*MII != FoldMI)
1133 LIS.InsertMachineInstrInMaps(&*MII);
1135 // TII.foldMemoryOperand may have left some implicit operands on the
1136 // instruction. Strip them.
1138 for (unsigned i = FoldMI->getNumOperands(); i; --i) {
1139 MachineOperand &MO = FoldMI->getOperand(i - 1);
1140 if (!MO.isReg() || !MO.isImplicit())
1142 if (MO.getReg() == ImpReg)
1143 FoldMI->RemoveOperand(i - 1);
1146 DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MIS.end(), LIS,
1151 else if (Ops.front().second == 0)
1158 void InlineSpiller::insertReload(unsigned NewVReg,
1160 MachineBasicBlock::iterator MI) {
1161 MachineBasicBlock &MBB = *MI->getParent();
1163 MachineInstrSpan MIS(MI);
1164 TII.loadRegFromStackSlot(MBB, MI, NewVReg, StackSlot,
1165 MRI.getRegClass(NewVReg), &TRI);
1167 LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MI);
1169 DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MI, LIS, "reload",
1174 /// insertSpill - Insert a spill of NewVReg after MI.
1175 void InlineSpiller::insertSpill(unsigned NewVReg, bool isKill,
1176 MachineBasicBlock::iterator MI) {
1177 MachineBasicBlock &MBB = *MI->getParent();
1179 MachineInstrSpan MIS(MI);
1180 TII.storeRegToStackSlot(MBB, std::next(MI), NewVReg, isKill, StackSlot,
1181 MRI.getRegClass(NewVReg), &TRI);
1183 LIS.InsertMachineInstrRangeInMaps(std::next(MI), MIS.end());
1185 DEBUG(dumpMachineInstrRangeWithSlotIndex(std::next(MI), MIS.end(), LIS,
1190 /// spillAroundUses - insert spill code around each use of Reg.
1191 void InlineSpiller::spillAroundUses(unsigned Reg) {
1192 DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n');
1193 LiveInterval &OldLI = LIS.getInterval(Reg);
1195 // Iterate over instructions using Reg.
1196 for (MachineRegisterInfo::reg_bundle_iterator
1197 RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();
1199 MachineInstr *MI = &*(RegI++);
1201 // Debug values are not allowed to affect codegen.
1202 if (MI->isDebugValue()) {
1203 // Modify DBG_VALUE now that the value is in a spill slot.
1204 bool IsIndirect = MI->isIndirectDebugValue();
1205 uint64_t Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
1206 const MDNode *MDPtr = MI->getOperand(2).getMetadata();
1207 DebugLoc DL = MI->getDebugLoc();
1208 DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
1209 MachineBasicBlock *MBB = MI->getParent();
1210 BuildMI(*MBB, MBB->erase(MI), DL, TII.get(TargetOpcode::DBG_VALUE))
1211 .addFrameIndex(StackSlot).addImm(Offset).addMetadata(MDPtr);
1215 // Ignore copies to/from snippets. We'll delete them.
1216 if (SnippetCopies.count(MI))
1219 // Stack slot accesses may coalesce away.
1220 if (coalesceStackAccess(MI, Reg))
1223 // Analyze instruction.
1224 SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops;
1225 MIBundleOperands::VirtRegInfo RI =
1226 MIBundleOperands(MI).analyzeVirtReg(Reg, &Ops);
1228 // Find the slot index where this instruction reads and writes OldLI.
1229 // This is usually the def slot, except for tied early clobbers.
1230 SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
1231 if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getRegSlot(true)))
1232 if (SlotIndex::isSameInstr(Idx, VNI->def))
1235 // Check for a sibling copy.
1236 unsigned SibReg = isFullCopyOf(MI, Reg);
1237 if (SibReg && isSibling(SibReg)) {
1238 // This may actually be a copy between snippets.
1239 if (isRegToSpill(SibReg)) {
1240 DEBUG(dbgs() << "Found new snippet copy: " << *MI);
1241 SnippetCopies.insert(MI);
1245 // Hoist the spill of a sib-reg copy.
1246 if (hoistSpill(OldLI, MI)) {
1247 // This COPY is now dead, the value is already in the stack slot.
1248 MI->getOperand(0).setIsDead();
1249 DeadDefs.push_back(MI);
1253 // This is a reload for a sib-reg copy. Drop spills downstream.
1254 LiveInterval &SibLI = LIS.getInterval(SibReg);
1255 eliminateRedundantSpills(SibLI, SibLI.getVNInfoAt(Idx));
1256 // The COPY will fold to a reload below.
1260 // Attempt to fold memory ops.
1261 if (foldMemoryOperand(Ops))
1264 // Create a new virtual register for spill/fill.
1265 // FIXME: Infer regclass from instruction alone.
1266 unsigned NewVReg = Edit->createFrom(Reg);
1269 insertReload(NewVReg, Idx, MI);
1271 // Rewrite instruction operands.
1272 bool hasLiveDef = false;
1273 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
1274 MachineOperand &MO = Ops[i].first->getOperand(Ops[i].second);
1277 if (!Ops[i].first->isRegTiedToDefOperand(Ops[i].second))
1284 DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI << '\n');
1286 // FIXME: Use a second vreg if instruction has no tied ops.
1289 insertSpill(NewVReg, true, MI);
1293 /// spillAll - Spill all registers remaining after rematerialization.
1294 void InlineSpiller::spillAll() {
1295 // Update LiveStacks now that we are committed to spilling.
1296 if (StackSlot == VirtRegMap::NO_STACK_SLOT) {
1297 StackSlot = VRM.assignVirt2StackSlot(Original);
1298 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original));
1299 StackInt->getNextValue(SlotIndex(), LSS.getVNInfoAllocator());
1301 StackInt = &LSS.getInterval(StackSlot);
1303 if (Original != Edit->getReg())
1304 VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot);
1306 assert(StackInt->getNumValNums() == 1 && "Bad stack interval values");
1307 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
1308 StackInt->MergeSegmentsInAsValue(LIS.getInterval(RegsToSpill[i]),
1309 StackInt->getValNumInfo(0));
1310 DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n');
1312 // Spill around uses of all RegsToSpill.
1313 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
1314 spillAroundUses(RegsToSpill[i]);
1316 // Hoisted spills may cause dead code.
1317 if (!DeadDefs.empty()) {
1318 DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n");
1319 Edit->eliminateDeadDefs(DeadDefs, RegsToSpill);
1322 // Finally delete the SnippetCopies.
1323 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
1324 for (MachineRegisterInfo::reg_instr_iterator
1325 RI = MRI.reg_instr_begin(RegsToSpill[i]), E = MRI.reg_instr_end();
1327 MachineInstr *MI = &*(RI++);
1328 assert(SnippetCopies.count(MI) && "Remaining use wasn't a snippet copy");
1329 // FIXME: Do this with a LiveRangeEdit callback.
1330 LIS.RemoveMachineInstrFromMaps(MI);
1331 MI->eraseFromParent();
1335 // Delete all spilled registers.
1336 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
1337 Edit->eraseVirtReg(RegsToSpill[i]);
1340 void InlineSpiller::spill(LiveRangeEdit &edit) {
1343 assert(!TargetRegisterInfo::isStackSlot(edit.getReg())
1344 && "Trying to spill a stack slot.");
1345 // Share a stack slot among all descendants of Original.
1346 Original = VRM.getOriginal(edit.getReg());
1347 StackSlot = VRM.getStackSlot(Original);
1350 DEBUG(dbgs() << "Inline spilling "
1351 << MRI.getRegClass(edit.getReg())->getName()
1352 << ':' << edit.getParent()
1353 << "\nFrom original " << PrintReg(Original) << '\n');
1354 assert(edit.getParent().isSpillable() &&
1355 "Attempting to spill already spilled value.");
1356 assert(DeadDefs.empty() && "Previous spill didn't remove dead defs");
1358 collectRegsToSpill();
1359 analyzeSiblingValues();
1362 // Remat may handle everything.
1363 if (!RegsToSpill.empty())
1366 Edit->calculateRegClassAndHint(MF, Loops, MBFI);