1 //===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The inline spiller modifies the machine function directly instead of
11 // inserting spills and restores in VirtRegMap.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "spiller"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/raw_ostream.h"
30 class InlineSpiller : public Spiller {
34 MachineFrameInfo &mfi_;
35 MachineRegisterInfo &mri_;
36 const TargetInstrInfo &tii_;
37 const TargetRegisterInfo &tri_;
38 const BitVector reserved_;
40 // Variables that are valid during spill(), but used by multiple methods.
42 std::vector<LiveInterval*> *newIntervals_;
43 const TargetRegisterClass *rc_;
45 const SmallVectorImpl<LiveInterval*> *spillIs_;
47 // Values of the current interval that can potentially remat.
48 SmallPtrSet<VNInfo*, 8> reMattable_;
50 // Values in reMattable_ that failed to remat at some point.
51 SmallPtrSet<VNInfo*, 8> usedValues_;
56 InlineSpiller(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
57 : mf_(*mf), lis_(*lis), vrm_(*vrm),
58 mfi_(*mf->getFrameInfo()),
59 mri_(mf->getRegInfo()),
60 tii_(*mf->getTarget().getInstrInfo()),
61 tri_(*mf->getTarget().getRegisterInfo()),
62 reserved_(tri_.getReservedRegs(mf_)) {}
64 void spill(LiveInterval *li,
65 std::vector<LiveInterval*> &newIntervals,
66 SmallVectorImpl<LiveInterval*> &spillIs,
67 SlotIndex *earliestIndex);
70 bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
72 bool reMaterializeFor(MachineBasicBlock::iterator MI);
73 void reMaterializeAll();
75 bool foldMemoryOperand(MachineBasicBlock::iterator MI,
76 const SmallVectorImpl<unsigned> &Ops);
77 void insertReload(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
78 void insertSpill(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
83 Spiller *createInlineSpiller(MachineFunction *mf,
85 const MachineLoopInfo *mli,
87 return new InlineSpiller(mf, lis, vrm);
91 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
92 /// OrigIdx are also available with the same value at UseIdx.
93 bool InlineSpiller::allUsesAvailableAt(const MachineInstr *OrigMI,
96 OrigIdx = OrigIdx.getUseIndex();
97 UseIdx = UseIdx.getUseIndex();
98 for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
99 const MachineOperand &MO = OrigMI->getOperand(i);
100 if (!MO.isReg() || !MO.getReg() || MO.getReg() == li_->reg)
102 // Reserved registers are OK.
103 if (MO.isUndef() || !lis_.hasInterval(MO.getReg()))
105 // We don't want to move any defs.
108 // We cannot depend on virtual registers in spillIs_. They will be spilled.
109 for (unsigned si = 0, se = spillIs_->size(); si != se; ++si)
110 if ((*spillIs_)[si]->reg == MO.getReg())
113 LiveInterval &LI = lis_.getInterval(MO.getReg());
114 const VNInfo *OVNI = LI.getVNInfoAt(OrigIdx);
117 if (OVNI != LI.getVNInfoAt(UseIdx))
123 /// reMaterializeFor - Attempt to rematerialize li_->reg before MI instead of
125 bool InlineSpiller::reMaterializeFor(MachineBasicBlock::iterator MI) {
126 SlotIndex UseIdx = lis_.getInstructionIndex(MI).getUseIndex();
127 VNInfo *OrigVNI = li_->getVNInfoAt(UseIdx);
129 DEBUG(dbgs() << "\tadding <undef> flags: ");
130 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
131 MachineOperand &MO = MI->getOperand(i);
132 if (MO.isReg() && MO.isUse() && MO.getReg() == li_->reg)
135 DEBUG(dbgs() << UseIdx << '\t' << *MI);
138 if (!reMattable_.count(OrigVNI)) {
139 DEBUG(dbgs() << "\tusing non-remat valno " << OrigVNI->id << ": "
140 << UseIdx << '\t' << *MI);
143 MachineInstr *OrigMI = lis_.getInstructionFromIndex(OrigVNI->def);
144 if (!allUsesAvailableAt(OrigMI, OrigVNI->def, UseIdx)) {
145 usedValues_.insert(OrigVNI);
146 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
150 // If the instruction also writes li_->reg, it had better not require the same
151 // register for uses and defs.
153 SmallVector<unsigned, 8> Ops;
154 tie(Reads, Writes) = MI->readsWritesVirtualRegister(li_->reg, &Ops);
156 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
157 MachineOperand &MO = MI->getOperand(Ops[i]);
158 if (MO.isUse() ? MI->isRegTiedToDefOperand(Ops[i]) : MO.getSubReg()) {
159 usedValues_.insert(OrigVNI);
160 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
166 // Alocate a new register for the remat.
167 unsigned NewVReg = mri_.createVirtualRegister(rc_);
169 LiveInterval &NewLI = lis_.getOrCreateInterval(NewVReg);
170 NewLI.markNotSpillable();
171 newIntervals_->push_back(&NewLI);
173 // Finally we can rematerialize OrigMI before MI.
174 MachineBasicBlock &MBB = *MI->getParent();
175 tii_.reMaterialize(MBB, MI, NewLI.reg, 0, OrigMI, tri_);
176 MachineBasicBlock::iterator RematMI = MI;
177 SlotIndex DefIdx = lis_.InsertMachineInstrInMaps(--RematMI).getDefIndex();
178 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t' << *RematMI);
181 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
182 MachineOperand &MO = MI->getOperand(Ops[i]);
183 if (MO.isReg() && MO.isUse() && MO.getReg() == li_->reg) {
188 DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI);
190 VNInfo *DefVNI = NewLI.getNextValue(DefIdx, 0, true,
191 lis_.getVNInfoAllocator());
192 NewLI.addRange(LiveRange(DefIdx, UseIdx.getDefIndex(), DefVNI));
193 DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
197 /// reMaterializeAll - Try to rematerialize as many uses of li_ as possible,
198 /// and trim the live ranges after.
199 void InlineSpiller::reMaterializeAll() {
200 // Do a quick scan of the interval values to find if any are remattable.
203 for (LiveInterval::const_vni_iterator I = li_->vni_begin(),
204 E = li_->vni_end(); I != E; ++I) {
206 if (VNI->isUnused() || !VNI->isDefAccurate())
208 MachineInstr *DefMI = lis_.getInstructionFromIndex(VNI->def);
209 if (!DefMI || !tii_.isTriviallyReMaterializable(DefMI))
211 reMattable_.insert(VNI);
214 // Often, no defs are remattable.
215 if (reMattable_.empty())
218 // Try to remat before all uses of li_->reg.
219 bool anyRemat = false;
220 for (MachineRegisterInfo::use_nodbg_iterator
221 RI = mri_.use_nodbg_begin(li_->reg);
222 MachineInstr *MI = RI.skipInstruction();)
223 anyRemat |= reMaterializeFor(MI);
228 // Remove any values that were completely rematted.
229 bool anyRemoved = false;
230 for (SmallPtrSet<VNInfo*, 8>::iterator I = reMattable_.begin(),
231 E = reMattable_.end(); I != E; ++I) {
233 if (VNI->hasPHIKill() || usedValues_.count(VNI))
235 MachineInstr *DefMI = lis_.getInstructionFromIndex(VNI->def);
236 DEBUG(dbgs() << "\tremoving dead def: " << VNI->def << '\t' << *DefMI);
237 lis_.RemoveMachineInstrFromMaps(DefMI);
238 vrm_.RemoveMachineInstrFromMaps(DefMI);
239 DefMI->eraseFromParent();
240 li_->removeValNo(VNI);
247 // Removing values may cause debug uses where li_ is not live.
248 for (MachineRegisterInfo::use_iterator RI = mri_.use_begin(li_->reg);
249 MachineInstr *MI = RI.skipInstruction();) {
250 if (!MI->isDebugValue())
252 // Try to preserve the debug value if li_ is live immediately after it.
253 MachineBasicBlock::iterator NextMI = MI;
255 if (NextMI != MI->getParent()->end() && !lis_.isNotInMIMap(NextMI)) {
256 SlotIndex NearIdx = lis_.getInstructionIndex(NextMI);
257 if (li_->liveAt(NearIdx))
260 DEBUG(dbgs() << "Removing debug info due to remat:" << "\t" << *MI);
261 assert(&*RI != MI && "Multiple register operands on debug value");
262 MI->eraseFromParent();
266 /// foldMemoryOperand - Try folding stack slot references in Ops into MI.
267 /// Return true on success, and MI will be erased.
268 bool InlineSpiller::foldMemoryOperand(MachineBasicBlock::iterator MI,
269 const SmallVectorImpl<unsigned> &Ops) {
270 // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
272 SmallVector<unsigned, 8> FoldOps;
273 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
274 unsigned Idx = Ops[i];
275 MachineOperand &MO = MI->getOperand(Idx);
278 // FIXME: Teach targets to deal with subregs.
281 // Tied use operands should not be passed to foldMemoryOperand.
282 if (!MI->isRegTiedToDefOperand(Idx))
283 FoldOps.push_back(Idx);
286 MachineInstr *FoldMI = tii_.foldMemoryOperand(mf_, MI, FoldOps, stackSlot_);
289 MachineBasicBlock &MBB = *MI->getParent();
290 lis_.ReplaceMachineInstrInMaps(MI, FoldMI);
291 vrm_.addSpillSlotUse(stackSlot_, FoldMI);
292 MBB.insert(MBB.erase(MI), FoldMI);
293 DEBUG(dbgs() << "\tfolded: " << *FoldMI);
297 /// insertReload - Insert a reload of NewLI.reg before MI.
298 void InlineSpiller::insertReload(LiveInterval &NewLI,
299 MachineBasicBlock::iterator MI) {
300 MachineBasicBlock &MBB = *MI->getParent();
301 SlotIndex Idx = lis_.getInstructionIndex(MI).getDefIndex();
302 tii_.loadRegFromStackSlot(MBB, MI, NewLI.reg, stackSlot_, rc_, &tri_);
303 --MI; // Point to load instruction.
304 SlotIndex LoadIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex();
305 vrm_.addSpillSlotUse(stackSlot_, MI);
306 DEBUG(dbgs() << "\treload: " << LoadIdx << '\t' << *MI);
307 VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0, true,
308 lis_.getVNInfoAllocator());
309 NewLI.addRange(LiveRange(LoadIdx, Idx, LoadVNI));
312 /// insertSpill - Insert a spill of NewLI.reg after MI.
313 void InlineSpiller::insertSpill(LiveInterval &NewLI,
314 MachineBasicBlock::iterator MI) {
315 MachineBasicBlock &MBB = *MI->getParent();
316 SlotIndex Idx = lis_.getInstructionIndex(MI).getDefIndex();
317 tii_.storeRegToStackSlot(MBB, ++MI, NewLI.reg, true, stackSlot_, rc_, &tri_);
318 --MI; // Point to store instruction.
319 SlotIndex StoreIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex();
320 vrm_.addSpillSlotUse(stackSlot_, MI);
321 DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MI);
322 VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, true,
323 lis_.getVNInfoAllocator());
324 NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
327 void InlineSpiller::spill(LiveInterval *li,
328 std::vector<LiveInterval*> &newIntervals,
329 SmallVectorImpl<LiveInterval*> &spillIs,
330 SlotIndex *earliestIndex) {
331 DEBUG(dbgs() << "Inline spilling " << *li << "\n");
332 assert(li->isSpillable() && "Attempting to spill already spilled value.");
333 assert(!li->isStackSlot() && "Trying to spill a stack slot.");
336 newIntervals_ = &newIntervals;
337 rc_ = mri_.getRegClass(li->reg);
342 // Remat may handle everything.
346 stackSlot_ = vrm_.assignVirt2StackSlot(li->reg);
348 // Iterate over instructions using register.
349 for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(li->reg);
350 MachineInstr *MI = RI.skipInstruction();) {
352 // Debug values are not allowed to affect codegen.
353 if (MI->isDebugValue()) {
354 // Modify DBG_VALUE now that the value is in a spill slot.
355 uint64_t Offset = MI->getOperand(1).getImm();
356 const MDNode *MDPtr = MI->getOperand(2).getMetadata();
357 DebugLoc DL = MI->getDebugLoc();
358 if (MachineInstr *NewDV = tii_.emitFrameIndexDebugValue(mf_, stackSlot_,
359 Offset, MDPtr, DL)) {
360 DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
361 MachineBasicBlock *MBB = MI->getParent();
362 MBB->insert(MBB->erase(MI), NewDV);
364 DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI);
365 MI->eraseFromParent();
370 // Analyze instruction.
372 SmallVector<unsigned, 8> Ops;
373 tie(Reads, Writes) = MI->readsWritesVirtualRegister(li->reg, &Ops);
375 // Attempt to fold memory ops.
376 if (foldMemoryOperand(MI, Ops))
379 // Allocate interval around instruction.
380 // FIXME: Infer regclass from instruction alone.
381 unsigned NewVReg = mri_.createVirtualRegister(rc_);
383 LiveInterval &NewLI = lis_.getOrCreateInterval(NewVReg);
384 NewLI.markNotSpillable();
387 insertReload(NewLI, MI);
389 // Rewrite instruction operands.
390 bool hasLiveDef = false;
391 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
392 MachineOperand &MO = MI->getOperand(Ops[i]);
395 if (!MI->isRegTiedToDefOperand(Ops[i]))
403 // FIXME: Use a second vreg if instruction has no tied ops.
404 if (Writes && hasLiveDef)
405 insertSpill(NewLI, MI);
407 DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
408 newIntervals.push_back(&NewLI);