1 //===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The inline spiller modifies the machine function directly instead of
11 // inserting spills and restores in VirtRegMap.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
17 #include "VirtRegMap.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/ADT/TinyPtrVector.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/LiveRangeEdit.h"
23 #include "llvm/CodeGen/LiveStackAnalysis.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineInstrBundle.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/raw_ostream.h"
38 STATISTIC(NumSpilledRanges, "Number of spilled live ranges");
39 STATISTIC(NumSnippets, "Number of spilled snippets");
40 STATISTIC(NumSpills, "Number of spills inserted");
41 STATISTIC(NumSpillsRemoved, "Number of spills removed");
42 STATISTIC(NumReloads, "Number of reloads inserted");
43 STATISTIC(NumReloadsRemoved, "Number of reloads removed");
44 STATISTIC(NumFolded, "Number of folded stack accesses");
45 STATISTIC(NumFoldedLoads, "Number of folded loads");
46 STATISTIC(NumRemats, "Number of rematerialized defs for spilling");
47 STATISTIC(NumOmitReloadSpill, "Number of omitted spills of reloads");
48 STATISTIC(NumHoists, "Number of hoisted spills");
50 static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden,
51 cl::desc("Disable inline spill hoisting"));
54 class InlineSpiller : public Spiller {
59 MachineDominatorTree &MDT;
60 MachineLoopInfo &Loops;
62 MachineFrameInfo &MFI;
63 MachineRegisterInfo &MRI;
64 const TargetInstrInfo &TII;
65 const TargetRegisterInfo &TRI;
67 // Variables that are valid during spill(), but used by multiple methods.
69 LiveInterval *StackInt;
73 // All registers to spill to StackSlot, including the main register.
74 SmallVector<unsigned, 8> RegsToSpill;
76 // All COPY instructions to/from snippets.
77 // They are ignored since both operands refer to the same stack slot.
78 SmallPtrSet<MachineInstr*, 8> SnippetCopies;
80 // Values that failed to remat at some point.
81 SmallPtrSet<VNInfo*, 8> UsedValues;
84 // Information about a value that was defined by a copy from a sibling
87 // True when all reaching defs were reloads: No spill is necessary.
88 bool AllDefsAreReloads;
90 // True when value is defined by an original PHI not from splitting.
93 // True when the COPY defining this value killed its source.
96 // The preferred register to spill.
99 // The value of SpillReg that should be spilled.
102 // The block where SpillVNI should be spilled. Currently, this must be the
103 // block containing SpillVNI->def.
104 MachineBasicBlock *SpillMBB;
106 // A defining instruction that is not a sibling copy or a reload, or NULL.
107 // This can be used as a template for rematerialization.
110 // List of values that depend on this one. These values are actually the
111 // same, but live range splitting has placed them in different registers,
112 // or SSA update needed to insert PHI-defs to preserve SSA form. This is
113 // copies of the current value and phi-kills. Usually only phi-kills cause
114 // more than one dependent value.
115 TinyPtrVector<VNInfo*> Deps;
117 SibValueInfo(unsigned Reg, VNInfo *VNI)
118 : AllDefsAreReloads(true), DefByOrigPHI(false), KillsSource(false),
119 SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {}
121 // Returns true when a def has been found.
122 bool hasDef() const { return DefByOrigPHI || DefMI; }
126 // Values in RegsToSpill defined by sibling copies.
127 typedef DenseMap<VNInfo*, SibValueInfo> SibValueMap;
128 SibValueMap SibValues;
130 // Dead defs generated during spilling.
131 SmallVector<MachineInstr*, 8> DeadDefs;
136 InlineSpiller(MachineFunctionPass &pass,
140 LIS(pass.getAnalysis<LiveIntervals>()),
141 LSS(pass.getAnalysis<LiveStacks>()),
142 AA(&pass.getAnalysis<AliasAnalysis>()),
143 MDT(pass.getAnalysis<MachineDominatorTree>()),
144 Loops(pass.getAnalysis<MachineLoopInfo>()),
146 MFI(*mf.getFrameInfo()),
147 MRI(mf.getRegInfo()),
148 TII(*mf.getTarget().getInstrInfo()),
149 TRI(*mf.getTarget().getRegisterInfo()) {}
151 void spill(LiveRangeEdit &);
154 bool isSnippet(const LiveInterval &SnipLI);
155 void collectRegsToSpill();
157 bool isRegToSpill(unsigned Reg) {
158 return std::find(RegsToSpill.begin(),
159 RegsToSpill.end(), Reg) != RegsToSpill.end();
162 bool isSibling(unsigned Reg);
163 MachineInstr *traceSiblingValue(unsigned, VNInfo*, VNInfo*);
164 void propagateSiblingValue(SibValueMap::iterator, VNInfo *VNI = 0);
165 void analyzeSiblingValues();
167 bool hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI);
168 void eliminateRedundantSpills(LiveInterval &LI, VNInfo *VNI);
170 void markValueUsed(LiveInterval*, VNInfo*);
171 bool reMaterializeFor(LiveInterval&, MachineBasicBlock::iterator MI);
172 void reMaterializeAll();
174 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
175 bool foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> >,
176 MachineInstr *LoadMI = 0);
177 void insertReload(LiveInterval &NewLI, SlotIndex,
178 MachineBasicBlock::iterator MI);
179 void insertSpill(LiveInterval &NewLI, const LiveInterval &OldLI,
180 SlotIndex, MachineBasicBlock::iterator MI);
182 void spillAroundUses(unsigned Reg);
188 Spiller *createInlineSpiller(MachineFunctionPass &pass,
191 return new InlineSpiller(pass, mf, vrm);
195 //===----------------------------------------------------------------------===//
197 //===----------------------------------------------------------------------===//
199 // When spilling a virtual register, we also spill any snippets it is connected
200 // to. The snippets are small live ranges that only have a single real use,
201 // leftovers from live range splitting. Spilling them enables memory operand
202 // folding or tightens the live range around the single use.
204 // This minimizes register pressure and maximizes the store-to-load distance for
205 // spill slots which can be important in tight loops.
207 /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
208 /// otherwise return 0.
209 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) {
210 if (!MI->isFullCopy())
212 if (MI->getOperand(0).getReg() == Reg)
213 return MI->getOperand(1).getReg();
214 if (MI->getOperand(1).getReg() == Reg)
215 return MI->getOperand(0).getReg();
219 /// isSnippet - Identify if a live interval is a snippet that should be spilled.
220 /// It is assumed that SnipLI is a virtual register with the same original as
222 bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
223 unsigned Reg = Edit->getReg();
225 // A snippet is a tiny live range with only a single instruction using it
226 // besides copies to/from Reg or spills/fills. We accept:
228 // %snip = COPY %Reg / FILL fi#
230 // %Reg = COPY %snip / SPILL %snip, fi#
232 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
235 MachineInstr *UseMI = 0;
237 // Check that all uses satisfy our criteria.
238 for (MachineRegisterInfo::reg_nodbg_iterator
239 RI = MRI.reg_nodbg_begin(SnipLI.reg);
240 MachineInstr *MI = RI.skipInstruction();) {
242 // Allow copies to/from Reg.
243 if (isFullCopyOf(MI, Reg))
246 // Allow stack slot loads.
248 if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot)
251 // Allow stack slot stores.
252 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
255 // Allow a single additional instruction.
256 if (UseMI && MI != UseMI)
263 /// collectRegsToSpill - Collect live range snippets that only have a single
265 void InlineSpiller::collectRegsToSpill() {
266 unsigned Reg = Edit->getReg();
268 // Main register always spills.
269 RegsToSpill.assign(1, Reg);
270 SnippetCopies.clear();
272 // Snippets all have the same original, so there can't be any for an original
277 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg);
278 MachineInstr *MI = RI.skipInstruction();) {
279 unsigned SnipReg = isFullCopyOf(MI, Reg);
280 if (!isSibling(SnipReg))
282 LiveInterval &SnipLI = LIS.getInterval(SnipReg);
283 if (!isSnippet(SnipLI))
285 SnippetCopies.insert(MI);
286 if (isRegToSpill(SnipReg))
288 RegsToSpill.push_back(SnipReg);
289 DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n');
295 //===----------------------------------------------------------------------===//
297 //===----------------------------------------------------------------------===//
299 // After live range splitting, some values to be spilled may be defined by
300 // copies from sibling registers. We trace the sibling copies back to the
301 // original value if it still exists. We need it for rematerialization.
303 // Even when the value can't be rematerialized, we still want to determine if
304 // the value has already been spilled, or we may want to hoist the spill from a
307 bool InlineSpiller::isSibling(unsigned Reg) {
308 return TargetRegisterInfo::isVirtualRegister(Reg) &&
309 VRM.getOriginal(Reg) == Original;
313 static raw_ostream &operator<<(raw_ostream &OS,
314 const InlineSpiller::SibValueInfo &SVI) {
315 OS << "spill " << PrintReg(SVI.SpillReg) << ':'
316 << SVI.SpillVNI->id << '@' << SVI.SpillVNI->def;
318 OS << " in BB#" << SVI.SpillMBB->getNumber();
319 if (SVI.AllDefsAreReloads)
320 OS << " all-reloads";
321 if (SVI.DefByOrigPHI)
326 for (unsigned i = 0, e = SVI.Deps.size(); i != e; ++i)
327 OS << ' ' << SVI.Deps[i]->id << '@' << SVI.Deps[i]->def;
330 OS << " def: " << *SVI.DefMI;
337 /// propagateSiblingValue - Propagate the value in SVI to dependents if it is
338 /// known. Otherwise remember the dependency for later.
340 /// @param SVI SibValues entry to propagate.
341 /// @param VNI Dependent value, or NULL to propagate to all saved dependents.
342 void InlineSpiller::propagateSiblingValue(SibValueMap::iterator SVI,
344 // When VNI is non-NULL, add it to SVI's deps, and only propagate to that.
345 TinyPtrVector<VNInfo*> FirstDeps;
347 FirstDeps.push_back(VNI);
348 SVI->second.Deps.push_back(VNI);
351 // Has the value been completely determined yet? If not, defer propagation.
352 if (!SVI->second.hasDef())
355 // Work list of values to propagate. It would be nice to use a SetVector
356 // here, but then we would be forced to use a SmallSet.
357 SmallVector<SibValueMap::iterator, 8> WorkList(1, SVI);
358 SmallPtrSet<VNInfo*, 8> WorkSet;
361 SVI = WorkList.pop_back_val();
362 WorkSet.erase(SVI->first);
363 TinyPtrVector<VNInfo*> *Deps = VNI ? &FirstDeps : &SVI->second.Deps;
366 SibValueInfo &SV = SVI->second;
368 SV.SpillMBB = LIS.getMBBFromIndex(SV.SpillVNI->def);
370 DEBUG(dbgs() << " prop to " << Deps->size() << ": "
371 << SVI->first->id << '@' << SVI->first->def << ":\t" << SV);
373 assert(SV.hasDef() && "Propagating undefined value");
375 // Should this value be propagated as a preferred spill candidate? We don't
376 // propagate values of registers that are about to spill.
377 bool PropSpill = !DisableHoisting && !isRegToSpill(SV.SpillReg);
378 unsigned SpillDepth = ~0u;
380 for (TinyPtrVector<VNInfo*>::iterator DepI = Deps->begin(),
381 DepE = Deps->end(); DepI != DepE; ++DepI) {
382 SibValueMap::iterator DepSVI = SibValues.find(*DepI);
383 assert(DepSVI != SibValues.end() && "Dependent value not in SibValues");
384 SibValueInfo &DepSV = DepSVI->second;
386 DepSV.SpillMBB = LIS.getMBBFromIndex(DepSV.SpillVNI->def);
388 bool Changed = false;
390 // Propagate defining instruction.
391 if (!DepSV.hasDef()) {
393 DepSV.DefMI = SV.DefMI;
394 DepSV.DefByOrigPHI = SV.DefByOrigPHI;
397 // Propagate AllDefsAreReloads. For PHI values, this computes an AND of
399 if (!SV.AllDefsAreReloads && DepSV.AllDefsAreReloads) {
401 DepSV.AllDefsAreReloads = false;
404 // Propagate best spill value.
405 if (PropSpill && SV.SpillVNI != DepSV.SpillVNI) {
406 if (SV.SpillMBB == DepSV.SpillMBB) {
407 // DepSV is in the same block. Hoist when dominated.
408 if (DepSV.KillsSource && SV.SpillVNI->def < DepSV.SpillVNI->def) {
409 // This is an alternative def earlier in the same MBB.
410 // Hoist the spill as far as possible in SpillMBB. This can ease
411 // register pressure:
417 // Hoisting the spill of s to immediately after the def removes the
418 // interference between x and y:
424 // This hoist only helps when the DepSV copy kills its source.
426 DepSV.SpillReg = SV.SpillReg;
427 DepSV.SpillVNI = SV.SpillVNI;
428 DepSV.SpillMBB = SV.SpillMBB;
431 // DepSV is in a different block.
432 if (SpillDepth == ~0u)
433 SpillDepth = Loops.getLoopDepth(SV.SpillMBB);
435 // Also hoist spills to blocks with smaller loop depth, but make sure
436 // that the new value dominates. Non-phi dependents are always
437 // dominated, phis need checking.
438 if ((Loops.getLoopDepth(DepSV.SpillMBB) > SpillDepth) &&
439 (!DepSVI->first->isPHIDef() ||
440 MDT.dominates(SV.SpillMBB, DepSV.SpillMBB))) {
442 DepSV.SpillReg = SV.SpillReg;
443 DepSV.SpillVNI = SV.SpillVNI;
444 DepSV.SpillMBB = SV.SpillMBB;
452 // Something changed in DepSVI. Propagate to dependents.
453 if (WorkSet.insert(DepSVI->first))
454 WorkList.push_back(DepSVI);
456 DEBUG(dbgs() << " update " << DepSVI->first->id << '@'
457 << DepSVI->first->def << " to:\t" << DepSV);
459 } while (!WorkList.empty());
462 /// traceSiblingValue - Trace a value that is about to be spilled back to the
463 /// real defining instructions by looking through sibling copies. Always stay
464 /// within the range of OrigVNI so the registers are known to carry the same
467 /// Determine if the value is defined by all reloads, so spilling isn't
468 /// necessary - the value is already in the stack slot.
470 /// Return a defining instruction that may be a candidate for rematerialization.
472 MachineInstr *InlineSpiller::traceSiblingValue(unsigned UseReg, VNInfo *UseVNI,
474 // Check if a cached value already exists.
475 SibValueMap::iterator SVI;
478 SibValues.insert(std::make_pair(UseVNI, SibValueInfo(UseReg, UseVNI)));
480 DEBUG(dbgs() << "Cached value " << PrintReg(UseReg) << ':'
481 << UseVNI->id << '@' << UseVNI->def << ' ' << SVI->second);
482 return SVI->second.DefMI;
485 DEBUG(dbgs() << "Tracing value " << PrintReg(UseReg) << ':'
486 << UseVNI->id << '@' << UseVNI->def << '\n');
488 // List of (Reg, VNI) that have been inserted into SibValues, but need to be
490 SmallVector<std::pair<unsigned, VNInfo*>, 8> WorkList;
491 WorkList.push_back(std::make_pair(UseReg, UseVNI));
496 tie(Reg, VNI) = WorkList.pop_back_val();
497 DEBUG(dbgs() << " " << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def
500 // First check if this value has already been computed.
501 SVI = SibValues.find(VNI);
502 assert(SVI != SibValues.end() && "Missing SibValues entry");
504 // Trace through PHI-defs created by live range splitting.
505 if (VNI->isPHIDef()) {
506 // Stop at original PHIs. We don't know the value at the predecessors.
507 if (VNI->def == OrigVNI->def) {
508 DEBUG(dbgs() << "orig phi value\n");
509 SVI->second.DefByOrigPHI = true;
510 SVI->second.AllDefsAreReloads = false;
511 propagateSiblingValue(SVI);
515 // This is a PHI inserted by live range splitting. We could trace the
516 // live-out value from predecessor blocks, but that search can be very
517 // expensive if there are many predecessors and many more PHIs as
518 // generated by tail-dup when it sees an indirectbr. Instead, look at
519 // all the non-PHI defs that have the same value as OrigVNI. They must
520 // jointly dominate VNI->def. This is not optimal since VNI may actually
521 // be jointly dominated by a smaller subset of defs, so there is a change
522 // we will miss a AllDefsAreReloads optimization.
524 // Separate all values dominated by OrigVNI into PHIs and non-PHIs.
525 SmallVector<VNInfo*, 8> PHIs, NonPHIs;
526 LiveInterval &LI = LIS.getInterval(Reg);
527 LiveInterval &OrigLI = LIS.getInterval(Original);
529 for (LiveInterval::vni_iterator VI = LI.vni_begin(), VE = LI.vni_end();
532 if (VNI2->isUnused())
534 if (!OrigLI.containsOneValue() &&
535 OrigLI.getVNInfoAt(VNI2->def) != OrigVNI)
537 if (VNI2->isPHIDef() && VNI2->def != OrigVNI->def)
538 PHIs.push_back(VNI2);
540 NonPHIs.push_back(VNI2);
542 DEBUG(dbgs() << "split phi value, checking " << PHIs.size()
543 << " phi-defs, and " << NonPHIs.size()
544 << " non-phi/orig defs\n");
546 // Create entries for all the PHIs. Don't add them to the worklist, we
547 // are processing all of them in one go here.
548 for (unsigned i = 0, e = PHIs.size(); i != e; ++i)
549 SibValues.insert(std::make_pair(PHIs[i], SibValueInfo(Reg, PHIs[i])));
551 // Add every PHI as a dependent of all the non-PHIs.
552 for (unsigned i = 0, e = NonPHIs.size(); i != e; ++i) {
553 VNInfo *NonPHI = NonPHIs[i];
554 // Known value? Try an insertion.
556 SibValues.insert(std::make_pair(NonPHI, SibValueInfo(Reg, NonPHI)));
557 // Add all the PHIs as dependents of NonPHI.
558 for (unsigned pi = 0, pe = PHIs.size(); pi != pe; ++pi)
559 SVI->second.Deps.push_back(PHIs[pi]);
560 // This is the first time we see NonPHI, add it to the worklist.
562 WorkList.push_back(std::make_pair(Reg, NonPHI));
564 // Propagate to all inserted PHIs, not just VNI.
565 propagateSiblingValue(SVI);
568 // Next work list item.
572 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
573 assert(MI && "Missing def");
575 // Trace through sibling copies.
576 if (unsigned SrcReg = isFullCopyOf(MI, Reg)) {
577 if (isSibling(SrcReg)) {
578 LiveInterval &SrcLI = LIS.getInterval(SrcReg);
579 LiveRangeQuery SrcQ(SrcLI, VNI->def);
580 assert(SrcQ.valueIn() && "Copy from non-existing value");
581 // Check if this COPY kills its source.
582 SVI->second.KillsSource = SrcQ.isKill();
583 VNInfo *SrcVNI = SrcQ.valueIn();
584 DEBUG(dbgs() << "copy of " << PrintReg(SrcReg) << ':'
585 << SrcVNI->id << '@' << SrcVNI->def
586 << " kill=" << unsigned(SVI->second.KillsSource) << '\n');
587 // Known sibling source value? Try an insertion.
588 tie(SVI, Inserted) = SibValues.insert(std::make_pair(SrcVNI,
589 SibValueInfo(SrcReg, SrcVNI)));
590 // This is the first time we see Src, add it to the worklist.
592 WorkList.push_back(std::make_pair(SrcReg, SrcVNI));
593 propagateSiblingValue(SVI, VNI);
594 // Next work list item.
599 // Track reachable reloads.
600 SVI->second.DefMI = MI;
601 SVI->second.SpillMBB = MI->getParent();
603 if (Reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) {
604 DEBUG(dbgs() << "reload\n");
605 propagateSiblingValue(SVI);
606 // Next work list item.
610 // Potential remat candidate.
611 DEBUG(dbgs() << "def " << *MI);
612 SVI->second.AllDefsAreReloads = false;
613 propagateSiblingValue(SVI);
614 } while (!WorkList.empty());
616 // Look up the value we were looking for. We already did this lokup at the
617 // top of the function, but SibValues may have been invalidated.
618 SVI = SibValues.find(UseVNI);
619 assert(SVI != SibValues.end() && "Didn't compute requested info");
620 DEBUG(dbgs() << " traced to:\t" << SVI->second);
621 return SVI->second.DefMI;
624 /// analyzeSiblingValues - Trace values defined by sibling copies back to
625 /// something that isn't a sibling copy.
627 /// Keep track of values that may be rematerializable.
628 void InlineSpiller::analyzeSiblingValues() {
631 // No siblings at all?
632 if (Edit->getReg() == Original)
635 LiveInterval &OrigLI = LIS.getInterval(Original);
636 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
637 unsigned Reg = RegsToSpill[i];
638 LiveInterval &LI = LIS.getInterval(Reg);
639 for (LiveInterval::const_vni_iterator VI = LI.vni_begin(),
640 VE = LI.vni_end(); VI != VE; ++VI) {
644 MachineInstr *DefMI = 0;
645 if (!VNI->isPHIDef()) {
646 DefMI = LIS.getInstructionFromIndex(VNI->def);
647 assert(DefMI && "No defining instruction");
649 // Check possible sibling copies.
650 if (VNI->isPHIDef() || DefMI->isCopy()) {
651 VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
652 assert(OrigVNI && "Def outside original live range");
653 if (OrigVNI->def != VNI->def)
654 DefMI = traceSiblingValue(Reg, VNI, OrigVNI);
656 if (DefMI && Edit->checkRematerializable(VNI, DefMI, AA)) {
657 DEBUG(dbgs() << "Value " << PrintReg(Reg) << ':' << VNI->id << '@'
658 << VNI->def << " may remat from " << *DefMI);
664 /// hoistSpill - Given a sibling copy that defines a value to be spilled, insert
665 /// a spill at a better location.
666 bool InlineSpiller::hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI) {
667 SlotIndex Idx = LIS.getInstructionIndex(CopyMI);
668 VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getRegSlot());
669 assert(VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy");
670 SibValueMap::iterator I = SibValues.find(VNI);
671 if (I == SibValues.end())
674 const SibValueInfo &SVI = I->second;
676 // Let the normal folding code deal with the boring case.
677 if (!SVI.AllDefsAreReloads && SVI.SpillVNI == VNI)
680 // SpillReg may have been deleted by remat and DCE.
681 if (!LIS.hasInterval(SVI.SpillReg)) {
682 DEBUG(dbgs() << "Stale interval: " << PrintReg(SVI.SpillReg) << '\n');
687 LiveInterval &SibLI = LIS.getInterval(SVI.SpillReg);
688 if (!SibLI.containsValue(SVI.SpillVNI)) {
689 DEBUG(dbgs() << "Stale value: " << PrintReg(SVI.SpillReg) << '\n');
694 // Conservatively extend the stack slot range to the range of the original
695 // value. We may be able to do better with stack slot coloring by being more
697 assert(StackInt && "No stack slot assigned yet.");
698 LiveInterval &OrigLI = LIS.getInterval(Original);
699 VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
700 StackInt->MergeValueInAsValue(OrigLI, OrigVNI, StackInt->getValNumInfo(0));
701 DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": "
702 << *StackInt << '\n');
704 // Already spilled everywhere.
705 if (SVI.AllDefsAreReloads) {
706 DEBUG(dbgs() << "\tno spill needed: " << SVI);
707 ++NumOmitReloadSpill;
710 // We are going to spill SVI.SpillVNI immediately after its def, so clear out
711 // any later spills of the same value.
712 eliminateRedundantSpills(SibLI, SVI.SpillVNI);
714 MachineBasicBlock *MBB = LIS.getMBBFromIndex(SVI.SpillVNI->def);
715 MachineBasicBlock::iterator MII;
716 if (SVI.SpillVNI->isPHIDef())
717 MII = MBB->SkipPHIsAndLabels(MBB->begin());
719 MachineInstr *DefMI = LIS.getInstructionFromIndex(SVI.SpillVNI->def);
720 assert(DefMI && "Defining instruction disappeared");
724 // Insert spill without kill flag immediately after def.
725 TII.storeRegToStackSlot(*MBB, MII, SVI.SpillReg, false, StackSlot,
726 MRI.getRegClass(SVI.SpillReg), &TRI);
727 --MII; // Point to store instruction.
728 LIS.InsertMachineInstrInMaps(MII);
729 DEBUG(dbgs() << "\thoisted: " << SVI.SpillVNI->def << '\t' << *MII);
736 /// eliminateRedundantSpills - SLI:VNI is known to be on the stack. Remove any
737 /// redundant spills of this value in SLI.reg and sibling copies.
738 void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
739 assert(VNI && "Missing value");
740 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
741 WorkList.push_back(std::make_pair(&SLI, VNI));
742 assert(StackInt && "No stack slot assigned yet.");
746 tie(LI, VNI) = WorkList.pop_back_val();
747 unsigned Reg = LI->reg;
748 DEBUG(dbgs() << "Checking redundant spills for "
749 << VNI->id << '@' << VNI->def << " in " << *LI << '\n');
751 // Regs to spill are taken care of.
752 if (isRegToSpill(Reg))
755 // Add all of VNI's live range to StackInt.
756 StackInt->MergeValueInAsValue(*LI, VNI, StackInt->getValNumInfo(0));
757 DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n');
759 // Find all spills and copies of VNI.
760 for (MachineRegisterInfo::use_nodbg_iterator UI = MRI.use_nodbg_begin(Reg);
761 MachineInstr *MI = UI.skipInstruction();) {
762 if (!MI->isCopy() && !MI->mayStore())
764 SlotIndex Idx = LIS.getInstructionIndex(MI);
765 if (LI->getVNInfoAt(Idx) != VNI)
768 // Follow sibling copies down the dominator tree.
769 if (unsigned DstReg = isFullCopyOf(MI, Reg)) {
770 if (isSibling(DstReg)) {
771 LiveInterval &DstLI = LIS.getInterval(DstReg);
772 VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getRegSlot());
773 assert(DstVNI && "Missing defined value");
774 assert(DstVNI->def == Idx.getRegSlot() && "Wrong copy def slot");
775 WorkList.push_back(std::make_pair(&DstLI, DstVNI));
782 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
783 DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << *MI);
784 // eliminateDeadDefs won't normally remove stores, so switch opcode.
785 MI->setDesc(TII.get(TargetOpcode::KILL));
786 DeadDefs.push_back(MI);
791 } while (!WorkList.empty());
795 //===----------------------------------------------------------------------===//
797 //===----------------------------------------------------------------------===//
799 /// markValueUsed - Remember that VNI failed to rematerialize, so its defining
800 /// instruction cannot be eliminated. See through snippet copies
801 void InlineSpiller::markValueUsed(LiveInterval *LI, VNInfo *VNI) {
802 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
803 WorkList.push_back(std::make_pair(LI, VNI));
805 tie(LI, VNI) = WorkList.pop_back_val();
806 if (!UsedValues.insert(VNI))
809 if (VNI->isPHIDef()) {
810 MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
811 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
812 PE = MBB->pred_end(); PI != PE; ++PI) {
813 VNInfo *PVNI = LI->getVNInfoBefore(LIS.getMBBEndIdx(*PI));
815 WorkList.push_back(std::make_pair(LI, PVNI));
820 // Follow snippet copies.
821 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
822 if (!SnippetCopies.count(MI))
824 LiveInterval &SnipLI = LIS.getInterval(MI->getOperand(1).getReg());
825 assert(isRegToSpill(SnipLI.reg) && "Unexpected register in copy");
826 VNInfo *SnipVNI = SnipLI.getVNInfoAt(VNI->def.getRegSlot(true));
827 assert(SnipVNI && "Snippet undefined before copy");
828 WorkList.push_back(std::make_pair(&SnipLI, SnipVNI));
829 } while (!WorkList.empty());
832 /// reMaterializeFor - Attempt to rematerialize before MI instead of reloading.
833 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg,
834 MachineBasicBlock::iterator MI) {
835 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
836 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
839 DEBUG(dbgs() << "\tadding <undef> flags: ");
840 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
841 MachineOperand &MO = MI->getOperand(i);
842 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
845 DEBUG(dbgs() << UseIdx << '\t' << *MI);
849 if (SnippetCopies.count(MI))
852 // Use an OrigVNI from traceSiblingValue when ParentVNI is a sibling copy.
853 LiveRangeEdit::Remat RM(ParentVNI);
854 SibValueMap::const_iterator SibI = SibValues.find(ParentVNI);
855 if (SibI != SibValues.end())
856 RM.OrigMI = SibI->second.DefMI;
857 if (!Edit->canRematerializeAt(RM, UseIdx, false)) {
858 markValueUsed(&VirtReg, ParentVNI);
859 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
863 // If the instruction also writes VirtReg.reg, it had better not require the
864 // same register for uses and defs.
865 SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops;
866 MIBundleOperands::RegInfo RI =
867 MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops);
869 markValueUsed(&VirtReg, ParentVNI);
870 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
874 // Before rematerializing into a register for a single instruction, try to
875 // fold a load into the instruction. That avoids allocating a new register.
876 if (RM.OrigMI->canFoldAsLoad() &&
877 foldMemoryOperand(Ops, RM.OrigMI)) {
878 Edit->markRematerialized(RM.ParentVNI);
883 // Alocate a new register for the remat.
884 LiveInterval &NewLI = Edit->createFrom(Original);
885 NewLI.markNotSpillable();
887 // Finally we can rematerialize OrigMI before MI.
888 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM,
890 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'
891 << *LIS.getInstructionFromIndex(DefIdx));
894 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
895 MachineOperand &MO = MI->getOperand(Ops[i].second);
896 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
897 MO.setReg(NewLI.reg);
901 DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI);
903 VNInfo *DefVNI = NewLI.getNextValue(DefIdx, LIS.getVNInfoAllocator());
904 NewLI.addRange(LiveRange(DefIdx, UseIdx.getRegSlot(), DefVNI));
905 DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
910 /// reMaterializeAll - Try to rematerialize as many uses as possible,
911 /// and trim the live ranges after.
912 void InlineSpiller::reMaterializeAll() {
913 // analyzeSiblingValues has already tested all relevant defining instructions.
914 if (!Edit->anyRematerializable(AA))
919 // Try to remat before all uses of snippets.
920 bool anyRemat = false;
921 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
922 unsigned Reg = RegsToSpill[i];
923 LiveInterval &LI = LIS.getInterval(Reg);
924 for (MachineRegisterInfo::use_nodbg_iterator
925 RI = MRI.use_nodbg_begin(Reg);
926 MachineInstr *MI = RI.skipBundle();)
927 anyRemat |= reMaterializeFor(LI, MI);
932 // Remove any values that were completely rematted.
933 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
934 unsigned Reg = RegsToSpill[i];
935 LiveInterval &LI = LIS.getInterval(Reg);
936 for (LiveInterval::vni_iterator I = LI.vni_begin(), E = LI.vni_end();
939 if (VNI->isUnused() || VNI->isPHIDef() || UsedValues.count(VNI))
941 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
942 MI->addRegisterDead(Reg, &TRI);
943 if (!MI->allDefsAreDead())
945 DEBUG(dbgs() << "All defs dead: " << *MI);
946 DeadDefs.push_back(MI);
950 // Eliminate dead code after remat. Note that some snippet copies may be
952 if (DeadDefs.empty())
954 DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n");
955 Edit->eliminateDeadDefs(DeadDefs, RegsToSpill);
957 // Get rid of deleted and empty intervals.
958 for (unsigned i = RegsToSpill.size(); i != 0; --i) {
959 unsigned Reg = RegsToSpill[i-1];
960 if (!LIS.hasInterval(Reg)) {
961 RegsToSpill.erase(RegsToSpill.begin() + (i - 1));
964 LiveInterval &LI = LIS.getInterval(Reg);
967 Edit->eraseVirtReg(Reg);
968 RegsToSpill.erase(RegsToSpill.begin() + (i - 1));
970 DEBUG(dbgs() << RegsToSpill.size() << " registers to spill after remat.\n");
974 //===----------------------------------------------------------------------===//
976 //===----------------------------------------------------------------------===//
978 /// If MI is a load or store of StackSlot, it can be removed.
979 bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
981 unsigned InstrReg = TII.isLoadFromStackSlot(MI, FI);
982 bool IsLoad = InstrReg;
984 InstrReg = TII.isStoreToStackSlot(MI, FI);
986 // We have a stack access. Is it the right register and slot?
987 if (InstrReg != Reg || FI != StackSlot)
990 DEBUG(dbgs() << "Coalescing stack access: " << *MI);
991 LIS.RemoveMachineInstrFromMaps(MI);
992 MI->eraseFromParent();
1005 /// foldMemoryOperand - Try folding stack slot references in Ops into their
1008 /// @param Ops Operand indices from analyzeVirtReg().
1009 /// @param LoadMI Load instruction to use instead of stack slot when non-null.
1010 /// @return True on success.
1011 bool InlineSpiller::
1012 foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> > Ops,
1013 MachineInstr *LoadMI) {
1016 // Don't attempt folding in bundles.
1017 MachineInstr *MI = Ops.front().first;
1018 if (Ops.back().first != MI || MI->isBundled())
1021 bool WasCopy = MI->isCopy();
1022 unsigned ImpReg = 0;
1024 // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
1026 SmallVector<unsigned, 8> FoldOps;
1027 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
1028 unsigned Idx = Ops[i].second;
1029 MachineOperand &MO = MI->getOperand(Idx);
1030 if (MO.isImplicit()) {
1031 ImpReg = MO.getReg();
1034 // FIXME: Teach targets to deal with subregs.
1037 // We cannot fold a load instruction into a def.
1038 if (LoadMI && MO.isDef())
1040 // Tied use operands should not be passed to foldMemoryOperand.
1041 if (!MI->isRegTiedToDefOperand(Idx))
1042 FoldOps.push_back(Idx);
1045 MachineInstr *FoldMI =
1046 LoadMI ? TII.foldMemoryOperand(MI, FoldOps, LoadMI)
1047 : TII.foldMemoryOperand(MI, FoldOps, StackSlot);
1050 LIS.ReplaceMachineInstrInMaps(MI, FoldMI);
1051 MI->eraseFromParent();
1053 // TII.foldMemoryOperand may have left some implicit operands on the
1054 // instruction. Strip them.
1056 for (unsigned i = FoldMI->getNumOperands(); i; --i) {
1057 MachineOperand &MO = FoldMI->getOperand(i - 1);
1058 if (!MO.isReg() || !MO.isImplicit())
1060 if (MO.getReg() == ImpReg)
1061 FoldMI->RemoveOperand(i - 1);
1064 DEBUG(dbgs() << "\tfolded: " << LIS.getInstructionIndex(FoldMI) << '\t'
1068 else if (Ops.front().second == 0)
1075 /// insertReload - Insert a reload of NewLI.reg before MI.
1076 void InlineSpiller::insertReload(LiveInterval &NewLI,
1078 MachineBasicBlock::iterator MI) {
1079 MachineBasicBlock &MBB = *MI->getParent();
1080 TII.loadRegFromStackSlot(MBB, MI, NewLI.reg, StackSlot,
1081 MRI.getRegClass(NewLI.reg), &TRI);
1082 --MI; // Point to load instruction.
1083 SlotIndex LoadIdx = LIS.InsertMachineInstrInMaps(MI).getRegSlot();
1084 DEBUG(dbgs() << "\treload: " << LoadIdx << '\t' << *MI);
1085 VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, LIS.getVNInfoAllocator());
1086 NewLI.addRange(LiveRange(LoadIdx, Idx, LoadVNI));
1090 /// insertSpill - Insert a spill of NewLI.reg after MI.
1091 void InlineSpiller::insertSpill(LiveInterval &NewLI, const LiveInterval &OldLI,
1092 SlotIndex Idx, MachineBasicBlock::iterator MI) {
1093 MachineBasicBlock &MBB = *MI->getParent();
1094 TII.storeRegToStackSlot(MBB, ++MI, NewLI.reg, true, StackSlot,
1095 MRI.getRegClass(NewLI.reg), &TRI);
1096 --MI; // Point to store instruction.
1097 SlotIndex StoreIdx = LIS.InsertMachineInstrInMaps(MI).getRegSlot();
1098 DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MI);
1099 VNInfo *StoreVNI = NewLI.getNextValue(Idx, LIS.getVNInfoAllocator());
1100 NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
1104 /// spillAroundUses - insert spill code around each use of Reg.
1105 void InlineSpiller::spillAroundUses(unsigned Reg) {
1106 DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n');
1107 LiveInterval &OldLI = LIS.getInterval(Reg);
1109 // Iterate over instructions using Reg.
1110 for (MachineRegisterInfo::reg_iterator RegI = MRI.reg_begin(Reg);
1111 MachineInstr *MI = RegI.skipBundle();) {
1113 // Debug values are not allowed to affect codegen.
1114 if (MI->isDebugValue()) {
1115 // Modify DBG_VALUE now that the value is in a spill slot.
1116 uint64_t Offset = MI->getOperand(1).getImm();
1117 const MDNode *MDPtr = MI->getOperand(2).getMetadata();
1118 DebugLoc DL = MI->getDebugLoc();
1119 if (MachineInstr *NewDV = TII.emitFrameIndexDebugValue(MF, StackSlot,
1120 Offset, MDPtr, DL)) {
1121 DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
1122 MachineBasicBlock *MBB = MI->getParent();
1123 MBB->insert(MBB->erase(MI), NewDV);
1125 DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI);
1126 MI->eraseFromParent();
1131 // Ignore copies to/from snippets. We'll delete them.
1132 if (SnippetCopies.count(MI))
1135 // Stack slot accesses may coalesce away.
1136 if (coalesceStackAccess(MI, Reg))
1139 // Analyze instruction.
1140 SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops;
1141 MIBundleOperands::RegInfo RI =
1142 MIBundleOperands(MI).analyzeVirtReg(Reg, &Ops);
1144 // Find the slot index where this instruction reads and writes OldLI.
1145 // This is usually the def slot, except for tied early clobbers.
1146 SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
1147 if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getRegSlot(true)))
1148 if (SlotIndex::isSameInstr(Idx, VNI->def))
1151 // Check for a sibling copy.
1152 unsigned SibReg = isFullCopyOf(MI, Reg);
1153 if (SibReg && isSibling(SibReg)) {
1154 // This may actually be a copy between snippets.
1155 if (isRegToSpill(SibReg)) {
1156 DEBUG(dbgs() << "Found new snippet copy: " << *MI);
1157 SnippetCopies.insert(MI);
1161 // Hoist the spill of a sib-reg copy.
1162 if (hoistSpill(OldLI, MI)) {
1163 // This COPY is now dead, the value is already in the stack slot.
1164 MI->getOperand(0).setIsDead();
1165 DeadDefs.push_back(MI);
1169 // This is a reload for a sib-reg copy. Drop spills downstream.
1170 LiveInterval &SibLI = LIS.getInterval(SibReg);
1171 eliminateRedundantSpills(SibLI, SibLI.getVNInfoAt(Idx));
1172 // The COPY will fold to a reload below.
1176 // Attempt to fold memory ops.
1177 if (foldMemoryOperand(Ops))
1180 // Allocate interval around instruction.
1181 // FIXME: Infer regclass from instruction alone.
1182 LiveInterval &NewLI = Edit->createFrom(Reg);
1183 NewLI.markNotSpillable();
1186 insertReload(NewLI, Idx, MI);
1188 // Rewrite instruction operands.
1189 bool hasLiveDef = false;
1190 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
1191 MachineOperand &MO = Ops[i].first->getOperand(Ops[i].second);
1192 MO.setReg(NewLI.reg);
1194 if (!Ops[i].first->isRegTiedToDefOperand(Ops[i].second))
1201 DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI);
1203 // FIXME: Use a second vreg if instruction has no tied ops.
1206 insertSpill(NewLI, OldLI, Idx, MI);
1208 // This instruction defines a dead value. We don't need to spill it,
1209 // but do create a live range for the dead value.
1210 VNInfo *VNI = NewLI.getNextValue(Idx, LIS.getVNInfoAllocator());
1211 NewLI.addRange(LiveRange(Idx, Idx.getDeadSlot(), VNI));
1215 DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
1219 /// spillAll - Spill all registers remaining after rematerialization.
1220 void InlineSpiller::spillAll() {
1221 // Update LiveStacks now that we are committed to spilling.
1222 if (StackSlot == VirtRegMap::NO_STACK_SLOT) {
1223 StackSlot = VRM.assignVirt2StackSlot(Original);
1224 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original));
1225 StackInt->getNextValue(SlotIndex(), LSS.getVNInfoAllocator());
1227 StackInt = &LSS.getInterval(StackSlot);
1229 if (Original != Edit->getReg())
1230 VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot);
1232 assert(StackInt->getNumValNums() == 1 && "Bad stack interval values");
1233 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
1234 StackInt->MergeRangesInAsValue(LIS.getInterval(RegsToSpill[i]),
1235 StackInt->getValNumInfo(0));
1236 DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n');
1238 // Spill around uses of all RegsToSpill.
1239 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
1240 spillAroundUses(RegsToSpill[i]);
1242 // Hoisted spills may cause dead code.
1243 if (!DeadDefs.empty()) {
1244 DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n");
1245 Edit->eliminateDeadDefs(DeadDefs, RegsToSpill);
1248 // Finally delete the SnippetCopies.
1249 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
1250 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(RegsToSpill[i]);
1251 MachineInstr *MI = RI.skipInstruction();) {
1252 assert(SnippetCopies.count(MI) && "Remaining use wasn't a snippet copy");
1253 // FIXME: Do this with a LiveRangeEdit callback.
1254 LIS.RemoveMachineInstrFromMaps(MI);
1255 MI->eraseFromParent();
1259 // Delete all spilled registers.
1260 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
1261 Edit->eraseVirtReg(RegsToSpill[i]);
1264 void InlineSpiller::spill(LiveRangeEdit &edit) {
1267 assert(!TargetRegisterInfo::isStackSlot(edit.getReg())
1268 && "Trying to spill a stack slot.");
1269 // Share a stack slot among all descendants of Original.
1270 Original = VRM.getOriginal(edit.getReg());
1271 StackSlot = VRM.getStackSlot(Original);
1274 DEBUG(dbgs() << "Inline spilling "
1275 << MRI.getRegClass(edit.getReg())->getName()
1276 << ':' << edit.getParent() << "\nFrom original "
1277 << LIS.getInterval(Original) << '\n');
1278 assert(edit.getParent().isSpillable() &&
1279 "Attempting to spill already spilled value.");
1280 assert(DeadDefs.empty() && "Previous spill didn't remove dead defs");
1282 collectRegsToSpill();
1283 analyzeSiblingValues();
1286 // Remat may handle everything.
1287 if (!RegsToSpill.empty())
1290 Edit->calculateRegClassAndHint(MF, Loops);