1 //===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The inline spiller modifies the machine function directly instead of
11 // inserting spills and restores in VirtRegMap.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
17 #include "LiveRangeEdit.h"
18 #include "VirtRegMap.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/LiveStackAnalysis.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineLoopInfo.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/raw_ostream.h"
35 class InlineSpiller : public Spiller {
36 MachineFunctionPass &Pass;
41 MachineDominatorTree &MDT;
42 MachineLoopInfo &Loops;
44 MachineFrameInfo &MFI;
45 MachineRegisterInfo &MRI;
46 const TargetInstrInfo &TII;
47 const TargetRegisterInfo &TRI;
49 // Variables that are valid during spill(), but used by multiple methods.
51 LiveInterval *StackInt;
55 // All registers to spill to StackSlot, including the main register.
56 SmallVector<unsigned, 8> RegsToSpill;
58 // All COPY instructions to/from snippets.
59 // They are ignored since both operands refer to the same stack slot.
60 SmallPtrSet<MachineInstr*, 8> SnippetCopies;
62 // Values that failed to remat at some point.
63 SmallPtrSet<VNInfo*, 8> UsedValues;
65 // Information about a value that was defined by a copy from a sibling
68 // True when all reaching defs were reloads: No spill is necessary.
69 bool AllDefsAreReloads;
71 // The preferred register to spill.
74 // The value of SpillReg that should be spilled.
77 // A defining instruction that is not a sibling copy or a reload, or NULL.
78 // This can be used as a template for rematerialization.
81 SibValueInfo(unsigned Reg, VNInfo *VNI)
82 : AllDefsAreReloads(false), SpillReg(Reg), SpillVNI(VNI), DefMI(0) {}
85 // Values in RegsToSpill defined by sibling copies.
86 typedef DenseMap<VNInfo*, SibValueInfo> SibValueMap;
87 SibValueMap SibValues;
89 // Dead defs generated during spilling.
90 SmallVector<MachineInstr*, 8> DeadDefs;
95 InlineSpiller(MachineFunctionPass &pass,
100 LIS(pass.getAnalysis<LiveIntervals>()),
101 LSS(pass.getAnalysis<LiveStacks>()),
102 AA(&pass.getAnalysis<AliasAnalysis>()),
103 MDT(pass.getAnalysis<MachineDominatorTree>()),
104 Loops(pass.getAnalysis<MachineLoopInfo>()),
106 MFI(*mf.getFrameInfo()),
107 MRI(mf.getRegInfo()),
108 TII(*mf.getTarget().getInstrInfo()),
109 TRI(*mf.getTarget().getRegisterInfo()) {}
111 void spill(LiveRangeEdit &);
114 bool isSnippet(const LiveInterval &SnipLI);
115 void collectRegsToSpill();
117 bool isRegToSpill(unsigned Reg) {
118 return std::find(RegsToSpill.begin(),
119 RegsToSpill.end(), Reg) != RegsToSpill.end();
122 bool isSibling(unsigned Reg);
123 MachineInstr *traceSiblingValue(unsigned, VNInfo*, VNInfo*);
124 void analyzeSiblingValues();
126 bool hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI);
127 void eliminateRedundantSpills(LiveInterval &LI, VNInfo *VNI);
129 void markValueUsed(LiveInterval*, VNInfo*);
130 bool reMaterializeFor(LiveInterval&, MachineBasicBlock::iterator MI);
131 void reMaterializeAll();
133 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
134 bool foldMemoryOperand(MachineBasicBlock::iterator MI,
135 const SmallVectorImpl<unsigned> &Ops,
136 MachineInstr *LoadMI = 0);
137 void insertReload(LiveInterval &NewLI, SlotIndex,
138 MachineBasicBlock::iterator MI);
139 void insertSpill(LiveInterval &NewLI, const LiveInterval &OldLI,
140 SlotIndex, MachineBasicBlock::iterator MI);
142 void spillAroundUses(unsigned Reg);
148 Spiller *createInlineSpiller(MachineFunctionPass &pass,
151 return new InlineSpiller(pass, mf, vrm);
155 //===----------------------------------------------------------------------===//
157 //===----------------------------------------------------------------------===//
159 // When spilling a virtual register, we also spill any snippets it is connected
160 // to. The snippets are small live ranges that only have a single real use,
161 // leftovers from live range splitting. Spilling them enables memory operand
162 // folding or tightens the live range around the single use.
164 // This minimizes register pressure and maximizes the store-to-load distance for
165 // spill slots which can be important in tight loops.
167 /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
168 /// otherwise return 0.
169 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) {
172 if (MI->getOperand(0).getSubReg() != 0)
174 if (MI->getOperand(1).getSubReg() != 0)
176 if (MI->getOperand(0).getReg() == Reg)
177 return MI->getOperand(1).getReg();
178 if (MI->getOperand(1).getReg() == Reg)
179 return MI->getOperand(0).getReg();
183 /// isSnippet - Identify if a live interval is a snippet that should be spilled.
184 /// It is assumed that SnipLI is a virtual register with the same original as
186 bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
187 unsigned Reg = Edit->getReg();
189 // A snippet is a tiny live range with only a single instruction using it
190 // besides copies to/from Reg or spills/fills. We accept:
192 // %snip = COPY %Reg / FILL fi#
194 // %Reg = COPY %snip / SPILL %snip, fi#
196 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
199 MachineInstr *UseMI = 0;
201 // Check that all uses satisfy our criteria.
202 for (MachineRegisterInfo::reg_nodbg_iterator
203 RI = MRI.reg_nodbg_begin(SnipLI.reg);
204 MachineInstr *MI = RI.skipInstruction();) {
206 // Allow copies to/from Reg.
207 if (isFullCopyOf(MI, Reg))
210 // Allow stack slot loads.
212 if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot)
215 // Allow stack slot stores.
216 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
219 // Allow a single additional instruction.
220 if (UseMI && MI != UseMI)
227 /// collectRegsToSpill - Collect live range snippets that only have a single
229 void InlineSpiller::collectRegsToSpill() {
230 unsigned Reg = Edit->getReg();
232 // Main register always spills.
233 RegsToSpill.assign(1, Reg);
234 SnippetCopies.clear();
236 // Snippets all have the same original, so there can't be any for an original
241 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg);
242 MachineInstr *MI = RI.skipInstruction();) {
243 unsigned SnipReg = isFullCopyOf(MI, Reg);
244 if (!isSibling(SnipReg))
246 LiveInterval &SnipLI = LIS.getInterval(SnipReg);
247 if (!isSnippet(SnipLI))
249 SnippetCopies.insert(MI);
250 if (!isRegToSpill(SnipReg))
251 RegsToSpill.push_back(SnipReg);
253 DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n');
258 //===----------------------------------------------------------------------===//
260 //===----------------------------------------------------------------------===//
262 // After live range splitting, some values to be spilled may be defined by
263 // copies from sibling registers. We trace the sibling copies back to the
264 // original value if it still exists. We need it for rematerialization.
266 // Even when the value can't be rematerialized, we still want to determine if
267 // the value has already been spilled, or we may want to hoist the spill from a
270 bool InlineSpiller::isSibling(unsigned Reg) {
271 return TargetRegisterInfo::isVirtualRegister(Reg) &&
272 VRM.getOriginal(Reg) == Original;
275 /// traceSiblingValue - Trace a value that is about to be spilled back to the
276 /// real defining instructions by looking through sibling copies. Always stay
277 /// within the range of OrigVNI so the registers are known to carry the same
280 /// Determine if the value is defined by all reloads, so spilling isn't
281 /// necessary - the value is already in the stack slot.
283 /// Return a defining instruction that may be a candidate for rematerialization.
285 MachineInstr *InlineSpiller::traceSiblingValue(unsigned UseReg, VNInfo *UseVNI,
287 DEBUG(dbgs() << "Tracing value " << PrintReg(UseReg) << ':'
288 << UseVNI->id << '@' << UseVNI->def << '\n');
289 SmallPtrSet<VNInfo*, 8> Visited;
290 SmallVector<std::pair<unsigned, VNInfo*>, 8> WorkList;
291 WorkList.push_back(std::make_pair(UseReg, UseVNI));
293 // Best spill candidate seen so far. This must dominate UseVNI.
294 SibValueInfo SVI(UseReg, UseVNI);
295 MachineBasicBlock *UseMBB = LIS.getMBBFromIndex(UseVNI->def);
296 unsigned SpillDepth = Loops.getLoopDepth(UseMBB);
297 bool SeenOrigPHI = false; // Original PHI met.
302 tie(Reg, VNI) = WorkList.pop_back_val();
303 if (!Visited.insert(VNI))
306 // Is this value a better spill candidate?
307 if (!isRegToSpill(Reg)) {
308 MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
309 if (MBB != UseMBB && MDT.dominates(MBB, UseMBB)) {
310 // This is a valid spill location dominating UseVNI.
311 // Prefer to spill at a smaller loop depth.
312 unsigned Depth = Loops.getLoopDepth(MBB);
313 if (Depth < SpillDepth) {
314 DEBUG(dbgs() << " spill depth " << Depth << ": " << PrintReg(Reg)
315 << ':' << VNI->id << '@' << VNI->def << '\n');
323 // Trace through PHI-defs created by live range splitting.
324 if (VNI->isPHIDef()) {
325 if (VNI->def == OrigVNI->def) {
326 DEBUG(dbgs() << " orig phi value " << PrintReg(Reg) << ':'
327 << VNI->id << '@' << VNI->def << '\n');
331 // Get values live-out of predecessors.
332 LiveInterval &LI = LIS.getInterval(Reg);
333 MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
334 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
335 PE = MBB->pred_end(); PI != PE; ++PI) {
336 VNInfo *PVNI = LI.getVNInfoAt(LIS.getMBBEndIdx(*PI).getPrevSlot());
338 WorkList.push_back(std::make_pair(Reg, PVNI));
343 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
344 assert(MI && "Missing def");
346 // Trace through sibling copies.
347 if (unsigned SrcReg = isFullCopyOf(MI, Reg)) {
348 if (isSibling(SrcReg)) {
349 LiveInterval &SrcLI = LIS.getInterval(SrcReg);
350 VNInfo *SrcVNI = SrcLI.getVNInfoAt(VNI->def.getUseIndex());
351 assert(SrcVNI && "Copy from non-existing value");
352 DEBUG(dbgs() << " copy of " << PrintReg(SrcReg) << ':'
353 << SrcVNI->id << '@' << SrcVNI->def << '\n');
354 WorkList.push_back(std::make_pair(SrcReg, SrcVNI));
359 // Track reachable reloads.
361 if (Reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) {
362 DEBUG(dbgs() << " reload " << PrintReg(Reg) << ':'
363 << VNI->id << "@" << VNI->def << '\n');
364 SVI.AllDefsAreReloads = true;
368 // We have an 'original' def. Don't record trivial cases.
370 DEBUG(dbgs() << "Not a sibling copy.\n");
374 // Potential remat candidate.
375 DEBUG(dbgs() << " def " << PrintReg(Reg) << ':'
376 << VNI->id << '@' << VNI->def << '\t' << *MI);
378 } while (!WorkList.empty());
380 if (SeenOrigPHI || SVI.DefMI)
381 SVI.AllDefsAreReloads = false;
384 if (SVI.AllDefsAreReloads)
385 dbgs() << "All defs are reloads.\n";
387 dbgs() << "Prefer to spill " << PrintReg(SVI.SpillReg) << ':'
388 << SVI.SpillVNI->id << '@' << SVI.SpillVNI->def << '\n';
390 SibValues.insert(std::make_pair(UseVNI, SVI));
394 /// analyzeSiblingValues - Trace values defined by sibling copies back to
395 /// something that isn't a sibling copy.
397 /// Keep track of values that may be rematerializable.
398 void InlineSpiller::analyzeSiblingValues() {
401 // No siblings at all?
402 if (Edit->getReg() == Original)
405 LiveInterval &OrigLI = LIS.getInterval(Original);
406 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
407 unsigned Reg = RegsToSpill[i];
408 LiveInterval &LI = LIS.getInterval(Reg);
409 for (LiveInterval::const_vni_iterator VI = LI.vni_begin(),
410 VE = LI.vni_end(); VI != VE; ++VI) {
414 MachineInstr *DefMI = 0;
415 // Check possible sibling copies.
416 if (VNI->isPHIDef() || VNI->getCopy()) {
417 VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
418 if (OrigVNI->def != VNI->def)
419 DefMI = traceSiblingValue(Reg, VNI, OrigVNI);
421 if (!DefMI && !VNI->isPHIDef())
422 DefMI = LIS.getInstructionFromIndex(VNI->def);
424 Edit->checkRematerializable(VNI, DefMI, TII, AA);
429 /// hoistSpill - Given a sibling copy that defines a value to be spilled, insert
430 /// a spill at a better location.
431 bool InlineSpiller::hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI) {
432 SlotIndex Idx = LIS.getInstructionIndex(CopyMI);
433 VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getDefIndex());
434 assert(VNI && VNI->def == Idx.getDefIndex() && "Not defined by copy");
435 SibValueMap::const_iterator I = SibValues.find(VNI);
436 if (I == SibValues.end())
439 const SibValueInfo &SVI = I->second;
441 // Let the normal folding code deal with the boring case.
442 if (!SVI.AllDefsAreReloads && SVI.SpillVNI == VNI)
445 // Conservatively extend the stack slot range to the range of the original
446 // value. We may be able to do better with stack slot coloring by being more
448 assert(StackInt && "No stack slot assigned yet.");
449 LiveInterval &OrigLI = LIS.getInterval(Original);
450 VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
451 StackInt->MergeValueInAsValue(OrigLI, OrigVNI, StackInt->getValNumInfo(0));
452 DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": "
453 << *StackInt << '\n');
455 // Already spilled everywhere.
456 if (SVI.AllDefsAreReloads)
459 // We are going to spill SVI.SpillVNI immediately after its def, so clear out
460 // any later spills of the same value.
461 eliminateRedundantSpills(LIS.getInterval(SVI.SpillReg), SVI.SpillVNI);
463 MachineBasicBlock *MBB = LIS.getMBBFromIndex(SVI.SpillVNI->def);
464 MachineBasicBlock::iterator MII;
465 if (SVI.SpillVNI->isPHIDef())
466 MII = MBB->SkipPHIsAndLabels(MBB->begin());
468 MII = LIS.getInstructionFromIndex(SVI.SpillVNI->def);
471 // Insert spill without kill flag immediately after def.
472 TII.storeRegToStackSlot(*MBB, MII, SVI.SpillReg, false, StackSlot,
473 MRI.getRegClass(SVI.SpillReg), &TRI);
474 --MII; // Point to store instruction.
475 LIS.InsertMachineInstrInMaps(MII);
476 VRM.addSpillSlotUse(StackSlot, MII);
477 DEBUG(dbgs() << "\thoisted: " << SVI.SpillVNI->def << '\t' << *MII);
481 /// eliminateRedundantSpills - SLI:VNI is known to be on the stack. Remove any
482 /// redundant spills of this value in SLI.reg and sibling copies.
483 void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
484 assert(VNI && "Missing value");
485 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
486 WorkList.push_back(std::make_pair(&SLI, VNI));
487 assert(StackInt && "No stack slot assigned yet.");
491 tie(LI, VNI) = WorkList.pop_back_val();
492 unsigned Reg = LI->reg;
493 DEBUG(dbgs() << "Checking redundant spills for " << PrintReg(Reg) << ':'
494 << VNI->id << '@' << VNI->def << '\n');
496 // Regs to spill are taken care of.
497 if (isRegToSpill(Reg))
500 // Add all of VNI's live range to StackInt.
501 StackInt->MergeValueInAsValue(*LI, VNI, StackInt->getValNumInfo(0));
502 DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n');
504 // Find all spills and copies of VNI.
505 for (MachineRegisterInfo::use_nodbg_iterator UI = MRI.use_nodbg_begin(Reg);
506 MachineInstr *MI = UI.skipInstruction();) {
507 if (!MI->isCopy() && !MI->getDesc().mayStore())
509 SlotIndex Idx = LIS.getInstructionIndex(MI);
510 if (LI->getVNInfoAt(Idx) != VNI)
513 // Follow sibling copies down the dominator tree.
514 if (unsigned DstReg = isFullCopyOf(MI, Reg)) {
515 if (isSibling(DstReg)) {
516 LiveInterval &DstLI = LIS.getInterval(DstReg);
517 VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getDefIndex());
518 assert(DstVNI && "Missing defined value");
519 assert(DstVNI->def == Idx.getDefIndex() && "Wrong copy def slot");
520 WorkList.push_back(std::make_pair(&DstLI, DstVNI));
527 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
528 DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << *MI);
529 // eliminateDeadDefs won't normally remove stores, so switch opcode.
530 MI->setDesc(TII.get(TargetOpcode::KILL));
531 DeadDefs.push_back(MI);
534 } while (!WorkList.empty());
538 //===----------------------------------------------------------------------===//
540 //===----------------------------------------------------------------------===//
542 /// markValueUsed - Remember that VNI failed to rematerialize, so its defining
543 /// instruction cannot be eliminated. See through snippet copies
544 void InlineSpiller::markValueUsed(LiveInterval *LI, VNInfo *VNI) {
545 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
546 WorkList.push_back(std::make_pair(LI, VNI));
548 tie(LI, VNI) = WorkList.pop_back_val();
549 if (!UsedValues.insert(VNI))
552 if (VNI->isPHIDef()) {
553 MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
554 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
555 PE = MBB->pred_end(); PI != PE; ++PI) {
556 VNInfo *PVNI = LI->getVNInfoAt(LIS.getMBBEndIdx(*PI).getPrevSlot());
558 WorkList.push_back(std::make_pair(LI, PVNI));
563 // Follow snippet copies.
564 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
565 if (!SnippetCopies.count(MI))
567 LiveInterval &SnipLI = LIS.getInterval(MI->getOperand(1).getReg());
568 assert(isRegToSpill(SnipLI.reg) && "Unexpected register in copy");
569 VNInfo *SnipVNI = SnipLI.getVNInfoAt(VNI->def.getUseIndex());
570 assert(SnipVNI && "Snippet undefined before copy");
571 WorkList.push_back(std::make_pair(&SnipLI, SnipVNI));
572 } while (!WorkList.empty());
575 /// reMaterializeFor - Attempt to rematerialize before MI instead of reloading.
576 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg,
577 MachineBasicBlock::iterator MI) {
578 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getUseIndex();
579 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx);
582 DEBUG(dbgs() << "\tadding <undef> flags: ");
583 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
584 MachineOperand &MO = MI->getOperand(i);
585 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
588 DEBUG(dbgs() << UseIdx << '\t' << *MI);
592 if (SnippetCopies.count(MI))
595 // Use an OrigVNI from traceSiblingValue when ParentVNI is a sibling copy.
596 LiveRangeEdit::Remat RM(ParentVNI);
597 SibValueMap::const_iterator SibI = SibValues.find(ParentVNI);
598 if (SibI != SibValues.end())
599 RM.OrigMI = SibI->second.DefMI;
600 if (!Edit->canRematerializeAt(RM, UseIdx, false, LIS)) {
601 markValueUsed(&VirtReg, ParentVNI);
602 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
606 // If the instruction also writes VirtReg.reg, it had better not require the
607 // same register for uses and defs.
609 SmallVector<unsigned, 8> Ops;
610 tie(Reads, Writes) = MI->readsWritesVirtualRegister(VirtReg.reg, &Ops);
612 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
613 MachineOperand &MO = MI->getOperand(Ops[i]);
614 if (MO.isUse() ? MI->isRegTiedToDefOperand(Ops[i]) : MO.getSubReg()) {
615 markValueUsed(&VirtReg, ParentVNI);
616 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
622 // Before rematerializing into a register for a single instruction, try to
623 // fold a load into the instruction. That avoids allocating a new register.
624 if (RM.OrigMI->getDesc().canFoldAsLoad() &&
625 foldMemoryOperand(MI, Ops, RM.OrigMI)) {
626 Edit->markRematerialized(RM.ParentVNI);
630 // Alocate a new register for the remat.
631 LiveInterval &NewLI = Edit->createFrom(Original, LIS, VRM);
632 NewLI.markNotSpillable();
634 // Finally we can rematerialize OrigMI before MI.
635 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM,
637 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'
638 << *LIS.getInstructionFromIndex(DefIdx));
641 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
642 MachineOperand &MO = MI->getOperand(Ops[i]);
643 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
644 MO.setReg(NewLI.reg);
648 DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI);
650 VNInfo *DefVNI = NewLI.getNextValue(DefIdx, 0, LIS.getVNInfoAllocator());
651 NewLI.addRange(LiveRange(DefIdx, UseIdx.getDefIndex(), DefVNI));
652 DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
656 /// reMaterializeAll - Try to rematerialize as many uses as possible,
657 /// and trim the live ranges after.
658 void InlineSpiller::reMaterializeAll() {
659 // analyzeSiblingValues has already tested all relevant defining instructions.
660 if (!Edit->anyRematerializable(LIS, TII, AA))
665 // Try to remat before all uses of snippets.
666 bool anyRemat = false;
667 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
668 unsigned Reg = RegsToSpill[i];
669 LiveInterval &LI = LIS.getInterval(Reg);
670 for (MachineRegisterInfo::use_nodbg_iterator
671 RI = MRI.use_nodbg_begin(Reg);
672 MachineInstr *MI = RI.skipInstruction();)
673 anyRemat |= reMaterializeFor(LI, MI);
678 // Remove any values that were completely rematted.
679 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
680 unsigned Reg = RegsToSpill[i];
681 LiveInterval &LI = LIS.getInterval(Reg);
682 for (LiveInterval::vni_iterator I = LI.vni_begin(), E = LI.vni_end();
685 if (VNI->isUnused() || VNI->isPHIDef() || UsedValues.count(VNI))
687 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
688 MI->addRegisterDead(Reg, &TRI);
689 if (!MI->allDefsAreDead())
691 DEBUG(dbgs() << "All defs dead: " << *MI);
692 DeadDefs.push_back(MI);
696 // Eliminate dead code after remat. Note that some snippet copies may be
698 if (DeadDefs.empty())
700 DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n");
701 Edit->eliminateDeadDefs(DeadDefs, LIS, VRM, TII);
703 // Get rid of deleted and empty intervals.
704 for (unsigned i = RegsToSpill.size(); i != 0; --i) {
705 unsigned Reg = RegsToSpill[i-1];
706 if (!LIS.hasInterval(Reg)) {
707 RegsToSpill.erase(RegsToSpill.begin() + (i - 1));
710 LiveInterval &LI = LIS.getInterval(Reg);
713 Edit->eraseVirtReg(Reg, LIS);
714 RegsToSpill.erase(RegsToSpill.begin() + (i - 1));
716 DEBUG(dbgs() << RegsToSpill.size() << " registers to spill after remat.\n");
720 //===----------------------------------------------------------------------===//
722 //===----------------------------------------------------------------------===//
724 /// If MI is a load or store of StackSlot, it can be removed.
725 bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
728 if (!(InstrReg = TII.isLoadFromStackSlot(MI, FI)) &&
729 !(InstrReg = TII.isStoreToStackSlot(MI, FI)))
732 // We have a stack access. Is it the right register and slot?
733 if (InstrReg != Reg || FI != StackSlot)
736 DEBUG(dbgs() << "Coalescing stack access: " << *MI);
737 LIS.RemoveMachineInstrFromMaps(MI);
738 MI->eraseFromParent();
742 /// foldMemoryOperand - Try folding stack slot references in Ops into MI.
743 /// @param MI Instruction using or defining the current register.
744 /// @param Ops Operand indices from readsWritesVirtualRegister().
745 /// @param LoadMI Load instruction to use instead of stack slot when non-null.
746 /// @return True on success, and MI will be erased.
747 bool InlineSpiller::foldMemoryOperand(MachineBasicBlock::iterator MI,
748 const SmallVectorImpl<unsigned> &Ops,
749 MachineInstr *LoadMI) {
750 // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
752 SmallVector<unsigned, 8> FoldOps;
753 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
754 unsigned Idx = Ops[i];
755 MachineOperand &MO = MI->getOperand(Idx);
758 // FIXME: Teach targets to deal with subregs.
761 // We cannot fold a load instruction into a def.
762 if (LoadMI && MO.isDef())
764 // Tied use operands should not be passed to foldMemoryOperand.
765 if (!MI->isRegTiedToDefOperand(Idx))
766 FoldOps.push_back(Idx);
769 MachineInstr *FoldMI =
770 LoadMI ? TII.foldMemoryOperand(MI, FoldOps, LoadMI)
771 : TII.foldMemoryOperand(MI, FoldOps, StackSlot);
774 LIS.ReplaceMachineInstrInMaps(MI, FoldMI);
776 VRM.addSpillSlotUse(StackSlot, FoldMI);
777 MI->eraseFromParent();
778 DEBUG(dbgs() << "\tfolded: " << *FoldMI);
782 /// insertReload - Insert a reload of NewLI.reg before MI.
783 void InlineSpiller::insertReload(LiveInterval &NewLI,
785 MachineBasicBlock::iterator MI) {
786 MachineBasicBlock &MBB = *MI->getParent();
787 TII.loadRegFromStackSlot(MBB, MI, NewLI.reg, StackSlot,
788 MRI.getRegClass(NewLI.reg), &TRI);
789 --MI; // Point to load instruction.
790 SlotIndex LoadIdx = LIS.InsertMachineInstrInMaps(MI).getDefIndex();
791 VRM.addSpillSlotUse(StackSlot, MI);
792 DEBUG(dbgs() << "\treload: " << LoadIdx << '\t' << *MI);
793 VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0,
794 LIS.getVNInfoAllocator());
795 NewLI.addRange(LiveRange(LoadIdx, Idx, LoadVNI));
798 /// insertSpill - Insert a spill of NewLI.reg after MI.
799 void InlineSpiller::insertSpill(LiveInterval &NewLI, const LiveInterval &OldLI,
800 SlotIndex Idx, MachineBasicBlock::iterator MI) {
801 MachineBasicBlock &MBB = *MI->getParent();
802 TII.storeRegToStackSlot(MBB, ++MI, NewLI.reg, true, StackSlot,
803 MRI.getRegClass(NewLI.reg), &TRI);
804 --MI; // Point to store instruction.
805 SlotIndex StoreIdx = LIS.InsertMachineInstrInMaps(MI).getDefIndex();
806 VRM.addSpillSlotUse(StackSlot, MI);
807 DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MI);
808 VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, LIS.getVNInfoAllocator());
809 NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
812 /// spillAroundUses - insert spill code around each use of Reg.
813 void InlineSpiller::spillAroundUses(unsigned Reg) {
814 LiveInterval &OldLI = LIS.getInterval(Reg);
816 // Iterate over instructions using Reg.
817 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg);
818 MachineInstr *MI = RI.skipInstruction();) {
820 // Debug values are not allowed to affect codegen.
821 if (MI->isDebugValue()) {
822 // Modify DBG_VALUE now that the value is in a spill slot.
823 uint64_t Offset = MI->getOperand(1).getImm();
824 const MDNode *MDPtr = MI->getOperand(2).getMetadata();
825 DebugLoc DL = MI->getDebugLoc();
826 if (MachineInstr *NewDV = TII.emitFrameIndexDebugValue(MF, StackSlot,
827 Offset, MDPtr, DL)) {
828 DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
829 MachineBasicBlock *MBB = MI->getParent();
830 MBB->insert(MBB->erase(MI), NewDV);
832 DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI);
833 MI->eraseFromParent();
838 // Ignore copies to/from snippets. We'll delete them.
839 if (SnippetCopies.count(MI))
842 // Stack slot accesses may coalesce away.
843 if (coalesceStackAccess(MI, Reg))
846 // Analyze instruction.
848 SmallVector<unsigned, 8> Ops;
849 tie(Reads, Writes) = MI->readsWritesVirtualRegister(Reg, &Ops);
851 // Find the slot index where this instruction reads and writes OldLI.
852 // This is usually the def slot, except for tied early clobbers.
853 SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
854 if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getUseIndex()))
855 if (SlotIndex::isSameInstr(Idx, VNI->def))
858 // Check for a sibling copy.
859 unsigned SibReg = isFullCopyOf(MI, Reg);
860 if (SibReg && isSibling(SibReg)) {
862 // Hoist the spill of a sib-reg copy.
863 if (hoistSpill(OldLI, MI)) {
864 // This COPY is now dead, the value is already in the stack slot.
865 MI->getOperand(0).setIsDead();
866 DeadDefs.push_back(MI);
870 // This is a reload for a sib-reg copy. Drop spills downstream.
871 LiveInterval &SibLI = LIS.getInterval(SibReg);
872 eliminateRedundantSpills(SibLI, SibLI.getVNInfoAt(Idx));
873 // The COPY will fold to a reload below.
877 // Attempt to fold memory ops.
878 if (foldMemoryOperand(MI, Ops))
881 // Allocate interval around instruction.
882 // FIXME: Infer regclass from instruction alone.
883 LiveInterval &NewLI = Edit->createFrom(Reg, LIS, VRM);
884 NewLI.markNotSpillable();
887 insertReload(NewLI, Idx, MI);
889 // Rewrite instruction operands.
890 bool hasLiveDef = false;
891 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
892 MachineOperand &MO = MI->getOperand(Ops[i]);
893 MO.setReg(NewLI.reg);
895 if (!MI->isRegTiedToDefOperand(Ops[i]))
902 DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI);
904 // FIXME: Use a second vreg if instruction has no tied ops.
905 if (Writes && hasLiveDef)
906 insertSpill(NewLI, OldLI, Idx, MI);
908 DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
912 /// spillAll - Spill all registers remaining after rematerialization.
913 void InlineSpiller::spillAll() {
914 // Update LiveStacks now that we are committed to spilling.
915 if (StackSlot == VirtRegMap::NO_STACK_SLOT) {
916 StackSlot = VRM.assignVirt2StackSlot(Original);
917 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original));
918 StackInt->getNextValue(SlotIndex(), 0, LSS.getVNInfoAllocator());
920 StackInt = &LSS.getInterval(StackSlot);
922 if (Original != Edit->getReg())
923 VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot);
925 assert(StackInt->getNumValNums() == 1 && "Bad stack interval values");
926 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
927 StackInt->MergeRangesInAsValue(LIS.getInterval(RegsToSpill[i]),
928 StackInt->getValNumInfo(0));
929 DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n');
931 // Spill around uses of all RegsToSpill.
932 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
933 spillAroundUses(RegsToSpill[i]);
935 // Hoisted spills may cause dead code.
936 if (!DeadDefs.empty()) {
937 DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n");
938 Edit->eliminateDeadDefs(DeadDefs, LIS, VRM, TII);
941 // Finally delete the SnippetCopies.
942 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg());
943 MachineInstr *MI = RI.skipInstruction();) {
944 assert(SnippetCopies.count(MI) && "Remaining use wasn't a snippet copy");
945 // FIXME: Do this with a LiveRangeEdit callback.
946 VRM.RemoveMachineInstrFromMaps(MI);
947 LIS.RemoveMachineInstrFromMaps(MI);
948 MI->eraseFromParent();
951 // Delete all spilled registers.
952 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
953 Edit->eraseVirtReg(RegsToSpill[i], LIS);
956 void InlineSpiller::spill(LiveRangeEdit &edit) {
958 assert(!TargetRegisterInfo::isStackSlot(edit.getReg())
959 && "Trying to spill a stack slot.");
960 // Share a stack slot among all descendants of Original.
961 Original = VRM.getOriginal(edit.getReg());
962 StackSlot = VRM.getStackSlot(Original);
965 DEBUG(dbgs() << "Inline spilling "
966 << MRI.getRegClass(edit.getReg())->getName()
967 << ':' << edit.getParent() << "\nFrom original "
968 << LIS.getInterval(Original) << '\n');
969 assert(edit.getParent().isSpillable() &&
970 "Attempting to spill already spilled value.");
971 assert(DeadDefs.empty() && "Previous spill didn't remove dead defs");
973 collectRegsToSpill();
974 analyzeSiblingValues();
977 // Remat may handle everything.
978 if (!RegsToSpill.empty())
981 Edit->calculateRegClassAndHint(MF, LIS, Loops);