1 //===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The inline spiller modifies the machine function directly instead of
11 // inserting spills and restores in VirtRegMap.
13 //===----------------------------------------------------------------------===//
16 #include "llvm/ADT/SetVector.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/ADT/TinyPtrVector.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/LiveRangeEdit.h"
22 #include "llvm/CodeGen/LiveStackAnalysis.h"
23 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
24 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineInstrBundle.h"
30 #include "llvm/CodeGen/MachineLoopInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/VirtRegMap.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetInstrInfo.h"
40 #define DEBUG_TYPE "regalloc"
42 STATISTIC(NumSpilledRanges, "Number of spilled live ranges");
43 STATISTIC(NumSnippets, "Number of spilled snippets");
44 STATISTIC(NumSpills, "Number of spills inserted");
45 STATISTIC(NumSpillsRemoved, "Number of spills removed");
46 STATISTIC(NumReloads, "Number of reloads inserted");
47 STATISTIC(NumReloadsRemoved, "Number of reloads removed");
48 STATISTIC(NumFolded, "Number of folded stack accesses");
49 STATISTIC(NumFoldedLoads, "Number of folded loads");
50 STATISTIC(NumRemats, "Number of rematerialized defs for spilling");
51 STATISTIC(NumOmitReloadSpill, "Number of omitted spills of reloads");
52 STATISTIC(NumHoists, "Number of hoisted spills");
54 static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden,
55 cl::desc("Disable inline spill hoisting"));
58 class InlineSpiller : public Spiller {
63 MachineDominatorTree &MDT;
64 MachineLoopInfo &Loops;
66 MachineFrameInfo &MFI;
67 MachineRegisterInfo &MRI;
68 const TargetInstrInfo &TII;
69 const TargetRegisterInfo &TRI;
70 const MachineBlockFrequencyInfo &MBFI;
72 // Variables that are valid during spill(), but used by multiple methods.
74 LiveInterval *StackInt;
78 // All registers to spill to StackSlot, including the main register.
79 SmallVector<unsigned, 8> RegsToSpill;
81 // All COPY instructions to/from snippets.
82 // They are ignored since both operands refer to the same stack slot.
83 SmallPtrSet<MachineInstr*, 8> SnippetCopies;
85 // Values that failed to remat at some point.
86 SmallPtrSet<VNInfo*, 8> UsedValues;
89 // Information about a value that was defined by a copy from a sibling
92 // True when all reaching defs were reloads: No spill is necessary.
93 bool AllDefsAreReloads;
95 // True when value is defined by an original PHI not from splitting.
98 // True when the COPY defining this value killed its source.
101 // The preferred register to spill.
104 // The value of SpillReg that should be spilled.
107 // The block where SpillVNI should be spilled. Currently, this must be the
108 // block containing SpillVNI->def.
109 MachineBasicBlock *SpillMBB;
111 // A defining instruction that is not a sibling copy or a reload, or NULL.
112 // This can be used as a template for rematerialization.
115 // List of values that depend on this one. These values are actually the
116 // same, but live range splitting has placed them in different registers,
117 // or SSA update needed to insert PHI-defs to preserve SSA form. This is
118 // copies of the current value and phi-kills. Usually only phi-kills cause
119 // more than one dependent value.
120 TinyPtrVector<VNInfo*> Deps;
122 SibValueInfo(unsigned Reg, VNInfo *VNI)
123 : AllDefsAreReloads(true), DefByOrigPHI(false), KillsSource(false),
124 SpillReg(Reg), SpillVNI(VNI), SpillMBB(nullptr), DefMI(nullptr) {}
126 // Returns true when a def has been found.
127 bool hasDef() const { return DefByOrigPHI || DefMI; }
131 // Values in RegsToSpill defined by sibling copies.
132 typedef DenseMap<VNInfo*, SibValueInfo> SibValueMap;
133 SibValueMap SibValues;
135 // Dead defs generated during spilling.
136 SmallVector<MachineInstr*, 8> DeadDefs;
138 ~InlineSpiller() override {}
141 InlineSpiller(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
142 : MF(mf), LIS(pass.getAnalysis<LiveIntervals>()),
143 LSS(pass.getAnalysis<LiveStacks>()),
144 AA(&pass.getAnalysis<AAResultsWrapperPass>().getAAResults()),
145 MDT(pass.getAnalysis<MachineDominatorTree>()),
146 Loops(pass.getAnalysis<MachineLoopInfo>()), VRM(vrm),
147 MFI(*mf.getFrameInfo()), MRI(mf.getRegInfo()),
148 TII(*mf.getSubtarget().getInstrInfo()),
149 TRI(*mf.getSubtarget().getRegisterInfo()),
150 MBFI(pass.getAnalysis<MachineBlockFrequencyInfo>()) {}
152 void spill(LiveRangeEdit &) override;
155 bool isSnippet(const LiveInterval &SnipLI);
156 void collectRegsToSpill();
158 bool isRegToSpill(unsigned Reg) {
159 return std::find(RegsToSpill.begin(),
160 RegsToSpill.end(), Reg) != RegsToSpill.end();
163 bool isSibling(unsigned Reg);
164 MachineInstr *traceSiblingValue(unsigned, VNInfo*, VNInfo*);
165 void propagateSiblingValue(SibValueMap::iterator, VNInfo *VNI = nullptr);
166 void analyzeSiblingValues();
168 bool hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI);
169 void eliminateRedundantSpills(LiveInterval &LI, VNInfo *VNI);
171 void markValueUsed(LiveInterval*, VNInfo*);
172 bool reMaterializeFor(LiveInterval&, MachineBasicBlock::iterator MI);
173 void reMaterializeAll();
175 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
176 bool foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> >,
177 MachineInstr *LoadMI = nullptr);
178 void insertReload(unsigned VReg, SlotIndex, MachineBasicBlock::iterator MI);
179 void insertSpill(unsigned VReg, bool isKill, MachineBasicBlock::iterator MI);
181 void spillAroundUses(unsigned Reg);
188 Spiller::~Spiller() { }
189 void Spiller::anchor() { }
191 Spiller *createInlineSpiller(MachineFunctionPass &pass,
194 return new InlineSpiller(pass, mf, vrm);
199 //===----------------------------------------------------------------------===//
201 //===----------------------------------------------------------------------===//
203 // When spilling a virtual register, we also spill any snippets it is connected
204 // to. The snippets are small live ranges that only have a single real use,
205 // leftovers from live range splitting. Spilling them enables memory operand
206 // folding or tightens the live range around the single use.
208 // This minimizes register pressure and maximizes the store-to-load distance for
209 // spill slots which can be important in tight loops.
211 /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
212 /// otherwise return 0.
213 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) {
214 if (!MI->isFullCopy())
216 if (MI->getOperand(0).getReg() == Reg)
217 return MI->getOperand(1).getReg();
218 if (MI->getOperand(1).getReg() == Reg)
219 return MI->getOperand(0).getReg();
223 /// isSnippet - Identify if a live interval is a snippet that should be spilled.
224 /// It is assumed that SnipLI is a virtual register with the same original as
226 bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
227 unsigned Reg = Edit->getReg();
229 // A snippet is a tiny live range with only a single instruction using it
230 // besides copies to/from Reg or spills/fills. We accept:
232 // %snip = COPY %Reg / FILL fi#
234 // %Reg = COPY %snip / SPILL %snip, fi#
236 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
239 MachineInstr *UseMI = nullptr;
241 // Check that all uses satisfy our criteria.
242 for (MachineRegisterInfo::reg_instr_nodbg_iterator
243 RI = MRI.reg_instr_nodbg_begin(SnipLI.reg),
244 E = MRI.reg_instr_nodbg_end(); RI != E; ) {
245 MachineInstr *MI = &*(RI++);
247 // Allow copies to/from Reg.
248 if (isFullCopyOf(MI, Reg))
251 // Allow stack slot loads.
253 if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot)
256 // Allow stack slot stores.
257 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
260 // Allow a single additional instruction.
261 if (UseMI && MI != UseMI)
268 /// collectRegsToSpill - Collect live range snippets that only have a single
270 void InlineSpiller::collectRegsToSpill() {
271 unsigned Reg = Edit->getReg();
273 // Main register always spills.
274 RegsToSpill.assign(1, Reg);
275 SnippetCopies.clear();
277 // Snippets all have the same original, so there can't be any for an original
282 for (MachineRegisterInfo::reg_instr_iterator
283 RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end(); RI != E; ) {
284 MachineInstr *MI = &*(RI++);
285 unsigned SnipReg = isFullCopyOf(MI, Reg);
286 if (!isSibling(SnipReg))
288 LiveInterval &SnipLI = LIS.getInterval(SnipReg);
289 if (!isSnippet(SnipLI))
291 SnippetCopies.insert(MI);
292 if (isRegToSpill(SnipReg))
294 RegsToSpill.push_back(SnipReg);
295 DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n');
301 //===----------------------------------------------------------------------===//
303 //===----------------------------------------------------------------------===//
305 // After live range splitting, some values to be spilled may be defined by
306 // copies from sibling registers. We trace the sibling copies back to the
307 // original value if it still exists. We need it for rematerialization.
309 // Even when the value can't be rematerialized, we still want to determine if
310 // the value has already been spilled, or we may want to hoist the spill from a
313 bool InlineSpiller::isSibling(unsigned Reg) {
314 return TargetRegisterInfo::isVirtualRegister(Reg) &&
315 VRM.getOriginal(Reg) == Original;
319 static raw_ostream &operator<<(raw_ostream &OS,
320 const InlineSpiller::SibValueInfo &SVI) {
321 OS << "spill " << PrintReg(SVI.SpillReg) << ':'
322 << SVI.SpillVNI->id << '@' << SVI.SpillVNI->def;
324 OS << " in BB#" << SVI.SpillMBB->getNumber();
325 if (SVI.AllDefsAreReloads)
326 OS << " all-reloads";
327 if (SVI.DefByOrigPHI)
332 for (VNInfo *Dep : SVI.Deps)
333 OS << ' ' << Dep->id << '@' << Dep->def;
336 OS << " def: " << *SVI.DefMI;
343 /// propagateSiblingValue - Propagate the value in SVI to dependents if it is
344 /// known. Otherwise remember the dependency for later.
346 /// @param SVIIter SibValues entry to propagate.
347 /// @param VNI Dependent value, or NULL to propagate to all saved dependents.
348 void InlineSpiller::propagateSiblingValue(SibValueMap::iterator SVIIter,
350 SibValueMap::value_type *SVI = &*SVIIter;
352 // When VNI is non-NULL, add it to SVI's deps, and only propagate to that.
353 TinyPtrVector<VNInfo*> FirstDeps;
355 FirstDeps.push_back(VNI);
356 SVI->second.Deps.push_back(VNI);
359 // Has the value been completely determined yet? If not, defer propagation.
360 if (!SVI->second.hasDef())
363 // Work list of values to propagate.
364 SmallSetVector<SibValueMap::value_type *, 8> WorkList;
365 WorkList.insert(SVI);
368 SVI = WorkList.pop_back_val();
369 TinyPtrVector<VNInfo*> *Deps = VNI ? &FirstDeps : &SVI->second.Deps;
372 SibValueInfo &SV = SVI->second;
374 SV.SpillMBB = LIS.getMBBFromIndex(SV.SpillVNI->def);
376 DEBUG(dbgs() << " prop to " << Deps->size() << ": "
377 << SVI->first->id << '@' << SVI->first->def << ":\t" << SV);
379 assert(SV.hasDef() && "Propagating undefined value");
381 // Should this value be propagated as a preferred spill candidate? We don't
382 // propagate values of registers that are about to spill.
383 bool PropSpill = !DisableHoisting && !isRegToSpill(SV.SpillReg);
384 unsigned SpillDepth = ~0u;
386 for (VNInfo *Dep : *Deps) {
387 SibValueMap::iterator DepSVI = SibValues.find(Dep);
388 assert(DepSVI != SibValues.end() && "Dependent value not in SibValues");
389 SibValueInfo &DepSV = DepSVI->second;
391 DepSV.SpillMBB = LIS.getMBBFromIndex(DepSV.SpillVNI->def);
393 bool Changed = false;
395 // Propagate defining instruction.
396 if (!DepSV.hasDef()) {
398 DepSV.DefMI = SV.DefMI;
399 DepSV.DefByOrigPHI = SV.DefByOrigPHI;
402 // Propagate AllDefsAreReloads. For PHI values, this computes an AND of
404 if (!SV.AllDefsAreReloads && DepSV.AllDefsAreReloads) {
406 DepSV.AllDefsAreReloads = false;
409 // Propagate best spill value.
410 if (PropSpill && SV.SpillVNI != DepSV.SpillVNI) {
411 if (SV.SpillMBB == DepSV.SpillMBB) {
412 // DepSV is in the same block. Hoist when dominated.
413 if (DepSV.KillsSource && SV.SpillVNI->def < DepSV.SpillVNI->def) {
414 // This is an alternative def earlier in the same MBB.
415 // Hoist the spill as far as possible in SpillMBB. This can ease
416 // register pressure:
422 // Hoisting the spill of s to immediately after the def removes the
423 // interference between x and y:
429 // This hoist only helps when the DepSV copy kills its source.
431 DepSV.SpillReg = SV.SpillReg;
432 DepSV.SpillVNI = SV.SpillVNI;
433 DepSV.SpillMBB = SV.SpillMBB;
436 // DepSV is in a different block.
437 if (SpillDepth == ~0u)
438 SpillDepth = Loops.getLoopDepth(SV.SpillMBB);
440 // Also hoist spills to blocks with smaller loop depth, but make sure
441 // that the new value dominates. Non-phi dependents are always
442 // dominated, phis need checking.
444 const BranchProbability MarginProb(4, 5); // 80%
445 // Hoist a spill to outer loop if there are multiple dependents (it
446 // can be beneficial if more than one dependents are hoisted) or
447 // if DepSV (the hoisting source) is hotter than SV (the hoisting
448 // destination) (we add a 80% margin to bias a little towards
450 bool HoistCondition =
451 (MBFI.getBlockFreq(DepSV.SpillMBB) >=
452 (MBFI.getBlockFreq(SV.SpillMBB) * MarginProb)) ||
455 if ((Loops.getLoopDepth(DepSV.SpillMBB) > SpillDepth) &&
457 (!DepSVI->first->isPHIDef() ||
458 MDT.dominates(SV.SpillMBB, DepSV.SpillMBB))) {
460 DepSV.SpillReg = SV.SpillReg;
461 DepSV.SpillVNI = SV.SpillVNI;
462 DepSV.SpillMBB = SV.SpillMBB;
470 // Something changed in DepSVI. Propagate to dependents.
471 WorkList.insert(&*DepSVI);
473 DEBUG(dbgs() << " update " << DepSVI->first->id << '@'
474 << DepSVI->first->def << " to:\t" << DepSV);
476 } while (!WorkList.empty());
479 /// traceSiblingValue - Trace a value that is about to be spilled back to the
480 /// real defining instructions by looking through sibling copies. Always stay
481 /// within the range of OrigVNI so the registers are known to carry the same
484 /// Determine if the value is defined by all reloads, so spilling isn't
485 /// necessary - the value is already in the stack slot.
487 /// Return a defining instruction that may be a candidate for rematerialization.
489 MachineInstr *InlineSpiller::traceSiblingValue(unsigned UseReg, VNInfo *UseVNI,
491 // Check if a cached value already exists.
492 SibValueMap::iterator SVI;
494 std::tie(SVI, Inserted) =
495 SibValues.insert(std::make_pair(UseVNI, SibValueInfo(UseReg, UseVNI)));
497 DEBUG(dbgs() << "Cached value " << PrintReg(UseReg) << ':'
498 << UseVNI->id << '@' << UseVNI->def << ' ' << SVI->second);
499 return SVI->second.DefMI;
502 DEBUG(dbgs() << "Tracing value " << PrintReg(UseReg) << ':'
503 << UseVNI->id << '@' << UseVNI->def << '\n');
505 // List of (Reg, VNI) that have been inserted into SibValues, but need to be
507 SmallVector<std::pair<unsigned, VNInfo*>, 8> WorkList;
508 WorkList.push_back(std::make_pair(UseReg, UseVNI));
510 LiveInterval &OrigLI = LIS.getInterval(Original);
514 std::tie(Reg, VNI) = WorkList.pop_back_val();
515 DEBUG(dbgs() << " " << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def
518 // First check if this value has already been computed.
519 SVI = SibValues.find(VNI);
520 assert(SVI != SibValues.end() && "Missing SibValues entry");
522 // Trace through PHI-defs created by live range splitting.
523 if (VNI->isPHIDef()) {
524 // Stop at original PHIs. We don't know the value at the
525 // predecessors. Look up the VNInfo for the current definition
526 // in OrigLI, to properly determine whether or not this phi was
527 // added by splitting.
528 if (VNI->def == OrigLI.getVNInfoAt(VNI->def)->def) {
529 DEBUG(dbgs() << "orig phi value\n");
530 SVI->second.DefByOrigPHI = true;
531 SVI->second.AllDefsAreReloads = false;
532 propagateSiblingValue(SVI);
536 // This is a PHI inserted by live range splitting. We could trace the
537 // live-out value from predecessor blocks, but that search can be very
538 // expensive if there are many predecessors and many more PHIs as
539 // generated by tail-dup when it sees an indirectbr. Instead, look at
540 // all the non-PHI defs that have the same value as OrigVNI. They must
541 // jointly dominate VNI->def. This is not optimal since VNI may actually
542 // be jointly dominated by a smaller subset of defs, so there is a change
543 // we will miss a AllDefsAreReloads optimization.
545 // Separate all values dominated by OrigVNI into PHIs and non-PHIs.
546 SmallVector<VNInfo*, 8> PHIs, NonPHIs;
547 LiveInterval &LI = LIS.getInterval(Reg);
549 for (LiveInterval::vni_iterator VI = LI.vni_begin(), VE = LI.vni_end();
552 if (VNI2->isUnused())
554 if (!OrigLI.containsOneValue() &&
555 OrigLI.getVNInfoAt(VNI2->def) != OrigVNI)
557 if (VNI2->isPHIDef() && VNI2->def != OrigVNI->def)
558 PHIs.push_back(VNI2);
560 NonPHIs.push_back(VNI2);
562 DEBUG(dbgs() << "split phi value, checking " << PHIs.size()
563 << " phi-defs, and " << NonPHIs.size()
564 << " non-phi/orig defs\n");
566 // Create entries for all the PHIs. Don't add them to the worklist, we
567 // are processing all of them in one go here.
568 for (VNInfo *PHI : PHIs)
569 SibValues.insert(std::make_pair(PHI, SibValueInfo(Reg, PHI)));
571 // Add every PHI as a dependent of all the non-PHIs.
572 for (VNInfo *NonPHI : NonPHIs) {
573 // Known value? Try an insertion.
574 std::tie(SVI, Inserted) =
575 SibValues.insert(std::make_pair(NonPHI, SibValueInfo(Reg, NonPHI)));
576 // Add all the PHIs as dependents of NonPHI.
577 SVI->second.Deps.insert(SVI->second.Deps.end(), PHIs.begin(),
579 // This is the first time we see NonPHI, add it to the worklist.
581 WorkList.push_back(std::make_pair(Reg, NonPHI));
583 // Propagate to all inserted PHIs, not just VNI.
584 propagateSiblingValue(SVI);
587 // Next work list item.
591 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
592 assert(MI && "Missing def");
594 // Trace through sibling copies.
595 if (unsigned SrcReg = isFullCopyOf(MI, Reg)) {
596 if (isSibling(SrcReg)) {
597 LiveInterval &SrcLI = LIS.getInterval(SrcReg);
598 LiveQueryResult SrcQ = SrcLI.Query(VNI->def);
599 assert(SrcQ.valueIn() && "Copy from non-existing value");
600 // Check if this COPY kills its source.
601 SVI->second.KillsSource = SrcQ.isKill();
602 VNInfo *SrcVNI = SrcQ.valueIn();
603 DEBUG(dbgs() << "copy of " << PrintReg(SrcReg) << ':'
604 << SrcVNI->id << '@' << SrcVNI->def
605 << " kill=" << unsigned(SVI->second.KillsSource) << '\n');
606 // Known sibling source value? Try an insertion.
607 std::tie(SVI, Inserted) = SibValues.insert(
608 std::make_pair(SrcVNI, SibValueInfo(SrcReg, SrcVNI)));
609 // This is the first time we see Src, add it to the worklist.
611 WorkList.push_back(std::make_pair(SrcReg, SrcVNI));
612 propagateSiblingValue(SVI, VNI);
613 // Next work list item.
618 // Track reachable reloads.
619 SVI->second.DefMI = MI;
620 SVI->second.SpillMBB = MI->getParent();
622 if (Reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) {
623 DEBUG(dbgs() << "reload\n");
624 propagateSiblingValue(SVI);
625 // Next work list item.
629 // Potential remat candidate.
630 DEBUG(dbgs() << "def " << *MI);
631 SVI->second.AllDefsAreReloads = false;
632 propagateSiblingValue(SVI);
633 } while (!WorkList.empty());
635 // Look up the value we were looking for. We already did this lookup at the
636 // top of the function, but SibValues may have been invalidated.
637 SVI = SibValues.find(UseVNI);
638 assert(SVI != SibValues.end() && "Didn't compute requested info");
639 DEBUG(dbgs() << " traced to:\t" << SVI->second);
640 return SVI->second.DefMI;
643 /// analyzeSiblingValues - Trace values defined by sibling copies back to
644 /// something that isn't a sibling copy.
646 /// Keep track of values that may be rematerializable.
647 void InlineSpiller::analyzeSiblingValues() {
650 // No siblings at all?
651 if (Edit->getReg() == Original)
654 LiveInterval &OrigLI = LIS.getInterval(Original);
655 for (unsigned Reg : RegsToSpill) {
656 LiveInterval &LI = LIS.getInterval(Reg);
657 for (LiveInterval::const_vni_iterator VI = LI.vni_begin(),
658 VE = LI.vni_end(); VI != VE; ++VI) {
662 MachineInstr *DefMI = nullptr;
663 if (!VNI->isPHIDef()) {
664 DefMI = LIS.getInstructionFromIndex(VNI->def);
665 assert(DefMI && "No defining instruction");
667 // Check possible sibling copies.
668 if (VNI->isPHIDef() || DefMI->isCopy()) {
669 VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
670 assert(OrigVNI && "Def outside original live range");
671 if (OrigVNI->def != VNI->def)
672 DefMI = traceSiblingValue(Reg, VNI, OrigVNI);
674 if (DefMI && Edit->checkRematerializable(VNI, DefMI, AA)) {
675 DEBUG(dbgs() << "Value " << PrintReg(Reg) << ':' << VNI->id << '@'
676 << VNI->def << " may remat from " << *DefMI);
682 /// hoistSpill - Given a sibling copy that defines a value to be spilled, insert
683 /// a spill at a better location.
684 bool InlineSpiller::hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI) {
685 SlotIndex Idx = LIS.getInstructionIndex(CopyMI);
686 VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getRegSlot());
687 assert(VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy");
688 SibValueMap::iterator I = SibValues.find(VNI);
689 if (I == SibValues.end())
692 const SibValueInfo &SVI = I->second;
694 // Let the normal folding code deal with the boring case.
695 if (!SVI.AllDefsAreReloads && SVI.SpillVNI == VNI)
698 // SpillReg may have been deleted by remat and DCE.
699 if (!LIS.hasInterval(SVI.SpillReg)) {
700 DEBUG(dbgs() << "Stale interval: " << PrintReg(SVI.SpillReg) << '\n');
705 LiveInterval &SibLI = LIS.getInterval(SVI.SpillReg);
706 if (!SibLI.containsValue(SVI.SpillVNI)) {
707 DEBUG(dbgs() << "Stale value: " << PrintReg(SVI.SpillReg) << '\n');
712 // Conservatively extend the stack slot range to the range of the original
713 // value. We may be able to do better with stack slot coloring by being more
715 assert(StackInt && "No stack slot assigned yet.");
716 LiveInterval &OrigLI = LIS.getInterval(Original);
717 VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
718 StackInt->MergeValueInAsValue(OrigLI, OrigVNI, StackInt->getValNumInfo(0));
719 DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": "
720 << *StackInt << '\n');
722 // Already spilled everywhere.
723 if (SVI.AllDefsAreReloads) {
724 DEBUG(dbgs() << "\tno spill needed: " << SVI);
725 ++NumOmitReloadSpill;
728 // We are going to spill SVI.SpillVNI immediately after its def, so clear out
729 // any later spills of the same value.
730 eliminateRedundantSpills(SibLI, SVI.SpillVNI);
732 MachineBasicBlock *MBB = LIS.getMBBFromIndex(SVI.SpillVNI->def);
733 MachineBasicBlock::iterator MII;
734 if (SVI.SpillVNI->isPHIDef())
735 MII = MBB->SkipPHIsAndLabels(MBB->begin());
737 MachineInstr *DefMI = LIS.getInstructionFromIndex(SVI.SpillVNI->def);
738 assert(DefMI && "Defining instruction disappeared");
742 // Insert spill without kill flag immediately after def.
743 TII.storeRegToStackSlot(*MBB, MII, SVI.SpillReg, false, StackSlot,
744 MRI.getRegClass(SVI.SpillReg), &TRI);
745 --MII; // Point to store instruction.
746 LIS.InsertMachineInstrInMaps(MII);
747 DEBUG(dbgs() << "\thoisted: " << SVI.SpillVNI->def << '\t' << *MII);
754 /// eliminateRedundantSpills - SLI:VNI is known to be on the stack. Remove any
755 /// redundant spills of this value in SLI.reg and sibling copies.
756 void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
757 assert(VNI && "Missing value");
758 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
759 WorkList.push_back(std::make_pair(&SLI, VNI));
760 assert(StackInt && "No stack slot assigned yet.");
764 std::tie(LI, VNI) = WorkList.pop_back_val();
765 unsigned Reg = LI->reg;
766 DEBUG(dbgs() << "Checking redundant spills for "
767 << VNI->id << '@' << VNI->def << " in " << *LI << '\n');
769 // Regs to spill are taken care of.
770 if (isRegToSpill(Reg))
773 // Add all of VNI's live range to StackInt.
774 StackInt->MergeValueInAsValue(*LI, VNI, StackInt->getValNumInfo(0));
775 DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n');
777 // Find all spills and copies of VNI.
778 for (MachineRegisterInfo::use_instr_nodbg_iterator
779 UI = MRI.use_instr_nodbg_begin(Reg), E = MRI.use_instr_nodbg_end();
781 MachineInstr *MI = &*(UI++);
782 if (!MI->isCopy() && !MI->mayStore())
784 SlotIndex Idx = LIS.getInstructionIndex(MI);
785 if (LI->getVNInfoAt(Idx) != VNI)
788 // Follow sibling copies down the dominator tree.
789 if (unsigned DstReg = isFullCopyOf(MI, Reg)) {
790 if (isSibling(DstReg)) {
791 LiveInterval &DstLI = LIS.getInterval(DstReg);
792 VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getRegSlot());
793 assert(DstVNI && "Missing defined value");
794 assert(DstVNI->def == Idx.getRegSlot() && "Wrong copy def slot");
795 WorkList.push_back(std::make_pair(&DstLI, DstVNI));
802 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
803 DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << *MI);
804 // eliminateDeadDefs won't normally remove stores, so switch opcode.
805 MI->setDesc(TII.get(TargetOpcode::KILL));
806 DeadDefs.push_back(MI);
811 } while (!WorkList.empty());
815 //===----------------------------------------------------------------------===//
817 //===----------------------------------------------------------------------===//
819 /// markValueUsed - Remember that VNI failed to rematerialize, so its defining
820 /// instruction cannot be eliminated. See through snippet copies
821 void InlineSpiller::markValueUsed(LiveInterval *LI, VNInfo *VNI) {
822 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
823 WorkList.push_back(std::make_pair(LI, VNI));
825 std::tie(LI, VNI) = WorkList.pop_back_val();
826 if (!UsedValues.insert(VNI).second)
829 if (VNI->isPHIDef()) {
830 MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
831 for (MachineBasicBlock *P : MBB->predecessors()) {
832 VNInfo *PVNI = LI->getVNInfoBefore(LIS.getMBBEndIdx(P));
834 WorkList.push_back(std::make_pair(LI, PVNI));
839 // Follow snippet copies.
840 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
841 if (!SnippetCopies.count(MI))
843 LiveInterval &SnipLI = LIS.getInterval(MI->getOperand(1).getReg());
844 assert(isRegToSpill(SnipLI.reg) && "Unexpected register in copy");
845 VNInfo *SnipVNI = SnipLI.getVNInfoAt(VNI->def.getRegSlot(true));
846 assert(SnipVNI && "Snippet undefined before copy");
847 WorkList.push_back(std::make_pair(&SnipLI, SnipVNI));
848 } while (!WorkList.empty());
851 /// reMaterializeFor - Attempt to rematerialize before MI instead of reloading.
852 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg,
853 MachineBasicBlock::iterator MI) {
855 // Analyze instruction
856 SmallVector<std::pair<MachineInstr *, unsigned>, 8> Ops;
857 MIBundleOperands::VirtRegInfo RI =
858 MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops);
863 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
864 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
867 DEBUG(dbgs() << "\tadding <undef> flags: ");
868 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
869 MachineOperand &MO = MI->getOperand(i);
870 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
873 DEBUG(dbgs() << UseIdx << '\t' << *MI);
877 if (SnippetCopies.count(MI))
880 // Use an OrigVNI from traceSiblingValue when ParentVNI is a sibling copy.
881 LiveRangeEdit::Remat RM(ParentVNI);
882 SibValueMap::const_iterator SibI = SibValues.find(ParentVNI);
883 if (SibI != SibValues.end())
884 RM.OrigMI = SibI->second.DefMI;
885 if (!Edit->canRematerializeAt(RM, UseIdx, false)) {
886 markValueUsed(&VirtReg, ParentVNI);
887 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
891 // If the instruction also writes VirtReg.reg, it had better not require the
892 // same register for uses and defs.
894 markValueUsed(&VirtReg, ParentVNI);
895 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
899 // Before rematerializing into a register for a single instruction, try to
900 // fold a load into the instruction. That avoids allocating a new register.
901 if (RM.OrigMI->canFoldAsLoad() &&
902 foldMemoryOperand(Ops, RM.OrigMI)) {
903 Edit->markRematerialized(RM.ParentVNI);
908 // Alocate a new register for the remat.
909 unsigned NewVReg = Edit->createFrom(Original);
911 // Finally we can rematerialize OrigMI before MI.
912 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewVReg, RM,
915 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'
916 << *LIS.getInstructionFromIndex(DefIdx));
919 for (const auto &OpPair : Ops) {
920 MachineOperand &MO = OpPair.first->getOperand(OpPair.second);
921 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
926 DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI << '\n');
932 /// reMaterializeAll - Try to rematerialize as many uses as possible,
933 /// and trim the live ranges after.
934 void InlineSpiller::reMaterializeAll() {
935 // analyzeSiblingValues has already tested all relevant defining instructions.
936 if (!Edit->anyRematerializable(AA))
941 // Try to remat before all uses of snippets.
942 bool anyRemat = false;
943 for (unsigned Reg : RegsToSpill) {
944 LiveInterval &LI = LIS.getInterval(Reg);
945 for (MachineRegisterInfo::reg_bundle_iterator
946 RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();
948 MachineInstr *MI = &*(RegI++);
950 // Debug values are not allowed to affect codegen.
951 if (MI->isDebugValue())
954 anyRemat |= reMaterializeFor(LI, MI);
960 // Remove any values that were completely rematted.
961 for (unsigned Reg : RegsToSpill) {
962 LiveInterval &LI = LIS.getInterval(Reg);
963 for (LiveInterval::vni_iterator I = LI.vni_begin(), E = LI.vni_end();
966 if (VNI->isUnused() || VNI->isPHIDef() || UsedValues.count(VNI))
968 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
969 MI->addRegisterDead(Reg, &TRI);
970 if (!MI->allDefsAreDead())
972 DEBUG(dbgs() << "All defs dead: " << *MI);
973 DeadDefs.push_back(MI);
977 // Eliminate dead code after remat. Note that some snippet copies may be
979 if (DeadDefs.empty())
981 DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n");
982 Edit->eliminateDeadDefs(DeadDefs, RegsToSpill);
984 // Get rid of deleted and empty intervals.
985 unsigned ResultPos = 0;
986 for (unsigned Reg : RegsToSpill) {
987 if (!LIS.hasInterval(Reg))
990 LiveInterval &LI = LIS.getInterval(Reg);
992 Edit->eraseVirtReg(Reg);
996 RegsToSpill[ResultPos++] = Reg;
998 RegsToSpill.erase(RegsToSpill.begin() + ResultPos, RegsToSpill.end());
999 DEBUG(dbgs() << RegsToSpill.size() << " registers to spill after remat.\n");
1003 //===----------------------------------------------------------------------===//
1005 //===----------------------------------------------------------------------===//
1007 /// If MI is a load or store of StackSlot, it can be removed.
1008 bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
1010 unsigned InstrReg = TII.isLoadFromStackSlot(MI, FI);
1011 bool IsLoad = InstrReg;
1013 InstrReg = TII.isStoreToStackSlot(MI, FI);
1015 // We have a stack access. Is it the right register and slot?
1016 if (InstrReg != Reg || FI != StackSlot)
1019 DEBUG(dbgs() << "Coalescing stack access: " << *MI);
1020 LIS.RemoveMachineInstrFromMaps(MI);
1021 MI->eraseFromParent();
1024 ++NumReloadsRemoved;
1034 #if !defined(NDEBUG)
1035 // Dump the range of instructions from B to E with their slot indexes.
1036 static void dumpMachineInstrRangeWithSlotIndex(MachineBasicBlock::iterator B,
1037 MachineBasicBlock::iterator E,
1038 LiveIntervals const &LIS,
1039 const char *const header,
1041 char NextLine = '\n';
1042 char SlotIndent = '\t';
1044 if (std::next(B) == E) {
1049 dbgs() << '\t' << header << ": " << NextLine;
1051 for (MachineBasicBlock::iterator I = B; I != E; ++I) {
1052 SlotIndex Idx = LIS.getInstructionIndex(I).getRegSlot();
1054 // If a register was passed in and this instruction has it as a
1055 // destination that is marked as an early clobber, print the
1056 // early-clobber slot index.
1058 MachineOperand *MO = I->findRegisterDefOperand(VReg);
1059 if (MO && MO->isEarlyClobber())
1060 Idx = Idx.getRegSlot(true);
1063 dbgs() << SlotIndent << Idx << '\t' << *I;
1068 /// foldMemoryOperand - Try folding stack slot references in Ops into their
1071 /// @param Ops Operand indices from analyzeVirtReg().
1072 /// @param LoadMI Load instruction to use instead of stack slot when non-null.
1073 /// @return True on success.
1074 bool InlineSpiller::
1075 foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> > Ops,
1076 MachineInstr *LoadMI) {
1079 // Don't attempt folding in bundles.
1080 MachineInstr *MI = Ops.front().first;
1081 if (Ops.back().first != MI || MI->isBundled())
1084 bool WasCopy = MI->isCopy();
1085 unsigned ImpReg = 0;
1087 bool SpillSubRegs = (MI->getOpcode() == TargetOpcode::STATEPOINT ||
1088 MI->getOpcode() == TargetOpcode::PATCHPOINT ||
1089 MI->getOpcode() == TargetOpcode::STACKMAP);
1091 // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
1093 SmallVector<unsigned, 8> FoldOps;
1094 for (const auto &OpPair : Ops) {
1095 unsigned Idx = OpPair.second;
1096 assert(MI == OpPair.first && "Instruction conflict during operand folding");
1097 MachineOperand &MO = MI->getOperand(Idx);
1098 if (MO.isImplicit()) {
1099 ImpReg = MO.getReg();
1102 // FIXME: Teach targets to deal with subregs.
1103 if (!SpillSubRegs && MO.getSubReg())
1105 // We cannot fold a load instruction into a def.
1106 if (LoadMI && MO.isDef())
1108 // Tied use operands should not be passed to foldMemoryOperand.
1109 if (!MI->isRegTiedToDefOperand(Idx))
1110 FoldOps.push_back(Idx);
1113 MachineInstrSpan MIS(MI);
1115 MachineInstr *FoldMI =
1116 LoadMI ? TII.foldMemoryOperand(MI, FoldOps, LoadMI)
1117 : TII.foldMemoryOperand(MI, FoldOps, StackSlot);
1121 // Remove LIS for any dead defs in the original MI not in FoldMI.
1122 for (MIBundleOperands MO(MI); MO.isValid(); ++MO) {
1125 unsigned Reg = MO->getReg();
1126 if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) ||
1127 MRI.isReserved(Reg)) {
1130 // Skip non-Defs, including undef uses and internal reads.
1133 MIBundleOperands::PhysRegInfo RI =
1134 MIBundleOperands(FoldMI).analyzePhysReg(Reg, &TRI);
1135 if (RI.FullyDefined)
1137 // FoldMI does not define this physreg. Remove the LI segment.
1138 assert(MO->isDead() && "Cannot fold physreg def");
1139 SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
1140 LIS.removePhysRegDefAt(Reg, Idx);
1143 LIS.ReplaceMachineInstrInMaps(MI, FoldMI);
1144 MI->eraseFromParent();
1146 // Insert any new instructions other than FoldMI into the LIS maps.
1147 assert(!MIS.empty() && "Unexpected empty span of instructions!");
1148 for (MachineInstr &MI : MIS)
1150 LIS.InsertMachineInstrInMaps(&MI);
1152 // TII.foldMemoryOperand may have left some implicit operands on the
1153 // instruction. Strip them.
1155 for (unsigned i = FoldMI->getNumOperands(); i; --i) {
1156 MachineOperand &MO = FoldMI->getOperand(i - 1);
1157 if (!MO.isReg() || !MO.isImplicit())
1159 if (MO.getReg() == ImpReg)
1160 FoldMI->RemoveOperand(i - 1);
1163 DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MIS.end(), LIS,
1168 else if (Ops.front().second == 0)
1175 void InlineSpiller::insertReload(unsigned NewVReg,
1177 MachineBasicBlock::iterator MI) {
1178 MachineBasicBlock &MBB = *MI->getParent();
1180 MachineInstrSpan MIS(MI);
1181 TII.loadRegFromStackSlot(MBB, MI, NewVReg, StackSlot,
1182 MRI.getRegClass(NewVReg), &TRI);
1184 LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MI);
1186 DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MI, LIS, "reload",
1191 /// insertSpill - Insert a spill of NewVReg after MI.
1192 void InlineSpiller::insertSpill(unsigned NewVReg, bool isKill,
1193 MachineBasicBlock::iterator MI) {
1194 MachineBasicBlock &MBB = *MI->getParent();
1196 MachineInstrSpan MIS(MI);
1197 TII.storeRegToStackSlot(MBB, std::next(MI), NewVReg, isKill, StackSlot,
1198 MRI.getRegClass(NewVReg), &TRI);
1200 LIS.InsertMachineInstrRangeInMaps(std::next(MI), MIS.end());
1202 DEBUG(dumpMachineInstrRangeWithSlotIndex(std::next(MI), MIS.end(), LIS,
1207 /// spillAroundUses - insert spill code around each use of Reg.
1208 void InlineSpiller::spillAroundUses(unsigned Reg) {
1209 DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n');
1210 LiveInterval &OldLI = LIS.getInterval(Reg);
1212 // Iterate over instructions using Reg.
1213 for (MachineRegisterInfo::reg_bundle_iterator
1214 RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();
1216 MachineInstr *MI = &*(RegI++);
1218 // Debug values are not allowed to affect codegen.
1219 if (MI->isDebugValue()) {
1220 // Modify DBG_VALUE now that the value is in a spill slot.
1221 bool IsIndirect = MI->isIndirectDebugValue();
1222 uint64_t Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
1223 const MDNode *Var = MI->getDebugVariable();
1224 const MDNode *Expr = MI->getDebugExpression();
1225 DebugLoc DL = MI->getDebugLoc();
1226 DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
1227 MachineBasicBlock *MBB = MI->getParent();
1228 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
1229 "Expected inlined-at fields to agree");
1230 BuildMI(*MBB, MBB->erase(MI), DL, TII.get(TargetOpcode::DBG_VALUE))
1231 .addFrameIndex(StackSlot)
1238 // Ignore copies to/from snippets. We'll delete them.
1239 if (SnippetCopies.count(MI))
1242 // Stack slot accesses may coalesce away.
1243 if (coalesceStackAccess(MI, Reg))
1246 // Analyze instruction.
1247 SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops;
1248 MIBundleOperands::VirtRegInfo RI =
1249 MIBundleOperands(MI).analyzeVirtReg(Reg, &Ops);
1251 // Find the slot index where this instruction reads and writes OldLI.
1252 // This is usually the def slot, except for tied early clobbers.
1253 SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
1254 if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getRegSlot(true)))
1255 if (SlotIndex::isSameInstr(Idx, VNI->def))
1258 // Check for a sibling copy.
1259 unsigned SibReg = isFullCopyOf(MI, Reg);
1260 if (SibReg && isSibling(SibReg)) {
1261 // This may actually be a copy between snippets.
1262 if (isRegToSpill(SibReg)) {
1263 DEBUG(dbgs() << "Found new snippet copy: " << *MI);
1264 SnippetCopies.insert(MI);
1268 // Hoist the spill of a sib-reg copy.
1269 if (hoistSpill(OldLI, MI)) {
1270 // This COPY is now dead, the value is already in the stack slot.
1271 MI->getOperand(0).setIsDead();
1272 DeadDefs.push_back(MI);
1276 // This is a reload for a sib-reg copy. Drop spills downstream.
1277 LiveInterval &SibLI = LIS.getInterval(SibReg);
1278 eliminateRedundantSpills(SibLI, SibLI.getVNInfoAt(Idx));
1279 // The COPY will fold to a reload below.
1283 // Attempt to fold memory ops.
1284 if (foldMemoryOperand(Ops))
1287 // Create a new virtual register for spill/fill.
1288 // FIXME: Infer regclass from instruction alone.
1289 unsigned NewVReg = Edit->createFrom(Reg);
1292 insertReload(NewVReg, Idx, MI);
1294 // Rewrite instruction operands.
1295 bool hasLiveDef = false;
1296 for (const auto &OpPair : Ops) {
1297 MachineOperand &MO = OpPair.first->getOperand(OpPair.second);
1300 if (!OpPair.first->isRegTiedToDefOperand(OpPair.second))
1307 DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI << '\n');
1309 // FIXME: Use a second vreg if instruction has no tied ops.
1312 insertSpill(NewVReg, true, MI);
1316 /// spillAll - Spill all registers remaining after rematerialization.
1317 void InlineSpiller::spillAll() {
1318 // Update LiveStacks now that we are committed to spilling.
1319 if (StackSlot == VirtRegMap::NO_STACK_SLOT) {
1320 StackSlot = VRM.assignVirt2StackSlot(Original);
1321 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original));
1322 StackInt->getNextValue(SlotIndex(), LSS.getVNInfoAllocator());
1324 StackInt = &LSS.getInterval(StackSlot);
1326 if (Original != Edit->getReg())
1327 VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot);
1329 assert(StackInt->getNumValNums() == 1 && "Bad stack interval values");
1330 for (unsigned Reg : RegsToSpill)
1331 StackInt->MergeSegmentsInAsValue(LIS.getInterval(Reg),
1332 StackInt->getValNumInfo(0));
1333 DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n');
1335 // Spill around uses of all RegsToSpill.
1336 for (unsigned Reg : RegsToSpill)
1337 spillAroundUses(Reg);
1339 // Hoisted spills may cause dead code.
1340 if (!DeadDefs.empty()) {
1341 DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n");
1342 Edit->eliminateDeadDefs(DeadDefs, RegsToSpill);
1345 // Finally delete the SnippetCopies.
1346 for (unsigned Reg : RegsToSpill) {
1347 for (MachineRegisterInfo::reg_instr_iterator
1348 RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end();
1350 MachineInstr *MI = &*(RI++);
1351 assert(SnippetCopies.count(MI) && "Remaining use wasn't a snippet copy");
1352 // FIXME: Do this with a LiveRangeEdit callback.
1353 LIS.RemoveMachineInstrFromMaps(MI);
1354 MI->eraseFromParent();
1358 // Delete all spilled registers.
1359 for (unsigned Reg : RegsToSpill)
1360 Edit->eraseVirtReg(Reg);
1363 void InlineSpiller::spill(LiveRangeEdit &edit) {
1366 assert(!TargetRegisterInfo::isStackSlot(edit.getReg())
1367 && "Trying to spill a stack slot.");
1368 // Share a stack slot among all descendants of Original.
1369 Original = VRM.getOriginal(edit.getReg());
1370 StackSlot = VRM.getStackSlot(Original);
1373 DEBUG(dbgs() << "Inline spilling "
1374 << TRI.getRegClassName(MRI.getRegClass(edit.getReg()))
1375 << ':' << edit.getParent()
1376 << "\nFrom original " << PrintReg(Original) << '\n');
1377 assert(edit.getParent().isSpillable() &&
1378 "Attempting to spill already spilled value.");
1379 assert(DeadDefs.empty() && "Previous spill didn't remove dead defs");
1381 collectRegsToSpill();
1382 analyzeSiblingValues();
1385 // Remat may handle everything.
1386 if (!RegsToSpill.empty())
1389 Edit->calculateRegClassAndHint(MF, Loops, MBFI);