1 //===- SchedGraph.cpp - Scheduling Graph Implementation -------------------===//
3 // Scheduling graph based on SSA graph plus extra dependence edges capturing
4 // dependences due to machine resources (machine registers, CC registers, and
7 //===----------------------------------------------------------------------===//
9 #include "SchedGraph.h"
10 #include "llvm/CodeGen/InstrSelection.h"
11 #include "llvm/CodeGen/MachineCodeForInstruction.h"
12 #include "llvm/CodeGen/MachineFunction.h"
13 #include "llvm/Target/TargetRegInfo.h"
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/Target/TargetInstrInfo.h"
16 #include "llvm/Function.h"
17 #include "llvm/iOther.h"
18 #include "Support/StringExtras.h"
19 #include "Support/STLExtras.h"
21 //*********************** Internal Data Structures *************************/
23 // The following two types need to be classes, not typedefs, so we can use
24 // opaque declarations in SchedGraph.h
26 struct RefVec: public std::vector<std::pair<SchedGraphNode*, int> > {
27 typedef std::vector<std::pair<SchedGraphNode*,int> >::iterator iterator;
29 std::vector<std::pair<SchedGraphNode*,int> >::const_iterator const_iterator;
32 struct RegToRefVecMap: public hash_map<int, RefVec> {
33 typedef hash_map<int, RefVec>:: iterator iterator;
34 typedef hash_map<int, RefVec>::const_iterator const_iterator;
37 struct ValueToDefVecMap: public hash_map<const Value*, RefVec> {
38 typedef hash_map<const Value*, RefVec>:: iterator iterator;
39 typedef hash_map<const Value*, RefVec>::const_iterator const_iterator;
43 // class SchedGraphEdge
47 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
48 SchedGraphNode* _sink,
49 SchedGraphEdgeDepType _depType,
50 unsigned int _depOrderType,
55 depOrderType(_depOrderType),
56 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
59 assert(src != sink && "Self-loop in scheduling graph!");
60 src->addOutEdge(this);
61 sink->addInEdge(this);
66 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
67 SchedGraphNode* _sink,
69 unsigned int _depOrderType,
74 depOrderType(_depOrderType),
75 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
78 assert(src != sink && "Self-loop in scheduling graph!");
79 src->addOutEdge(this);
80 sink->addInEdge(this);
85 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
86 SchedGraphNode* _sink,
88 unsigned int _depOrderType,
92 depType(MachineRegister),
93 depOrderType(_depOrderType),
94 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
95 machineRegNum(_regNum)
97 assert(src != sink && "Self-loop in scheduling graph!");
98 src->addOutEdge(this);
99 sink->addInEdge(this);
104 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
105 SchedGraphNode* _sink,
106 ResourceId _resourceId,
110 depType(MachineResource),
111 depOrderType(NonDataDep),
112 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
113 resourceId(_resourceId)
115 assert(src != sink && "Self-loop in scheduling graph!");
116 src->addOutEdge(this);
117 sink->addInEdge(this);
121 SchedGraphEdge::~SchedGraphEdge()
125 void SchedGraphEdge::dump(int indent) const {
126 std::cerr << std::string(indent*2, ' ') << *this;
131 // class SchedGraphNode
135 SchedGraphNode::SchedGraphNode(unsigned NID,
136 MachineBasicBlock *mbb,
138 const TargetMachine& Target)
139 : nodeId(NID), MBB(mbb), minstr(mbb ? (*mbb)[indexInBB] : 0),
140 origIndexInBB(indexInBB), latency(0) {
143 MachineOpCode mopCode = minstr->getOpCode();
144 latency = Target.getInstrInfo().hasResultInterlock(mopCode)
145 ? Target.getInstrInfo().minLatency(mopCode)
146 : Target.getInstrInfo().maxLatency(mopCode);
152 SchedGraphNode::~SchedGraphNode()
154 // for each node, delete its out-edges
155 std::for_each(beginOutEdges(), endOutEdges(),
156 deleter<SchedGraphEdge>);
159 void SchedGraphNode::dump(int indent) const {
160 std::cerr << std::string(indent*2, ' ') << *this;
165 SchedGraphNode::addInEdge(SchedGraphEdge* edge)
167 inEdges.push_back(edge);
172 SchedGraphNode::addOutEdge(SchedGraphEdge* edge)
174 outEdges.push_back(edge);
178 SchedGraphNode::removeInEdge(const SchedGraphEdge* edge)
180 assert(edge->getSink() == this);
182 for (iterator I = beginInEdges(); I != endInEdges(); ++I)
191 SchedGraphNode::removeOutEdge(const SchedGraphEdge* edge)
193 assert(edge->getSrc() == this);
195 for (iterator I = beginOutEdges(); I != endOutEdges(); ++I)
210 SchedGraph::SchedGraph(MachineBasicBlock &mbb, const TargetMachine& target)
217 SchedGraph::~SchedGraph()
219 for (const_iterator I = begin(); I != end(); ++I)
227 SchedGraph::dump() const
229 std::cerr << " Sched Graph for Basic Block: ";
230 std::cerr << MBB.getBasicBlock()->getName()
231 << " (" << MBB.getBasicBlock() << ")";
233 std::cerr << "\n\n Actual Root nodes : ";
234 for (unsigned i=0, N=graphRoot->outEdges.size(); i < N; i++)
235 std::cerr << graphRoot->outEdges[i]->getSink()->getNodeId()
236 << ((i == N-1)? "" : ", ");
238 std::cerr << "\n Graph Nodes:\n";
239 for (const_iterator I=begin(); I != end(); ++I)
240 std::cerr << "\n" << *I->second;
247 SchedGraph::eraseIncomingEdges(SchedGraphNode* node, bool addDummyEdges)
249 // Delete and disconnect all in-edges for the node
250 for (SchedGraphNode::iterator I = node->beginInEdges();
251 I != node->endInEdges(); ++I)
253 SchedGraphNode* srcNode = (*I)->getSrc();
254 srcNode->removeOutEdge(*I);
258 srcNode != getRoot() &&
259 srcNode->beginOutEdges() == srcNode->endOutEdges())
261 // srcNode has no more out edges, so add an edge to dummy EXIT node
262 assert(node != getLeaf() && "Adding edge that was just removed?");
263 (void) new SchedGraphEdge(srcNode, getLeaf(),
264 SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
268 node->inEdges.clear();
272 SchedGraph::eraseOutgoingEdges(SchedGraphNode* node, bool addDummyEdges)
274 // Delete and disconnect all out-edges for the node
275 for (SchedGraphNode::iterator I = node->beginOutEdges();
276 I != node->endOutEdges(); ++I)
278 SchedGraphNode* sinkNode = (*I)->getSink();
279 sinkNode->removeInEdge(*I);
283 sinkNode != getLeaf() &&
284 sinkNode->beginInEdges() == sinkNode->endInEdges())
285 { //sinkNode has no more in edges, so add an edge from dummy ENTRY node
286 assert(node != getRoot() && "Adding edge that was just removed?");
287 (void) new SchedGraphEdge(getRoot(), sinkNode,
288 SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
292 node->outEdges.clear();
296 SchedGraph::eraseIncidentEdges(SchedGraphNode* node, bool addDummyEdges)
298 this->eraseIncomingEdges(node, addDummyEdges);
299 this->eraseOutgoingEdges(node, addDummyEdges);
304 SchedGraph::addDummyEdges()
306 assert(graphRoot->outEdges.size() == 0);
308 for (const_iterator I=begin(); I != end(); ++I)
310 SchedGraphNode* node = (*I).second;
311 assert(node != graphRoot && node != graphLeaf);
312 if (node->beginInEdges() == node->endInEdges())
313 (void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep,
314 SchedGraphEdge::NonDataDep, 0);
315 if (node->beginOutEdges() == node->endOutEdges())
316 (void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep,
317 SchedGraphEdge::NonDataDep, 0);
323 SchedGraph::addCDEdges(const TerminatorInst* term,
324 const TargetMachine& target)
326 const TargetInstrInfo& mii = target.getInstrInfo();
327 MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
329 // Find the first branch instr in the sequence of machine instrs for term
332 while (! mii.isBranch(termMvec[first]->getOpCode()) &&
333 ! mii.isReturn(termMvec[first]->getOpCode()))
335 assert(first < termMvec.size() &&
336 "No branch instructions for terminator? Ok, but weird!");
337 if (first == termMvec.size())
340 SchedGraphNode* firstBrNode = getGraphNodeForInstr(termMvec[first]);
342 // Add CD edges from each instruction in the sequence to the
343 // *last preceding* branch instr. in the sequence
344 // Use a latency of 0 because we only need to prevent out-of-order issue.
346 for (unsigned i = termMvec.size(); i > first+1; --i)
348 SchedGraphNode* toNode = getGraphNodeForInstr(termMvec[i-1]);
349 assert(toNode && "No node for instr generated for branch/ret?");
351 for (unsigned j = i-1; j != 0; --j)
352 if (mii.isBranch(termMvec[j-1]->getOpCode()) ||
353 mii.isReturn(termMvec[j-1]->getOpCode()))
355 SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]);
356 assert(brNode && "No node for instr generated for branch/ret?");
357 (void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
358 SchedGraphEdge::NonDataDep, 0);
359 break; // only one incoming edge is enough
363 // Add CD edges from each instruction preceding the first branch
364 // to the first branch. Use a latency of 0 as above.
366 for (unsigned i = first; i != 0; --i)
368 SchedGraphNode* fromNode = getGraphNodeForInstr(termMvec[i-1]);
369 assert(fromNode && "No node for instr generated for branch?");
370 (void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
371 SchedGraphEdge::NonDataDep, 0);
374 // Now add CD edges to the first branch instruction in the sequence from
375 // all preceding instructions in the basic block. Use 0 latency again.
377 for (unsigned i=0, N=MBB.size(); i < N; i++)
379 if (MBB[i] == termMvec[first]) // reached the first branch
382 SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
383 if (fromNode == NULL)
384 continue; // dummy instruction, e.g., PHI
386 (void) new SchedGraphEdge(fromNode, firstBrNode,
387 SchedGraphEdge::CtrlDep,
388 SchedGraphEdge::NonDataDep, 0);
390 // If we find any other machine instructions (other than due to
391 // the terminator) that also have delay slots, add an outgoing edge
392 // from the instruction to the instructions in the delay slots.
394 unsigned d = mii.getNumDelaySlots(MBB[i]->getOpCode());
395 assert(i+d < N && "Insufficient delay slots for instruction?");
397 for (unsigned j=1; j <= d; j++)
399 SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
400 assert(toNode && "No node for machine instr in delay slot?");
401 (void) new SchedGraphEdge(fromNode, toNode,
402 SchedGraphEdge::CtrlDep,
403 SchedGraphEdge::NonDataDep, 0);
408 static const int SG_LOAD_REF = 0;
409 static const int SG_STORE_REF = 1;
410 static const int SG_CALL_REF = 2;
412 static const unsigned int SG_DepOrderArray[][3] = {
413 { SchedGraphEdge::NonDataDep,
414 SchedGraphEdge::AntiDep,
415 SchedGraphEdge::AntiDep },
416 { SchedGraphEdge::TrueDep,
417 SchedGraphEdge::OutputDep,
418 SchedGraphEdge::TrueDep | SchedGraphEdge::OutputDep },
419 { SchedGraphEdge::TrueDep,
420 SchedGraphEdge::AntiDep | SchedGraphEdge::OutputDep,
421 SchedGraphEdge::TrueDep | SchedGraphEdge::AntiDep
422 | SchedGraphEdge::OutputDep }
426 // Add a dependence edge between every pair of machine load/store/call
427 // instructions, where at least one is a store or a call.
428 // Use latency 1 just to ensure that memory operations are ordered;
429 // latency does not otherwise matter (true dependences enforce that).
432 SchedGraph::addMemEdges(const std::vector<SchedGraphNode*>& memNodeVec,
433 const TargetMachine& target)
435 const TargetInstrInfo& mii = target.getInstrInfo();
437 // Instructions in memNodeVec are in execution order within the basic block,
438 // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
440 for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
442 MachineOpCode fromOpCode = memNodeVec[im]->getOpCode();
443 int fromType = (mii.isCall(fromOpCode)? SG_CALL_REF
444 : (mii.isLoad(fromOpCode)? SG_LOAD_REF
446 for (unsigned jm=im+1; jm < NM; jm++)
448 MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
449 int toType = (mii.isCall(toOpCode)? SG_CALL_REF
450 : (mii.isLoad(toOpCode)? SG_LOAD_REF
453 if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF)
454 (void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm],
455 SchedGraphEdge::MemoryDep,
456 SG_DepOrderArray[fromType][toType], 1);
461 // Add edges from/to CC reg instrs to/from call instrs.
462 // Essentially this prevents anything that sets or uses a CC reg from being
463 // reordered w.r.t. a call.
464 // Use a latency of 0 because we only need to prevent out-of-order issue,
465 // like with control dependences.
468 SchedGraph::addCallDepEdges(const std::vector<SchedGraphNode*>& callDepNodeVec,
469 const TargetMachine& target)
471 const TargetInstrInfo& mii = target.getInstrInfo();
473 // Instructions in memNodeVec are in execution order within the basic block,
474 // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
476 for (unsigned ic=0, NC=callDepNodeVec.size(); ic < NC; ic++)
477 if (mii.isCall(callDepNodeVec[ic]->getOpCode()))
479 // Add SG_CALL_REF edges from all preds to this instruction.
480 for (unsigned jc=0; jc < ic; jc++)
481 (void) new SchedGraphEdge(callDepNodeVec[jc], callDepNodeVec[ic],
482 SchedGraphEdge::MachineRegister,
483 MachineIntRegsRID, 0);
485 // And do the same from this instruction to all successors.
486 for (unsigned jc=ic+1; jc < NC; jc++)
487 (void) new SchedGraphEdge(callDepNodeVec[ic], callDepNodeVec[jc],
488 SchedGraphEdge::MachineRegister,
489 MachineIntRegsRID, 0);
492 #ifdef CALL_DEP_NODE_VEC_CANNOT_WORK
493 // Find the call instruction nodes and put them in a vector.
494 std::vector<SchedGraphNode*> callNodeVec;
495 for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
496 if (mii.isCall(memNodeVec[im]->getOpCode()))
497 callNodeVec.push_back(memNodeVec[im]);
499 // Now walk the entire basic block, looking for CC instructions *and*
500 // call instructions, and keep track of the order of the instructions.
501 // Use the call node vec to quickly find earlier and later call nodes
502 // relative to the current CC instruction.
504 int lastCallNodeIdx = -1;
505 for (unsigned i=0, N=bbMvec.size(); i < N; i++)
506 if (mii.isCall(bbMvec[i]->getOpCode()))
509 for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
510 if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
512 assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
514 else if (mii.isCCInstr(bbMvec[i]->getOpCode()))
516 // Add incoming/outgoing edges from/to preceding/later calls
517 SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
519 for ( ; j <= lastCallNodeIdx; j++)
520 (void) new SchedGraphEdge(callNodeVec[j], ccNode,
521 MachineCCRegsRID, 0);
522 for ( ; j < (int) callNodeVec.size(); j++)
523 (void) new SchedGraphEdge(ccNode, callNodeVec[j],
524 MachineCCRegsRID, 0);
531 SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
532 const TargetMachine& target)
534 // This code assumes that two registers with different numbers are
537 for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
538 I != regToRefVecMap.end(); ++I)
540 int regNum = (*I).first;
541 RefVec& regRefVec = (*I).second;
543 // regRefVec is ordered by control flow order in the basic block
544 for (unsigned i=0; i < regRefVec.size(); ++i) {
545 SchedGraphNode* node = regRefVec[i].first;
546 unsigned int opNum = regRefVec[i].second;
547 const MachineOperand& mop =
548 node->getMachineInstr()->getExplOrImplOperand(opNum);
549 bool isDef = mop.opIsDefOnly();
550 bool isDefAndUse = mop.opIsDefAndUse();
552 for (unsigned p=0; p < i; ++p) {
553 SchedGraphNode* prevNode = regRefVec[p].first;
554 if (prevNode != node) {
555 unsigned int prevOpNum = regRefVec[p].second;
556 const MachineOperand& prevMop =
557 prevNode->getMachineInstr()->getExplOrImplOperand(prevOpNum);
558 bool prevIsDef = prevMop.opIsDefOnly();
559 bool prevIsDefAndUse = prevMop.opIsDefAndUse();
562 new SchedGraphEdge(prevNode, node, regNum,
563 SchedGraphEdge::OutputDep);
564 if (!prevIsDef || prevIsDefAndUse)
565 new SchedGraphEdge(prevNode, node, regNum,
566 SchedGraphEdge::AntiDep);
570 if (!isDef || isDefAndUse)
571 new SchedGraphEdge(prevNode, node, regNum,
572 SchedGraphEdge::TrueDep);
580 // Adds dependences to/from refNode from/to all other defs
581 // in the basic block. refNode may be a use, a def, or both.
582 // We do not consider other uses because we are not building use-use deps.
585 SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
586 const RefVec& defVec,
587 const Value* defValue,
589 bool refNodeIsDefAndUse,
590 const TargetMachine& target)
592 bool refNodeIsUse = !refNodeIsDef || refNodeIsDefAndUse;
594 // Add true or output dep edges from all def nodes before refNode in BB.
595 // Add anti or output dep edges to all def nodes after refNode.
596 for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I)
598 if ((*I).first == refNode)
599 continue; // Dont add any self-loops
601 if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB()) {
602 // (*).first is before refNode
604 (void) new SchedGraphEdge((*I).first, refNode, defValue,
605 SchedGraphEdge::OutputDep);
607 (void) new SchedGraphEdge((*I).first, refNode, defValue,
608 SchedGraphEdge::TrueDep);
610 // (*).first is after refNode
612 (void) new SchedGraphEdge(refNode, (*I).first, defValue,
613 SchedGraphEdge::OutputDep);
615 (void) new SchedGraphEdge(refNode, (*I).first, defValue,
616 SchedGraphEdge::AntiDep);
623 SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
624 const ValueToDefVecMap& valueToDefVecMap,
625 const TargetMachine& target)
627 SchedGraphNode* node = getGraphNodeForInstr(&MI);
631 // Add edges for all operands of the machine instruction.
633 for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i)
635 switch (MI.getOperand(i).getType())
637 case MachineOperand::MO_VirtualRegister:
638 case MachineOperand::MO_CCRegister:
639 if (const Value* srcI = MI.getOperand(i).getVRegValue())
641 ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
642 if (I != valueToDefVecMap.end())
643 addEdgesForValue(node, I->second, srcI,
644 MI.getOperand(i).opIsDefOnly(),
645 MI.getOperand(i).opIsDefAndUse(), target);
649 case MachineOperand::MO_MachineRegister:
652 case MachineOperand::MO_SignExtendedImmed:
653 case MachineOperand::MO_UnextendedImmed:
654 case MachineOperand::MO_PCRelativeDisp:
655 break; // nothing to do for immediate fields
658 assert(0 && "Unknown machine operand type in SchedGraph builder");
663 // Add edges for values implicitly used by the machine instruction.
664 // Examples include function arguments to a Call instructions or the return
665 // value of a Ret instruction.
667 for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i)
668 if (MI.getImplicitOp(i).opIsUse() || MI.getImplicitOp(i).opIsDefAndUse())
669 if (const Value* srcI = MI.getImplicitRef(i))
671 ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
672 if (I != valueToDefVecMap.end())
673 addEdgesForValue(node, I->second, srcI,
674 MI.getImplicitOp(i).opIsDefOnly(),
675 MI.getImplicitOp(i).opIsDefAndUse(), target);
681 SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
682 SchedGraphNode* node,
683 std::vector<SchedGraphNode*>& memNodeVec,
684 std::vector<SchedGraphNode*>& callDepNodeVec,
685 RegToRefVecMap& regToRefVecMap,
686 ValueToDefVecMap& valueToDefVecMap)
688 const TargetInstrInfo& mii = target.getInstrInfo();
690 MachineOpCode opCode = node->getOpCode();
692 if (mii.isCall(opCode) || mii.isCCInstr(opCode))
693 callDepNodeVec.push_back(node);
695 if (mii.isLoad(opCode) || mii.isStore(opCode) || mii.isCall(opCode))
696 memNodeVec.push_back(node);
698 // Collect the register references and value defs. for explicit operands
700 const MachineInstr& minstr = *node->getMachineInstr();
701 for (int i=0, numOps = (int) minstr.getNumOperands(); i < numOps; i++)
703 const MachineOperand& mop = minstr.getOperand(i);
705 // if this references a register other than the hardwired
706 // "zero" register, record the reference.
707 if (mop.hasAllocatedReg())
709 int regNum = mop.getAllocatedRegNum();
711 // If this is not a dummy zero register, record the reference in order
712 if (regNum != target.getRegInfo().getZeroRegNum())
713 regToRefVecMap[mop.getAllocatedRegNum()]
714 .push_back(std::make_pair(node, i));
716 // If this is a volatile register, add the instruction to callDepVec
717 // (only if the node is not already on the callDepVec!)
718 if (callDepNodeVec.size() == 0 || callDepNodeVec.back() != node)
721 int regInClass = target.getRegInfo().getClassRegNum(regNum, rcid);
722 if (target.getRegInfo().getMachineRegClass(rcid)
723 ->isRegVolatile(regInClass))
724 callDepNodeVec.push_back(node);
727 continue; // nothing more to do
730 // ignore all other non-def operands
731 if (!minstr.getOperand(i).opIsDefOnly() &&
732 !minstr.getOperand(i).opIsDefAndUse())
735 // We must be defining a value.
736 assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
737 mop.getType() == MachineOperand::MO_CCRegister)
738 && "Do not expect any other kind of operand to be defined!");
739 assert(mop.getVRegValue() != NULL && "Null value being defined?");
741 valueToDefVecMap[mop.getVRegValue()].push_back(std::make_pair(node, i));
745 // Collect value defs. for implicit operands. They may have allocated
746 // physical registers also.
748 for (unsigned i=0, N = minstr.getNumImplicitRefs(); i != N; ++i)
750 const MachineOperand& mop = minstr.getImplicitOp(i);
751 if (mop.hasAllocatedReg())
753 int regNum = mop.getAllocatedRegNum();
754 if (regNum != target.getRegInfo().getZeroRegNum())
755 regToRefVecMap[mop.getAllocatedRegNum()]
756 .push_back(std::make_pair(node, i + minstr.getNumOperands()));
757 continue; // nothing more to do
760 if (mop.opIsDefOnly() || mop.opIsDefAndUse()) {
761 assert(minstr.getImplicitRef(i) != NULL && "Null value being defined?");
762 valueToDefVecMap[minstr.getImplicitRef(i)].push_back(std::make_pair(node,
770 SchedGraph::buildNodesForBB(const TargetMachine& target,
771 MachineBasicBlock& MBB,
772 std::vector<SchedGraphNode*>& memNodeVec,
773 std::vector<SchedGraphNode*>& callDepNodeVec,
774 RegToRefVecMap& regToRefVecMap,
775 ValueToDefVecMap& valueToDefVecMap)
777 const TargetInstrInfo& mii = target.getInstrInfo();
779 // Build graph nodes for each VM instruction and gather def/use info.
780 // Do both those together in a single pass over all machine instructions.
781 for (unsigned i=0; i < MBB.size(); i++)
782 if (!mii.isDummyPhiInstr(MBB[i]->getOpCode())) {
783 SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
784 noteGraphNodeForInstr(MBB[i], node);
786 // Remember all register references and value defs
787 findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec,
788 regToRefVecMap, valueToDefVecMap);
794 SchedGraph::buildGraph(const TargetMachine& target)
796 // Use this data structure to note all machine operands that compute
797 // ordinary LLVM values. These must be computed defs (i.e., instructions).
798 // Note that there may be multiple machine instructions that define
800 ValueToDefVecMap valueToDefVecMap;
802 // Use this data structure to note all memory instructions.
803 // We use this to add memory dependence edges without a second full walk.
804 std::vector<SchedGraphNode*> memNodeVec;
806 // Use this data structure to note all instructions that access physical
807 // registers that can be modified by a call (including call instructions)
808 std::vector<SchedGraphNode*> callDepNodeVec;
810 // Use this data structure to note any uses or definitions of
811 // machine registers so we can add edges for those later without
812 // extra passes over the nodes.
813 // The vector holds an ordered list of references to the machine reg,
814 // ordered according to control-flow order. This only works for a
815 // single basic block, hence the assertion. Each reference is identified
816 // by the pair: <node, operand-number>.
818 RegToRefVecMap regToRefVecMap;
820 // Make a dummy root node. We'll add edges to the real roots later.
821 graphRoot = new SchedGraphNode(0, NULL, -1, target);
822 graphLeaf = new SchedGraphNode(1, NULL, -1, target);
824 //----------------------------------------------------------------
825 // First add nodes for all the machine instructions in the basic block
826 // because this greatly simplifies identifying which edges to add.
827 // Do this one VM instruction at a time since the SchedGraphNode needs that.
828 // Also, remember the load/store instructions to add memory deps later.
829 //----------------------------------------------------------------
831 buildNodesForBB(target, MBB, memNodeVec, callDepNodeVec,
832 regToRefVecMap, valueToDefVecMap);
834 //----------------------------------------------------------------
835 // Now add edges for the following (all are incoming edges except (4)):
836 // (1) operands of the machine instruction, including hidden operands
837 // (2) machine register dependences
838 // (3) memory load/store dependences
839 // (3) other resource dependences for the machine instruction, if any
840 // (4) output dependences when multiple machine instructions define the
841 // same value; all must have been generated from a single VM instrn
842 // (5) control dependences to branch instructions generated for the
843 // terminator instruction of the BB. Because of delay slots and
844 // 2-way conditional branches, multiple CD edges are needed
845 // (see addCDEdges for details).
846 // Also, note any uses or defs of machine registers.
848 //----------------------------------------------------------------
850 // First, add edges to the terminator instruction of the basic block.
851 this->addCDEdges(MBB.getBasicBlock()->getTerminator(), target);
853 // Then add memory dep edges: store->load, load->store, and store->store.
854 // Call instructions are treated as both load and store.
855 this->addMemEdges(memNodeVec, target);
857 // Then add edges between call instructions and CC set/use instructions
858 this->addCallDepEdges(callDepNodeVec, target);
860 // Then add incoming def-use (SSA) edges for each machine instruction.
861 for (unsigned i=0, N=MBB.size(); i < N; i++)
862 addEdgesForInstruction(*MBB[i], valueToDefVecMap, target);
864 #ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
865 // Then add non-SSA edges for all VM instructions in the block.
866 // We assume that all machine instructions that define a value are
867 // generated from the VM instruction corresponding to that value.
868 // TODO: This could probably be done much more efficiently.
869 for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
870 this->addNonSSAEdgesForValue(*II, target);
871 #endif //NEED_SEPARATE_NONSSA_EDGES_CODE
873 // Then add edges for dependences on machine registers
874 this->addMachineRegEdges(regToRefVecMap, target);
876 // Finally, add edges from the dummy root and to dummy leaf
877 this->addDummyEdges();
882 // class SchedGraphSet
886 SchedGraphSet::SchedGraphSet(const Function* _function,
887 const TargetMachine& target) :
890 buildGraphsForMethod(method, target);
895 SchedGraphSet::~SchedGraphSet()
897 // delete all the graphs
898 for(iterator I = begin(), E = end(); I != E; ++I)
899 delete *I; // destructor is a friend
904 SchedGraphSet::dump() const
906 std::cerr << "======== Sched graphs for function `" << method->getName()
909 for (const_iterator I=begin(); I != end(); ++I)
912 std::cerr << "\n====== End graphs for function `" << method->getName()
918 SchedGraphSet::buildGraphsForMethod(const Function *F,
919 const TargetMachine& target)
921 MachineFunction &MF = MachineFunction::get(F);
922 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
923 addGraph(new SchedGraph(*I, target));
927 std::ostream &operator<<(std::ostream &os, const SchedGraphEdge& edge)
929 os << "edge [" << edge.src->getNodeId() << "] -> ["
930 << edge.sink->getNodeId() << "] : ";
932 switch(edge.depType) {
933 case SchedGraphEdge::CtrlDep: os<< "Control Dep"; break;
934 case SchedGraphEdge::ValueDep: os<< "Reg Value " << edge.val; break;
935 case SchedGraphEdge::MemoryDep: os<< "Memory Dep"; break;
936 case SchedGraphEdge::MachineRegister: os<< "Reg " <<edge.machineRegNum;break;
937 case SchedGraphEdge::MachineResource: os<<"Resource "<<edge.resourceId;break;
938 default: assert(0); break;
941 os << " : delay = " << edge.minDelay << "\n";
946 std::ostream &operator<<(std::ostream &os, const SchedGraphNode& node)
948 os << std::string(8, ' ')
949 << "Node " << node.nodeId << " : "
950 << "latency = " << node.latency << "\n" << std::string(12, ' ');
952 if (node.getMachineInstr() == NULL)
953 os << "(Dummy node)\n";
955 os << *node.getMachineInstr() << "\n" << std::string(12, ' ');
956 os << node.inEdges.size() << " Incoming Edges:\n";
957 for (unsigned i=0, N=node.inEdges.size(); i < N; i++)
958 os << std::string(16, ' ') << *node.inEdges[i];
960 os << std::string(12, ' ') << node.outEdges.size()
961 << " Outgoing Edges:\n";
962 for (unsigned i=0, N=node.outEdges.size(); i < N; i++)
963 os << std::string(16, ' ') << *node.outEdges[i];