1 //===- SchedGraph.cpp - Scheduling Graph Implementation -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Scheduling graph based on SSA graph plus extra dependence edges capturing
11 // dependences due to machine resources (machine registers, CC registers, and
14 //===----------------------------------------------------------------------===//
16 #include "SchedGraph.h"
17 #include "llvm/Function.h"
18 #include "llvm/iOther.h"
19 #include "llvm/CodeGen/MachineCodeForInstruction.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetRegInfo.h"
24 #include "Support/STLExtras.h"
26 //*********************** Internal Data Structures *************************/
28 // The following two types need to be classes, not typedefs, so we can use
29 // opaque declarations in SchedGraph.h
31 struct RefVec: public std::vector<std::pair<SchedGraphNode*, int> > {
32 typedef std::vector<std::pair<SchedGraphNode*,int> >::iterator iterator;
34 std::vector<std::pair<SchedGraphNode*,int> >::const_iterator const_iterator;
37 struct RegToRefVecMap: public hash_map<int, RefVec> {
38 typedef hash_map<int, RefVec>:: iterator iterator;
39 typedef hash_map<int, RefVec>::const_iterator const_iterator;
42 struct ValueToDefVecMap: public hash_map<const Value*, RefVec> {
43 typedef hash_map<const Value*, RefVec>:: iterator iterator;
44 typedef hash_map<const Value*, RefVec>::const_iterator const_iterator;
49 // class SchedGraphNode
52 SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb,
53 int indexInBB, const TargetMachine& Target)
54 : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(mbb ? (*mbb)[indexInBB] : 0) {
56 MachineOpCode mopCode = MI->getOpCode();
57 latency = Target.getInstrInfo().hasResultInterlock(mopCode)
58 ? Target.getInstrInfo().minLatency(mopCode)
59 : Target.getInstrInfo().maxLatency(mopCode);
64 // Method: SchedGraphNode Destructor
67 // Free memory allocated by the SchedGraphNode object.
70 // Do not delete the edges here. The base class will take care of that.
71 // Only handle subclass specific stuff here (where currently there is
74 SchedGraphNode::~SchedGraphNode() {
80 SchedGraph::SchedGraph(MachineBasicBlock &mbb, const TargetMachine& target)
86 // Method: SchedGraph Destructor
89 // This method deletes memory allocated by the SchedGraph object.
92 // Do not delete the graphRoot or graphLeaf here. The base class handles
95 SchedGraph::~SchedGraph() {
96 for (const_iterator I = begin(); I != end(); ++I)
100 void SchedGraph::dump() const {
101 std::cerr << " Sched Graph for Basic Block: ";
102 std::cerr << MBB.getBasicBlock()->getName()
103 << " (" << MBB.getBasicBlock() << ")";
105 std::cerr << "\n\n Actual Root nodes : ";
106 for (unsigned i=0, N=graphRoot->outEdges.size(); i < N; i++)
107 std::cerr << graphRoot->outEdges[i]->getSink()->getNodeId()
108 << ((i == N-1)? "" : ", ");
110 std::cerr << "\n Graph Nodes:\n";
111 for (const_iterator I=begin(); I != end(); ++I)
112 std::cerr << "\n" << *I->second;
119 void SchedGraph::addDummyEdges() {
120 assert(graphRoot->outEdges.size() == 0);
122 for (const_iterator I=begin(); I != end(); ++I) {
123 SchedGraphNode* node = (*I).second;
124 assert(node != graphRoot && node != graphLeaf);
125 if (node->beginInEdges() == node->endInEdges())
126 (void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep,
127 SchedGraphEdge::NonDataDep, 0);
128 if (node->beginOutEdges() == node->endOutEdges())
129 (void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep,
130 SchedGraphEdge::NonDataDep, 0);
135 void SchedGraph::addCDEdges(const TerminatorInst* term,
136 const TargetMachine& target) {
137 const TargetInstrInfo& mii = target.getInstrInfo();
138 MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
140 // Find the first branch instr in the sequence of machine instrs for term
143 while (! mii.isBranch(termMvec[first]->getOpCode()) &&
144 ! mii.isReturn(termMvec[first]->getOpCode()))
146 assert(first < termMvec.size() &&
147 "No branch instructions for terminator? Ok, but weird!");
148 if (first == termMvec.size())
151 SchedGraphNode* firstBrNode = getGraphNodeForInstr(termMvec[first]);
153 // Add CD edges from each instruction in the sequence to the
154 // *last preceding* branch instr. in the sequence
155 // Use a latency of 0 because we only need to prevent out-of-order issue.
157 for (unsigned i = termMvec.size(); i > first+1; --i) {
158 SchedGraphNode* toNode = getGraphNodeForInstr(termMvec[i-1]);
159 assert(toNode && "No node for instr generated for branch/ret?");
161 for (unsigned j = i-1; j != 0; --j)
162 if (mii.isBranch(termMvec[j-1]->getOpCode()) ||
163 mii.isReturn(termMvec[j-1]->getOpCode())) {
164 SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]);
165 assert(brNode && "No node for instr generated for branch/ret?");
166 (void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
167 SchedGraphEdge::NonDataDep, 0);
168 break; // only one incoming edge is enough
172 // Add CD edges from each instruction preceding the first branch
173 // to the first branch. Use a latency of 0 as above.
175 for (unsigned i = first; i != 0; --i) {
176 SchedGraphNode* fromNode = getGraphNodeForInstr(termMvec[i-1]);
177 assert(fromNode && "No node for instr generated for branch?");
178 (void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
179 SchedGraphEdge::NonDataDep, 0);
182 // Now add CD edges to the first branch instruction in the sequence from
183 // all preceding instructions in the basic block. Use 0 latency again.
185 for (unsigned i=0, N=MBB.size(); i < N; i++) {
186 if (MBB[i] == termMvec[first]) // reached the first branch
189 SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
190 if (fromNode == NULL)
191 continue; // dummy instruction, e.g., PHI
193 (void) new SchedGraphEdge(fromNode, firstBrNode,
194 SchedGraphEdge::CtrlDep,
195 SchedGraphEdge::NonDataDep, 0);
197 // If we find any other machine instructions (other than due to
198 // the terminator) that also have delay slots, add an outgoing edge
199 // from the instruction to the instructions in the delay slots.
201 unsigned d = mii.getNumDelaySlots(MBB[i]->getOpCode());
202 assert(i+d < N && "Insufficient delay slots for instruction?");
204 for (unsigned j=1; j <= d; j++) {
205 SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
206 assert(toNode && "No node for machine instr in delay slot?");
207 (void) new SchedGraphEdge(fromNode, toNode,
208 SchedGraphEdge::CtrlDep,
209 SchedGraphEdge::NonDataDep, 0);
214 static const int SG_LOAD_REF = 0;
215 static const int SG_STORE_REF = 1;
216 static const int SG_CALL_REF = 2;
218 static const unsigned int SG_DepOrderArray[][3] = {
219 { SchedGraphEdge::NonDataDep,
220 SchedGraphEdge::AntiDep,
221 SchedGraphEdge::AntiDep },
222 { SchedGraphEdge::TrueDep,
223 SchedGraphEdge::OutputDep,
224 SchedGraphEdge::TrueDep | SchedGraphEdge::OutputDep },
225 { SchedGraphEdge::TrueDep,
226 SchedGraphEdge::AntiDep | SchedGraphEdge::OutputDep,
227 SchedGraphEdge::TrueDep | SchedGraphEdge::AntiDep
228 | SchedGraphEdge::OutputDep }
232 // Add a dependence edge between every pair of machine load/store/call
233 // instructions, where at least one is a store or a call.
234 // Use latency 1 just to ensure that memory operations are ordered;
235 // latency does not otherwise matter (true dependences enforce that).
237 void SchedGraph::addMemEdges(const std::vector<SchedGraphNode*>& memNodeVec,
238 const TargetMachine& target) {
239 const TargetInstrInfo& mii = target.getInstrInfo();
241 // Instructions in memNodeVec are in execution order within the basic block,
242 // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
244 for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++) {
245 MachineOpCode fromOpCode = memNodeVec[im]->getOpCode();
246 int fromType = (mii.isCall(fromOpCode)? SG_CALL_REF
247 : (mii.isLoad(fromOpCode)? SG_LOAD_REF
249 for (unsigned jm=im+1; jm < NM; jm++) {
250 MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
251 int toType = (mii.isCall(toOpCode)? SG_CALL_REF
252 : (mii.isLoad(toOpCode)? SG_LOAD_REF
255 if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF)
256 (void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm],
257 SchedGraphEdge::MemoryDep,
258 SG_DepOrderArray[fromType][toType], 1);
263 // Add edges from/to CC reg instrs to/from call instrs.
264 // Essentially this prevents anything that sets or uses a CC reg from being
265 // reordered w.r.t. a call.
266 // Use a latency of 0 because we only need to prevent out-of-order issue,
267 // like with control dependences.
269 void SchedGraph::addCallDepEdges(const std::vector<SchedGraphNode*>& callDepNodeVec,
270 const TargetMachine& target) {
271 const TargetInstrInfo& mii = target.getInstrInfo();
273 // Instructions in memNodeVec are in execution order within the basic block,
274 // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
276 for (unsigned ic=0, NC=callDepNodeVec.size(); ic < NC; ic++)
277 if (mii.isCall(callDepNodeVec[ic]->getOpCode())) {
278 // Add SG_CALL_REF edges from all preds to this instruction.
279 for (unsigned jc=0; jc < ic; jc++)
280 (void) new SchedGraphEdge(callDepNodeVec[jc], callDepNodeVec[ic],
281 SchedGraphEdge::MachineRegister,
282 MachineIntRegsRID, 0);
284 // And do the same from this instruction to all successors.
285 for (unsigned jc=ic+1; jc < NC; jc++)
286 (void) new SchedGraphEdge(callDepNodeVec[ic], callDepNodeVec[jc],
287 SchedGraphEdge::MachineRegister,
288 MachineIntRegsRID, 0);
291 #ifdef CALL_DEP_NODE_VEC_CANNOT_WORK
292 // Find the call instruction nodes and put them in a vector.
293 std::vector<SchedGraphNode*> callNodeVec;
294 for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
295 if (mii.isCall(memNodeVec[im]->getOpCode()))
296 callNodeVec.push_back(memNodeVec[im]);
298 // Now walk the entire basic block, looking for CC instructions *and*
299 // call instructions, and keep track of the order of the instructions.
300 // Use the call node vec to quickly find earlier and later call nodes
301 // relative to the current CC instruction.
303 int lastCallNodeIdx = -1;
304 for (unsigned i=0, N=bbMvec.size(); i < N; i++)
305 if (mii.isCall(bbMvec[i]->getOpCode())) {
307 for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
308 if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
310 assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
312 else if (mii.isCCInstr(bbMvec[i]->getOpCode())) {
313 // Add incoming/outgoing edges from/to preceding/later calls
314 SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
316 for ( ; j <= lastCallNodeIdx; j++)
317 (void) new SchedGraphEdge(callNodeVec[j], ccNode,
318 MachineCCRegsRID, 0);
319 for ( ; j < (int) callNodeVec.size(); j++)
320 (void) new SchedGraphEdge(ccNode, callNodeVec[j],
321 MachineCCRegsRID, 0);
327 void SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
328 const TargetMachine& target) {
329 // This code assumes that two registers with different numbers are
332 for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
333 I != regToRefVecMap.end(); ++I) {
334 int regNum = (*I).first;
335 RefVec& regRefVec = (*I).second;
337 // regRefVec is ordered by control flow order in the basic block
338 for (unsigned i=0; i < regRefVec.size(); ++i) {
339 SchedGraphNode* node = regRefVec[i].first;
340 unsigned int opNum = regRefVec[i].second;
341 const MachineOperand& mop =
342 node->getMachineInstr()->getExplOrImplOperand(opNum);
343 bool isDef = mop.opIsDefOnly();
344 bool isDefAndUse = mop.opIsDefAndUse();
346 for (unsigned p=0; p < i; ++p) {
347 SchedGraphNode* prevNode = regRefVec[p].first;
348 if (prevNode != node) {
349 unsigned int prevOpNum = regRefVec[p].second;
350 const MachineOperand& prevMop =
351 prevNode->getMachineInstr()->getExplOrImplOperand(prevOpNum);
352 bool prevIsDef = prevMop.opIsDefOnly();
353 bool prevIsDefAndUse = prevMop.opIsDefAndUse();
356 new SchedGraphEdge(prevNode, node, regNum,
357 SchedGraphEdge::OutputDep);
358 if (!prevIsDef || prevIsDefAndUse)
359 new SchedGraphEdge(prevNode, node, regNum,
360 SchedGraphEdge::AntiDep);
364 if (!isDef || isDefAndUse)
365 new SchedGraphEdge(prevNode, node, regNum,
366 SchedGraphEdge::TrueDep);
374 // Adds dependences to/from refNode from/to all other defs
375 // in the basic block. refNode may be a use, a def, or both.
376 // We do not consider other uses because we are not building use-use deps.
378 void SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
379 const RefVec& defVec,
380 const Value* defValue,
382 bool refNodeIsDefAndUse,
383 const TargetMachine& target) {
384 bool refNodeIsUse = !refNodeIsDef || refNodeIsDefAndUse;
386 // Add true or output dep edges from all def nodes before refNode in BB.
387 // Add anti or output dep edges to all def nodes after refNode.
388 for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I) {
389 if ((*I).first == refNode)
390 continue; // Dont add any self-loops
392 if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB()) {
393 // (*).first is before refNode
395 (void) new SchedGraphEdge((*I).first, refNode, defValue,
396 SchedGraphEdge::OutputDep);
398 (void) new SchedGraphEdge((*I).first, refNode, defValue,
399 SchedGraphEdge::TrueDep);
401 // (*).first is after refNode
403 (void) new SchedGraphEdge(refNode, (*I).first, defValue,
404 SchedGraphEdge::OutputDep);
406 (void) new SchedGraphEdge(refNode, (*I).first, defValue,
407 SchedGraphEdge::AntiDep);
413 void SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
414 const ValueToDefVecMap& valueToDefVecMap,
415 const TargetMachine& target) {
416 SchedGraphNode* node = getGraphNodeForInstr(&MI);
420 // Add edges for all operands of the machine instruction.
422 for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i) {
423 switch (MI.getOperand(i).getType()) {
424 case MachineOperand::MO_VirtualRegister:
425 case MachineOperand::MO_CCRegister:
426 if (const Value* srcI = MI.getOperand(i).getVRegValue()) {
427 ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
428 if (I != valueToDefVecMap.end())
429 addEdgesForValue(node, I->second, srcI,
430 MI.getOperand(i).opIsDefOnly(),
431 MI.getOperand(i).opIsDefAndUse(), target);
435 case MachineOperand::MO_MachineRegister:
438 case MachineOperand::MO_SignExtendedImmed:
439 case MachineOperand::MO_UnextendedImmed:
440 case MachineOperand::MO_PCRelativeDisp:
441 break; // nothing to do for immediate fields
444 assert(0 && "Unknown machine operand type in SchedGraph builder");
449 // Add edges for values implicitly used by the machine instruction.
450 // Examples include function arguments to a Call instructions or the return
451 // value of a Ret instruction.
453 for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i)
454 if (MI.getImplicitOp(i).opIsUse() || MI.getImplicitOp(i).opIsDefAndUse())
455 if (const Value* srcI = MI.getImplicitRef(i)) {
456 ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
457 if (I != valueToDefVecMap.end())
458 addEdgesForValue(node, I->second, srcI,
459 MI.getImplicitOp(i).opIsDefOnly(),
460 MI.getImplicitOp(i).opIsDefAndUse(), target);
465 void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
466 SchedGraphNode* node,
467 std::vector<SchedGraphNode*>& memNodeVec,
468 std::vector<SchedGraphNode*>& callDepNodeVec,
469 RegToRefVecMap& regToRefVecMap,
470 ValueToDefVecMap& valueToDefVecMap) {
471 const TargetInstrInfo& mii = target.getInstrInfo();
473 MachineOpCode opCode = node->getOpCode();
475 if (mii.isCall(opCode) || mii.isCCInstr(opCode))
476 callDepNodeVec.push_back(node);
478 if (mii.isLoad(opCode) || mii.isStore(opCode) || mii.isCall(opCode))
479 memNodeVec.push_back(node);
481 // Collect the register references and value defs. for explicit operands
483 const MachineInstr& MI = *node->getMachineInstr();
484 for (int i=0, numOps = (int) MI.getNumOperands(); i < numOps; i++) {
485 const MachineOperand& mop = MI.getOperand(i);
487 // if this references a register other than the hardwired
488 // "zero" register, record the reference.
489 if (mop.hasAllocatedReg()) {
490 int regNum = mop.getAllocatedRegNum();
492 // If this is not a dummy zero register, record the reference in order
493 if (regNum != target.getRegInfo().getZeroRegNum())
494 regToRefVecMap[mop.getAllocatedRegNum()]
495 .push_back(std::make_pair(node, i));
497 // If this is a volatile register, add the instruction to callDepVec
498 // (only if the node is not already on the callDepVec!)
499 if (callDepNodeVec.size() == 0 || callDepNodeVec.back() != node)
502 int regInClass = target.getRegInfo().getClassRegNum(regNum, rcid);
503 if (target.getRegInfo().getMachineRegClass(rcid)
504 ->isRegVolatile(regInClass))
505 callDepNodeVec.push_back(node);
508 continue; // nothing more to do
511 // ignore all other non-def operands
512 if (!MI.getOperand(i).opIsDefOnly() &&
513 !MI.getOperand(i).opIsDefAndUse())
516 // We must be defining a value.
517 assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
518 mop.getType() == MachineOperand::MO_CCRegister)
519 && "Do not expect any other kind of operand to be defined!");
520 assert(mop.getVRegValue() != NULL && "Null value being defined?");
522 valueToDefVecMap[mop.getVRegValue()].push_back(std::make_pair(node, i));
526 // Collect value defs. for implicit operands. They may have allocated
527 // physical registers also.
529 for (unsigned i=0, N = MI.getNumImplicitRefs(); i != N; ++i) {
530 const MachineOperand& mop = MI.getImplicitOp(i);
531 if (mop.hasAllocatedReg()) {
532 int regNum = mop.getAllocatedRegNum();
533 if (regNum != target.getRegInfo().getZeroRegNum())
534 regToRefVecMap[mop.getAllocatedRegNum()]
535 .push_back(std::make_pair(node, i + MI.getNumOperands()));
536 continue; // nothing more to do
539 if (mop.opIsDefOnly() || mop.opIsDefAndUse()) {
540 assert(MI.getImplicitRef(i) != NULL && "Null value being defined?");
541 valueToDefVecMap[MI.getImplicitRef(i)].push_back(std::make_pair(node,
548 void SchedGraph::buildNodesForBB(const TargetMachine& target,
549 MachineBasicBlock& MBB,
550 std::vector<SchedGraphNode*>& memNodeVec,
551 std::vector<SchedGraphNode*>& callDepNodeVec,
552 RegToRefVecMap& regToRefVecMap,
553 ValueToDefVecMap& valueToDefVecMap) {
554 const TargetInstrInfo& mii = target.getInstrInfo();
556 // Build graph nodes for each VM instruction and gather def/use info.
557 // Do both those together in a single pass over all machine instructions.
558 for (unsigned i=0; i < MBB.size(); i++)
559 if (!mii.isDummyPhiInstr(MBB[i]->getOpCode())) {
560 SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
561 noteGraphNodeForInstr(MBB[i], node);
563 // Remember all register references and value defs
564 findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec,
565 regToRefVecMap, valueToDefVecMap);
570 void SchedGraph::buildGraph(const TargetMachine& target) {
571 // Use this data structure to note all machine operands that compute
572 // ordinary LLVM values. These must be computed defs (i.e., instructions).
573 // Note that there may be multiple machine instructions that define
575 ValueToDefVecMap valueToDefVecMap;
577 // Use this data structure to note all memory instructions.
578 // We use this to add memory dependence edges without a second full walk.
579 std::vector<SchedGraphNode*> memNodeVec;
581 // Use this data structure to note all instructions that access physical
582 // registers that can be modified by a call (including call instructions)
583 std::vector<SchedGraphNode*> callDepNodeVec;
585 // Use this data structure to note any uses or definitions of
586 // machine registers so we can add edges for those later without
587 // extra passes over the nodes.
588 // The vector holds an ordered list of references to the machine reg,
589 // ordered according to control-flow order. This only works for a
590 // single basic block, hence the assertion. Each reference is identified
591 // by the pair: <node, operand-number>.
593 RegToRefVecMap regToRefVecMap;
595 // Make a dummy root node. We'll add edges to the real roots later.
596 graphRoot = new SchedGraphNode(0, NULL, -1, target);
597 graphLeaf = new SchedGraphNode(1, NULL, -1, target);
599 //----------------------------------------------------------------
600 // First add nodes for all the machine instructions in the basic block
601 // because this greatly simplifies identifying which edges to add.
602 // Do this one VM instruction at a time since the SchedGraphNode needs that.
603 // Also, remember the load/store instructions to add memory deps later.
604 //----------------------------------------------------------------
606 buildNodesForBB(target, MBB, memNodeVec, callDepNodeVec,
607 regToRefVecMap, valueToDefVecMap);
609 //----------------------------------------------------------------
610 // Now add edges for the following (all are incoming edges except (4)):
611 // (1) operands of the machine instruction, including hidden operands
612 // (2) machine register dependences
613 // (3) memory load/store dependences
614 // (3) other resource dependences for the machine instruction, if any
615 // (4) output dependences when multiple machine instructions define the
616 // same value; all must have been generated from a single VM instrn
617 // (5) control dependences to branch instructions generated for the
618 // terminator instruction of the BB. Because of delay slots and
619 // 2-way conditional branches, multiple CD edges are needed
620 // (see addCDEdges for details).
621 // Also, note any uses or defs of machine registers.
623 //----------------------------------------------------------------
625 // First, add edges to the terminator instruction of the basic block.
626 this->addCDEdges(MBB.getBasicBlock()->getTerminator(), target);
628 // Then add memory dep edges: store->load, load->store, and store->store.
629 // Call instructions are treated as both load and store.
630 this->addMemEdges(memNodeVec, target);
632 // Then add edges between call instructions and CC set/use instructions
633 this->addCallDepEdges(callDepNodeVec, target);
635 // Then add incoming def-use (SSA) edges for each machine instruction.
636 for (unsigned i=0, N=MBB.size(); i < N; i++)
637 addEdgesForInstruction(*MBB[i], valueToDefVecMap, target);
639 #ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
640 // Then add non-SSA edges for all VM instructions in the block.
641 // We assume that all machine instructions that define a value are
642 // generated from the VM instruction corresponding to that value.
643 // TODO: This could probably be done much more efficiently.
644 for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
645 this->addNonSSAEdgesForValue(*II, target);
646 #endif //NEED_SEPARATE_NONSSA_EDGES_CODE
648 // Then add edges for dependences on machine registers
649 this->addMachineRegEdges(regToRefVecMap, target);
651 // Finally, add edges from the dummy root and to dummy leaf
652 this->addDummyEdges();
657 // class SchedGraphSet
659 SchedGraphSet::SchedGraphSet(const Function* _function,
660 const TargetMachine& target) :
661 function(_function) {
662 buildGraphsForMethod(function, target);
665 SchedGraphSet::~SchedGraphSet() {
666 // delete all the graphs
667 for(iterator I = begin(), E = end(); I != E; ++I)
668 delete *I; // destructor is a friend
672 void SchedGraphSet::dump() const {
673 std::cerr << "======== Sched graphs for function `" << function->getName()
676 for (const_iterator I=begin(); I != end(); ++I)
679 std::cerr << "\n====== End graphs for function `" << function->getName()
684 void SchedGraphSet::buildGraphsForMethod(const Function *F,
685 const TargetMachine& target) {
686 MachineFunction &MF = MachineFunction::get(F);
687 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
688 addGraph(new SchedGraph(*I, target));
692 void SchedGraphEdge::print(std::ostream &os) const {
693 os << "edge [" << src->getNodeId() << "] -> ["
694 << sink->getNodeId() << "] : ";
697 case SchedGraphEdge::CtrlDep:
700 case SchedGraphEdge::ValueDep:
701 os<< "Reg Value " << val;
703 case SchedGraphEdge::MemoryDep:
706 case SchedGraphEdge::MachineRegister:
707 os<< "Reg " << machineRegNum;
709 case SchedGraphEdge::MachineResource:
710 os<<"Resource "<< resourceId;
717 os << " : delay = " << minDelay << "\n";
720 void SchedGraphNode::print(std::ostream &os) const {
721 os << std::string(8, ' ')
722 << "Node " << ID << " : "
723 << "latency = " << latency << "\n" << std::string(12, ' ');
725 if (getMachineInstr() == NULL)
726 os << "(Dummy node)\n";
728 os << *getMachineInstr() << "\n" << std::string(12, ' ');
729 os << inEdges.size() << " Incoming Edges:\n";
730 for (unsigned i=0, N = inEdges.size(); i < N; i++)
731 os << std::string(16, ' ') << *inEdges[i];
733 os << std::string(12, ' ') << outEdges.size()
734 << " Outgoing Edges:\n";
735 for (unsigned i=0, N= outEdges.size(); i < N; i++)
736 os << std::string(16, ' ') << *outEdges[i];