1 //===-- InstrSelectionSupport.cpp -----------------------------------------===//
3 // Target-independent instruction selection code. See SparcInstrSelection.cpp
6 //===----------------------------------------------------------------------===//
8 #include "llvm/CodeGen/InstrSelectionSupport.h"
9 #include "llvm/CodeGen/InstrSelection.h"
10 #include "llvm/CodeGen/MachineInstrAnnot.h"
11 #include "llvm/CodeGen/MachineCodeForInstruction.h"
12 #include "llvm/CodeGen/InstrForest.h"
13 #include "llvm/Target/TargetMachine.h"
14 #include "llvm/Target/TargetRegInfo.h"
15 #include "llvm/Target/TargetInstrInfo.h"
16 #include "llvm/Constants.h"
17 #include "llvm/BasicBlock.h"
18 #include "llvm/DerivedTypes.h"
21 //*************************** Local Functions ******************************/
24 // Generate code to load the constant into a TmpInstruction (virtual reg) and
25 // returns the virtual register.
27 static TmpInstruction*
28 InsertCodeToLoadConstant(Function *F,
31 vector<MachineInstr*>& loadConstVec,
32 TargetMachine& target)
34 // Create a tmp virtual register to hold the constant.
35 TmpInstruction* tmpReg = new TmpInstruction(opValue);
36 MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(vmInstr);
39 target.getInstrInfo().CreateCodeToLoadConst(target, F, opValue, tmpReg,
42 // Record the mapping from the tmp VM instruction to machine instruction.
43 // Do this for all machine instructions that were not mapped to any
44 // other temp values created by
45 // tmpReg->addMachineInstruction(loadConstVec.back());
51 MachineOperand::MachineOperandType
52 ChooseRegOrImmed(int64_t intValue,
55 const TargetMachine& target,
57 unsigned int& getMachineRegNum,
58 int64_t& getImmedValue)
60 MachineOperand::MachineOperandType opType=MachineOperand::MO_VirtualRegister;
65 target.getInstrInfo().constantFitsInImmedField(opCode, intValue))
67 opType = isSigned? MachineOperand::MO_SignExtendedImmed
68 : MachineOperand::MO_UnextendedImmed;
69 getImmedValue = intValue;
71 else if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0)
73 opType = MachineOperand::MO_MachineRegister;
74 getMachineRegNum = target.getRegInfo().getZeroRegNum();
81 MachineOperand::MachineOperandType
82 ChooseRegOrImmed(Value* val,
84 const TargetMachine& target,
86 unsigned int& getMachineRegNum,
87 int64_t& getImmedValue)
92 // To use reg or immed, constant needs to be integer, bool, or a NULL pointer
93 Constant *CPV = dyn_cast<Constant>(val);
95 (! CPV->getType()->isIntegral() &&
96 ! (isa<PointerType>(CPV->getType()) && CPV->isNullValue())))
97 return MachineOperand::MO_VirtualRegister;
99 // Now get the constant value and check if it fits in the IMMED field.
100 // Take advantage of the fact that the max unsigned value will rarely
101 // fit into any IMMED field and ignore that case (i.e., cast smaller
102 // unsigned constants to signed).
105 if (isa<PointerType>(CPV->getType()))
106 intValue = 0; // We checked above that it is NULL
107 else if (ConstantBool* CB = dyn_cast<ConstantBool>(CPV))
108 intValue = (int64_t) CB->getValue();
109 else if (CPV->getType()->isSigned())
110 intValue = cast<ConstantSInt>(CPV)->getValue();
112 { // get the int value and sign-extend if original was less than 64 bits
113 intValue = (int64_t) cast<ConstantUInt>(CPV)->getValue();
114 switch(CPV->getType()->getPrimitiveID())
116 case Type::UByteTyID: intValue = (int64_t) (int8_t) intValue; break;
117 case Type::UShortTyID: intValue = (int64_t) (short) intValue; break;
118 case Type::UIntTyID: intValue = (int64_t) (int) intValue; break;
123 return ChooseRegOrImmed(intValue, CPV->getType()->isSigned(),
124 opCode, target, canUseImmed,
125 getMachineRegNum, getImmedValue);
130 //---------------------------------------------------------------------------
131 // Function: FixConstantOperandsForInstr
134 // Special handling for constant operands of a machine instruction
135 // -- if the constant is 0, use the hardwired 0 register, if any;
136 // -- if the constant fits in the IMMEDIATE field, use that field;
137 // -- else create instructions to put the constant into a register, either
138 // directly or by loading explicitly from the constant pool.
140 // In the first 2 cases, the operand of `minstr' is modified in place.
141 // Returns a vector of machine instructions generated for operands that
142 // fall under case 3; these must be inserted before `minstr'.
143 //---------------------------------------------------------------------------
145 vector<MachineInstr*>
146 FixConstantOperandsForInstr(Instruction* vmInstr,
147 MachineInstr* minstr,
148 TargetMachine& target)
150 vector<MachineInstr*> MVec;
152 MachineOpCode opCode = minstr->getOpCode();
153 const TargetInstrInfo& instrInfo = target.getInstrInfo();
154 int resultPos = instrInfo.getResultPos(opCode);
155 int immedPos = instrInfo.getImmedConstantPos(opCode);
157 Function *F = vmInstr->getParent()->getParent();
159 for (unsigned op=0; op < minstr->getNumOperands(); op++)
161 const MachineOperand& mop = minstr->getOperand(op);
163 // Skip the result position, preallocated machine registers, or operands
164 // that cannot be constants (CC regs or PC-relative displacements)
165 if (resultPos == (int)op ||
166 mop.getType() == MachineOperand::MO_MachineRegister ||
167 mop.getType() == MachineOperand::MO_CCRegister ||
168 mop.getType() == MachineOperand::MO_PCRelativeDisp)
171 bool constantThatMustBeLoaded = false;
172 unsigned int machineRegNum = 0;
173 int64_t immedValue = 0;
174 Value* opValue = NULL;
175 MachineOperand::MachineOperandType opType =
176 MachineOperand::MO_VirtualRegister;
178 // Operand may be a virtual register or a compile-time constant
179 if (mop.getType() == MachineOperand::MO_VirtualRegister)
181 assert(mop.getVRegValue() != NULL);
182 opValue = mop.getVRegValue();
183 if (Constant *opConst = dyn_cast<Constant>(opValue)) {
184 opType = ChooseRegOrImmed(opConst, opCode, target,
185 (immedPos == (int)op), machineRegNum,
187 if (opType == MachineOperand::MO_VirtualRegister)
188 constantThatMustBeLoaded = true;
193 assert(mop.isImmediate());
194 bool isSigned = mop.getType() == MachineOperand::MO_SignExtendedImmed;
196 // Bit-selection flags indicate an instruction that is extracting
197 // bits from its operand so ignore this even if it is a big constant.
198 if (mop.opHiBits32() || mop.opLoBits32() ||
199 mop.opHiBits64() || mop.opLoBits64())
202 opType = ChooseRegOrImmed(mop.getImmedValue(), isSigned,
203 opCode, target, (immedPos == (int)op),
204 machineRegNum, immedValue);
206 if (opType == mop.getType())
207 continue; // no change: this is the most common case
209 if (opType == MachineOperand::MO_VirtualRegister)
211 constantThatMustBeLoaded = true;
213 ? (Value*)ConstantSInt::get(Type::LongTy, immedValue)
214 : (Value*)ConstantUInt::get(Type::ULongTy,(uint64_t)immedValue);
218 if (opType == MachineOperand::MO_MachineRegister)
219 minstr->SetMachineOperandReg(op, machineRegNum);
220 else if (opType == MachineOperand::MO_SignExtendedImmed ||
221 opType == MachineOperand::MO_UnextendedImmed)
222 minstr->SetMachineOperandConst(op, opType, immedValue);
223 else if (constantThatMustBeLoaded ||
224 (opValue && isa<GlobalValue>(opValue)))
225 { // opValue is a constant that must be explicitly loaded into a reg
227 TmpInstruction* tmpReg = InsertCodeToLoadConstant(F, opValue, vmInstr,
229 minstr->SetMachineOperandVal(op, MachineOperand::MO_VirtualRegister,
234 // Also, check for implicit operands used by the machine instruction
235 // (no need to check those defined since they cannot be constants).
237 // -- arguments to a Call
238 // -- return value of a Return
239 // Any such operand that is a constant value needs to be fixed also.
240 // The current instructions with implicit refs (viz., Call and Return)
241 // have no immediate fields, so the constant always needs to be loaded
244 bool isCall = instrInfo.isCall(opCode);
245 unsigned lastCallArgNum = 0; // unused if not a call
246 CallArgsDescriptor* argDesc = NULL; // unused if not a call
248 argDesc = CallArgsDescriptor::get(minstr);
250 for (unsigned i=0, N=minstr->getNumImplicitRefs(); i < N; ++i)
251 if (isa<Constant>(minstr->getImplicitRef(i)) ||
252 isa<GlobalValue>(minstr->getImplicitRef(i)))
254 Value* oldVal = minstr->getImplicitRef(i);
255 TmpInstruction* tmpReg =
256 InsertCodeToLoadConstant(F, oldVal, vmInstr, MVec, target);
257 minstr->setImplicitRef(i, tmpReg);
260 { // find and replace the argument in the CallArgsDescriptor
261 unsigned i=lastCallArgNum;
262 while (argDesc->getArgInfo(i).getArgVal() != oldVal)
264 assert(i < argDesc->getNumArgs() &&
265 "Constant operands to a call *must* be in the arg list");
267 argDesc->getArgInfo(i).replaceArgVal(tmpReg);