1 //===-- InterferenceCache.h - Caching per-block interference ---*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // InterferenceCache remembers per-block interference in LiveIntervalUnions.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_INTERFERENCECACHE
15 #define LLVM_CODEGEN_INTERFERENCECACHE
17 #include "LiveIntervalUnion.h"
21 class InterferenceCache {
22 const TargetRegisterInfo *TRI;
23 LiveIntervalUnion *LIUArray;
27 /// BlockInterference - information about the interference in a single basic
29 struct BlockInterference {
30 BlockInterference() : Tag(0) {}
36 /// Entry - A cache entry containing interference information for all aliases
37 /// of PhysReg in all basic blocks.
39 /// PhysReg - The register currently represented.
42 /// Tag - Cache tag is changed when any of the underlying LiveIntervalUnions
46 /// MF - The current function.
49 /// Indexes - Mapping block numbers to SlotIndex ranges.
52 /// PrevPos - The previous position the iterators were moved to.
55 /// AliasTags - A LiveIntervalUnion pointer and tag for each alias of
57 SmallVector<std::pair<LiveIntervalUnion*, unsigned>, 8> Aliases;
59 typedef LiveIntervalUnion::SegmentIter Iter;
61 /// Iters - an iterator for each alias
62 SmallVector<Iter, 8> Iters;
64 /// Blocks - Interference for each block in the function.
65 SmallVector<BlockInterference, 8> Blocks;
67 /// update - Recompute Blocks[MBBNum]
68 void update(unsigned MBBNum);
71 Entry() : PhysReg(0), Tag(0), Indexes(0) {}
73 void clear(MachineFunction *mf, SlotIndexes *indexes) {
79 unsigned getPhysReg() const { return PhysReg; }
83 /// valid - Return true if this is a valid entry for physReg.
84 bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
86 /// reset - Initialize entry to represent physReg's aliases.
87 void reset(unsigned physReg,
88 LiveIntervalUnion *LIUArray,
89 const TargetRegisterInfo *TRI,
90 const MachineFunction *MF);
92 /// get - Return an up to date BlockInterference.
93 BlockInterference *get(unsigned MBBNum) {
94 if (Blocks[MBBNum].Tag != Tag)
96 return &Blocks[MBBNum];
100 // We don't keep a cache entry for every physical register, that would use too
101 // much memory. Instead, a fixed number of cache entries are used in a round-
103 enum { CacheEntries = 32 };
105 // Point to an entry for each physreg. The entry pointed to may not be up to
106 // date, and it may have been reused for a different physreg.
107 SmallVector<unsigned char, 2> PhysRegEntries;
109 // Next round-robin entry to be picked.
112 // The actual cache entries.
113 Entry Entries[CacheEntries];
115 // get - Get a valid entry for PhysReg.
116 Entry *get(unsigned PhysReg);
119 InterferenceCache() : TRI(0), LIUArray(0), Indexes(0), MF(0), RoundRobin(0) {}
121 /// init - Prepare cache for a new function.
122 void init(MachineFunction*, LiveIntervalUnion*, SlotIndexes*,
123 const TargetRegisterInfo *);
125 /// Cursor - The primary query interface for the block interference cache.
128 BlockInterference *Current;
130 /// Cursor - Create a cursor for the interference allocated to PhysReg and
132 Cursor(InterferenceCache &Cache, unsigned PhysReg)
133 : CacheEntry(Cache.get(PhysReg)), Current(0) {}
135 /// moveTo - Move cursor to basic block MBBNum.
136 void moveToBlock(unsigned MBBNum) {
137 Current = CacheEntry->get(MBBNum);
140 /// hasInterference - Return true if the current block has any interference.
141 bool hasInterference() {
142 return Current->First.isValid();
145 /// first - Return the starting index of the first interfering range in the
148 return Current->First;
151 /// last - Return the ending index of the last interfering range in the
154 return Current->Last;