1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LLVMTargetMachine class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Pass.h"
17 #include "llvm/Analysis/Verifier.h"
18 #include "llvm/Assembly/PrintModulePass.h"
19 #include "llvm/CodeGen/AsmPrinter.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/GCStrategy.h"
22 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/MC/MCAsmInfo.h"
25 #include "llvm/MC/MCContext.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/Target/TargetData.h"
28 #include "llvm/Target/TargetRegistry.h"
29 #include "llvm/Transforms/Scalar.h"
30 #include "llvm/ADT/OwningPtr.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/FormattedStream.h"
40 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
41 cl::desc("Disable Post Regalloc"));
42 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
43 cl::desc("Disable branch folding"));
44 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
45 cl::desc("Disable tail duplication"));
46 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
47 cl::desc("Disable pre-register allocation tail duplication"));
48 static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
49 cl::desc("Disable code placement"));
50 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
51 cl::desc("Disable Stack Slot Coloring"));
52 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
53 cl::desc("Disable Machine LICM"));
54 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
55 cl::desc("Disable Machine Sinking"));
56 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
57 cl::desc("Disable Loop Strength Reduction Pass"));
58 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
59 cl::desc("Disable Codegen Prepare"));
60 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
61 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
62 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
63 cl::desc("Print LLVM IR input to isel pass"));
64 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
65 cl::desc("Dump garbage collector data"));
66 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
67 cl::desc("Verify generated machine code"),
68 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
70 static cl::opt<cl::boolOrDefault>
71 AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
72 cl::init(cl::BOU_UNSET));
74 static bool getVerboseAsm() {
77 case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
78 case cl::BOU_TRUE: return true;
79 case cl::BOU_FALSE: return false;
83 // Enable or disable FastISel. Both options are needed, because
84 // FastISel is enabled by default with -fast, and we wish to be
85 // able to enable or disable fast-isel independently from -O0.
86 static cl::opt<cl::boolOrDefault>
87 EnableFastISelOption("fast-isel", cl::Hidden,
88 cl::desc("Enable the \"fast\" instruction selector"));
90 // Enable or disable an experimental optimization to split GEPs
91 // and run a special GVN pass which does not examine loads, in
92 // an effort to factor out redundancy implicit in complex GEPs.
93 static cl::opt<bool> EnableSplitGEPGVN("split-gep-gvn", cl::Hidden,
94 cl::desc("Split GEPs and run no-load GVN"));
96 LLVMTargetMachine::LLVMTargetMachine(const Target &T,
97 const std::string &Triple)
98 : TargetMachine(T), TargetTriple(Triple) {
99 AsmInfo = T.createAsmInfo(TargetTriple);
102 // Set the default code model for the JIT for a generic target.
103 // FIXME: Is small right here? or .is64Bit() ? Large : Small?
105 LLVMTargetMachine::setCodeModelForJIT() {
106 setCodeModel(CodeModel::Small);
109 // Set the default code model for static compilation for a generic target.
111 LLVMTargetMachine::setCodeModelForStatic() {
112 setCodeModel(CodeModel::Small);
115 bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
116 formatted_raw_ostream &Out,
117 CodeGenFileType FileType,
118 CodeGenOpt::Level OptLevel,
119 bool DisableVerify) {
120 // Add common CodeGen passes.
121 if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify))
124 OwningPtr<MCContext> Context(new MCContext());
125 OwningPtr<MCStreamer> AsmStreamer;
127 formatted_raw_ostream *LegacyOutput;
129 default: return true;
130 case CGFT_AssemblyFile: {
131 const MCAsmInfo &MAI = *getMCAsmInfo();
132 MCInstPrinter *InstPrinter =
133 getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI, Out);
134 AsmStreamer.reset(createAsmStreamer(*Context, Out, MAI,
135 getTargetData()->isLittleEndian(),
136 getVerboseAsm(), InstPrinter,
138 // Set the AsmPrinter's "O" to the output file.
142 case CGFT_ObjectFile: {
143 // Create the code emitter for the target if it exists. If not, .o file
145 MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context);
146 TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);
147 if (MCE == 0 || TAB == 0)
150 AsmStreamer.reset(createMachOStreamer(*Context, *TAB, Out, MCE));
152 // Any output to the asmprinter's "O" stream is bad and needs to be fixed,
153 // force it to come out stderr.
154 // FIXME: this is horrible and leaks, eventually remove the raw_ostream from
156 LegacyOutput = new formatted_raw_ostream(errs());
160 // The Null output is intended for use for performance analysis and testing,
162 AsmStreamer.reset(createNullStreamer(*Context));
163 // Any output to the asmprinter's "O" stream is bad and needs to be fixed,
164 // force it to come out stderr.
165 // FIXME: this is horrible and leaks, eventually remove the raw_ostream from
167 LegacyOutput = new formatted_raw_ostream(errs());
171 // Create the AsmPrinter, which takes ownership of Context and AsmStreamer
173 FunctionPass *Printer =
174 getTarget().createAsmPrinter(*LegacyOutput, *this, *Context, *AsmStreamer,
179 // If successful, createAsmPrinter took ownership of AsmStreamer and Context.
180 Context.take(); AsmStreamer.take();
184 // Make sure the code model is set.
185 setCodeModelForStatic();
186 PM.add(createGCInfoDeleter());
190 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
191 /// get machine code emitted. This uses a JITCodeEmitter object to handle
192 /// actually outputting the machine code and resolving things like the address
193 /// of functions. This method should returns true if machine code emission is
196 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
198 CodeGenOpt::Level OptLevel,
199 bool DisableVerify) {
200 // Make sure the code model is set.
201 setCodeModelForJIT();
203 // Add common CodeGen passes.
204 if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify))
207 addCodeEmitter(PM, OptLevel, JCE);
208 PM.add(createGCInfoDeleter());
210 return false; // success!
213 static void printNoVerify(PassManagerBase &PM,
214 const char *Banner) {
215 if (PrintMachineCode)
216 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
219 static void printAndVerify(PassManagerBase &PM,
221 bool allowDoubleDefs = false) {
222 if (PrintMachineCode)
223 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
225 if (VerifyMachineCode)
226 PM.add(createMachineVerifierPass(allowDoubleDefs));
229 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
230 /// emitting to assembly files or machine code output.
232 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
233 CodeGenOpt::Level OptLevel,
234 bool DisableVerify) {
235 // Standard LLVM-Level Passes.
237 // Before running any passes, run the verifier to determine if the input
238 // coming from the front-end and/or optimizer is valid.
240 PM.add(createVerifierPass());
242 // Optionally, tun split-GEPs and no-load GVN.
243 if (EnableSplitGEPGVN) {
244 PM.add(createGEPSplitterPass());
245 PM.add(createGVNPass(/*NoLoads=*/true));
248 // Run loop strength reduction before anything else.
249 if (OptLevel != CodeGenOpt::None && !DisableLSR) {
250 PM.add(createLoopStrengthReducePass(getTargetLowering()));
252 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
255 // Turn exception handling constructs into something the code generators can
257 switch (getMCAsmInfo()->getExceptionHandlingType())
259 case ExceptionHandling::SjLj:
260 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
261 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
262 // catch info can get misplaced when a selector ends up more than one block
263 // removed from the parent invoke(s). This could happen when a landing
264 // pad is shared by multiple invokes and is also a target of a normal
265 // edge from elsewhere.
266 PM.add(createSjLjEHPass(getTargetLowering()));
267 PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
269 case ExceptionHandling::Dwarf:
270 PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
272 case ExceptionHandling::None:
273 PM.add(createLowerInvokePass(getTargetLowering()));
277 PM.add(createGCLoweringPass());
279 // Make sure that no unreachable blocks are instruction selected.
280 PM.add(createUnreachableBlockEliminationPass());
282 if (OptLevel != CodeGenOpt::None && !DisableCGP)
283 PM.add(createCodeGenPreparePass(getTargetLowering()));
285 PM.add(createStackProtectorPass(getTargetLowering()));
288 PM.add(createPrintFunctionPass("\n\n"
289 "*** Final LLVM Code input to ISel ***\n",
292 // All passes which modify the LLVM IR are now complete; run the verifier
293 // to ensure that the IR is valid.
295 PM.add(createVerifierPass());
297 // Standard Lower-Level Passes.
299 // Set up a MachineFunction for the rest of CodeGen to work on.
300 PM.add(new MachineFunctionAnalysis(*this, OptLevel));
302 // Enable FastISel with -fast, but allow that to be overridden.
303 if (EnableFastISelOption == cl::BOU_TRUE ||
304 (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
305 EnableFastISel = true;
307 // Ask the target for an isel.
308 if (addInstSelector(PM, OptLevel))
311 // Print the instruction selected machine code...
312 printAndVerify(PM, "After Instruction Selection",
313 /* allowDoubleDefs= */ true);
315 // Optimize PHIs before DCE: removing dead PHI cycles may make more
316 // instructions dead.
317 if (OptLevel != CodeGenOpt::None)
318 PM.add(createOptimizePHIsPass());
320 // Delete dead machine instructions regardless of optimization level.
321 PM.add(createDeadMachineInstructionElimPass());
322 printAndVerify(PM, "After codegen DCE pass",
323 /* allowDoubleDefs= */ true);
325 if (OptLevel != CodeGenOpt::None) {
326 PM.add(createOptimizeExtsPass());
327 if (!DisableMachineLICM)
328 PM.add(createMachineLICMPass());
329 PM.add(createMachineCSEPass());
330 if (!DisableMachineSink)
331 PM.add(createMachineSinkingPass());
332 printAndVerify(PM, "After Machine LICM, CSE and Sinking passes",
333 /* allowDoubleDefs= */ true);
336 // Pre-ra tail duplication.
337 if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
338 PM.add(createTailDuplicatePass(true));
339 printAndVerify(PM, "After Pre-RegAlloc TailDuplicate",
340 /* allowDoubleDefs= */ true);
343 // Run pre-ra passes.
344 if (addPreRegAlloc(PM, OptLevel))
345 printAndVerify(PM, "After PreRegAlloc passes",
346 /* allowDoubleDefs= */ true);
348 // Perform register allocation.
349 PM.add(createRegisterAllocator());
350 printAndVerify(PM, "After Register Allocation");
352 // Perform stack slot coloring.
353 if (OptLevel != CodeGenOpt::None && !DisableSSC) {
354 // FIXME: Re-enable coloring with register when it's capable of adding
356 PM.add(createStackSlotColoringPass(false));
357 printAndVerify(PM, "After StackSlotColoring");
360 // Run post-ra passes.
361 if (addPostRegAlloc(PM, OptLevel))
362 printAndVerify(PM, "After PostRegAlloc passes");
364 PM.add(createLowerSubregsPass());
365 printAndVerify(PM, "After LowerSubregs");
367 // Insert prolog/epilog code. Eliminate abstract frame index references...
368 PM.add(createPrologEpilogCodeInserter());
369 printAndVerify(PM, "After PrologEpilogCodeInserter");
371 // Run pre-sched2 passes.
372 if (addPreSched2(PM, OptLevel))
373 printAndVerify(PM, "After PreSched2 passes");
375 // Second pass scheduler.
376 if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
377 PM.add(createPostRAScheduler(OptLevel));
378 printAndVerify(PM, "After PostRAScheduler");
381 // Branch folding must be run after regalloc and prolog/epilog insertion.
382 if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
383 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
384 printNoVerify(PM, "After BranchFolding");
388 if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
389 PM.add(createTailDuplicatePass(false));
390 printNoVerify(PM, "After TailDuplicate");
393 PM.add(createGCMachineCodeAnalysisPass());
396 PM.add(createGCInfoPrinter(dbgs()));
398 if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
399 PM.add(createCodePlacementOptPass());
400 printNoVerify(PM, "After CodePlacementOpt");
403 if (addPreEmitPass(PM, OptLevel))
404 printNoVerify(PM, "After PreEmit passes");