1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LLVMTargetMachine class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Pass.h"
17 #include "llvm/Assembly/PrintModulePass.h"
18 #include "llvm/CodeGen/AsmPrinter.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/GCStrategy.h"
21 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/MC/MCAsmInfo.h"
24 #include "llvm/Target/TargetRegistry.h"
25 #include "llvm/Transforms/Scalar.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/FormattedStream.h"
34 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
35 cl::desc("Disable Post Regalloc"));
36 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
37 cl::desc("Disable branch folding"));
38 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
39 cl::desc("Disable tail duplication"));
40 static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
41 cl::desc("Disable code placement"));
42 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
43 cl::desc("Disable Stack Slot Coloring"));
44 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
45 cl::desc("Disable Machine LICM"));
46 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
47 cl::desc("Disable Machine Sinking"));
48 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
49 cl::desc("Disable Loop Strength Reduction Pass"));
50 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
51 cl::desc("Disable Codegen Prepare"));
52 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
53 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
54 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
55 cl::desc("Print LLVM IR input to isel pass"));
56 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
57 cl::desc("Dump emitter generated instructions as assembly"));
58 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
59 cl::desc("Dump garbage collector data"));
60 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
61 cl::desc("Verify generated machine code"),
62 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
64 // Enable or disable FastISel. Both options are needed, because
65 // FastISel is enabled by default with -fast, and we wish to be
66 // able to enable or disable fast-isel independently from -O0.
67 static cl::opt<cl::boolOrDefault>
68 EnableFastISelOption("fast-isel", cl::Hidden,
69 cl::desc("Enable the \"fast\" instruction selector"));
71 // Enable or disable an experimental optimization to split GEPs
72 // and run a special GVN pass which does not examine loads, in
73 // an effort to factor out redundancy implicit in complex GEPs.
74 static cl::opt<bool> EnableSplitGEPGVN("split-gep-gvn", cl::Hidden,
75 cl::desc("Split GEPs and run no-load GVN"));
77 LLVMTargetMachine::LLVMTargetMachine(const Target &T,
78 const std::string &TargetTriple)
80 AsmInfo = T.createAsmInfo(TargetTriple);
86 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
87 formatted_raw_ostream &Out,
88 CodeGenFileType FileType,
89 CodeGenOpt::Level OptLevel) {
90 // Add common CodeGen passes.
91 if (addCommonCodeGenPasses(PM, OptLevel))
92 return FileModel::Error;
97 case TargetMachine::AssemblyFile:
98 if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
99 return FileModel::Error;
100 return FileModel::AsmFile;
101 case TargetMachine::ObjectFile:
102 if (getMachOWriterInfo())
103 return FileModel::MachOFile;
104 else if (getELFWriterInfo())
105 return FileModel::ElfFile;
108 return FileModel::Error;
111 bool LLVMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
112 CodeGenOpt::Level OptLevel,
114 formatted_raw_ostream &Out) {
115 FunctionPass *Printer =
116 getTarget().createAsmPrinter(Out, *this, getMCAsmInfo(), Verbose);
124 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
125 /// be split up (e.g., to add an object writer pass), this method can be used to
126 /// finish up adding passes to emit the file, if necessary.
127 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
128 MachineCodeEmitter *MCE,
129 CodeGenOpt::Level OptLevel) {
131 addSimpleCodeEmitter(PM, OptLevel, *MCE);
133 addAssemblyEmitter(PM, OptLevel, true, ferrs());
135 PM.add(createGCInfoDeleter());
137 return false; // success!
140 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
141 /// be split up (e.g., to add an object writer pass), this method can be used to
142 /// finish up adding passes to emit the file, if necessary.
143 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
145 CodeGenOpt::Level OptLevel) {
147 addSimpleCodeEmitter(PM, OptLevel, *JCE);
149 addAssemblyEmitter(PM, OptLevel, true, ferrs());
151 PM.add(createGCInfoDeleter());
153 return false; // success!
156 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
157 /// be split up (e.g., to add an object writer pass), this method can be used to
158 /// finish up adding passes to emit the file, if necessary.
159 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
160 ObjectCodeEmitter *OCE,
161 CodeGenOpt::Level OptLevel) {
163 addSimpleCodeEmitter(PM, OptLevel, *OCE);
165 addAssemblyEmitter(PM, OptLevel, true, ferrs());
167 PM.add(createGCInfoDeleter());
169 return false; // success!
172 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
173 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
174 /// actually outputting the machine code and resolving things like the address
175 /// of functions. This method should returns true if machine code emission is
178 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
179 MachineCodeEmitter &MCE,
180 CodeGenOpt::Level OptLevel) {
181 // Add common CodeGen passes.
182 if (addCommonCodeGenPasses(PM, OptLevel))
185 addCodeEmitter(PM, OptLevel, MCE);
187 addAssemblyEmitter(PM, OptLevel, true, ferrs());
189 PM.add(createGCInfoDeleter());
191 return false; // success!
194 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
195 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
196 /// actually outputting the machine code and resolving things like the address
197 /// of functions. This method should returns true if machine code emission is
200 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
202 CodeGenOpt::Level OptLevel) {
203 // Add common CodeGen passes.
204 if (addCommonCodeGenPasses(PM, OptLevel))
207 addCodeEmitter(PM, OptLevel, JCE);
209 addAssemblyEmitter(PM, OptLevel, true, ferrs());
211 PM.add(createGCInfoDeleter());
213 return false; // success!
216 static void printAndVerify(PassManagerBase &PM,
218 bool allowDoubleDefs = false) {
219 if (PrintMachineCode)
220 PM.add(createMachineFunctionPrinterPass(errs(), Banner));
222 if (VerifyMachineCode)
223 PM.add(createMachineVerifierPass(allowDoubleDefs));
226 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
227 /// emitting to assembly files or machine code output.
229 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
230 CodeGenOpt::Level OptLevel) {
231 // Standard LLVM-Level Passes.
233 // Optionally, tun split-GEPs and no-load GVN.
234 if (EnableSplitGEPGVN) {
235 PM.add(createGEPSplitterPass());
236 PM.add(createGVNPass(/*NoPRE=*/false, /*NoLoads=*/true));
239 // Run loop strength reduction before anything else.
240 if (OptLevel != CodeGenOpt::None && !DisableLSR) {
241 PM.add(createLoopStrengthReducePass(getTargetLowering()));
243 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
246 // Turn exception handling constructs into something the code generators can
248 switch (getMCAsmInfo()->getExceptionHandlingType())
250 case ExceptionHandling::SjLj:
251 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
252 PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
253 PM.add(createSjLjEHPass(getTargetLowering()));
255 case ExceptionHandling::Dwarf:
256 PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
258 case ExceptionHandling::None:
259 PM.add(createLowerInvokePass(getTargetLowering()));
263 PM.add(createGCLoweringPass());
265 // Make sure that no unreachable blocks are instruction selected.
266 PM.add(createUnreachableBlockEliminationPass());
268 if (OptLevel != CodeGenOpt::None && !DisableCGP)
269 PM.add(createCodeGenPreparePass(getTargetLowering()));
271 PM.add(createStackProtectorPass(getTargetLowering()));
274 PM.add(createPrintFunctionPass("\n\n"
275 "*** Final LLVM Code input to ISel ***\n",
278 // Standard Lower-Level Passes.
280 // Set up a MachineFunction for the rest of CodeGen to work on.
281 PM.add(new MachineFunctionAnalysis(*this, OptLevel));
283 // Enable FastISel with -fast, but allow that to be overridden.
284 if (EnableFastISelOption == cl::BOU_TRUE ||
285 (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
286 EnableFastISel = true;
288 // Ask the target for an isel.
289 if (addInstSelector(PM, OptLevel))
292 // Print the instruction selected machine code...
293 printAndVerify(PM, "After Instruction Selection",
294 /* allowDoubleDefs= */ true);
296 if (OptLevel != CodeGenOpt::None) {
297 if (!DisableMachineLICM)
298 PM.add(createMachineLICMPass());
299 if (!DisableMachineSink)
300 PM.add(createMachineSinkingPass());
301 printAndVerify(PM, "After MachineLICM and MachineSinking",
302 /* allowDoubleDefs= */ true);
305 // Run pre-ra passes.
306 if (addPreRegAlloc(PM, OptLevel))
307 printAndVerify(PM, "After PreRegAlloc passes",
308 /* allowDoubleDefs= */ true);
310 // Perform register allocation.
311 PM.add(createRegisterAllocator());
312 printAndVerify(PM, "After Register Allocation");
314 // Perform stack slot coloring.
315 if (OptLevel != CodeGenOpt::None && !DisableSSC) {
316 // FIXME: Re-enable coloring with register when it's capable of adding
318 PM.add(createStackSlotColoringPass(false));
319 printAndVerify(PM, "After StackSlotColoring");
322 // Run post-ra passes.
323 if (addPostRegAlloc(PM, OptLevel))
324 printAndVerify(PM, "After PostRegAlloc passes");
326 PM.add(createLowerSubregsPass());
327 printAndVerify(PM, "After LowerSubregs");
329 // Insert prolog/epilog code. Eliminate abstract frame index references...
330 PM.add(createPrologEpilogCodeInserter());
331 printAndVerify(PM, "After PrologEpilogCodeInserter");
333 // Run pre-sched2 passes.
334 if (addPreSched2(PM, OptLevel))
335 printAndVerify(PM, "After PreSched2 passes");
337 // Second pass scheduler.
338 if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
339 PM.add(createPostRAScheduler(OptLevel));
340 printAndVerify(PM, "After PostRAScheduler");
343 // Branch folding must be run after regalloc and prolog/epilog insertion.
344 if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
345 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
346 printAndVerify(PM, "After BranchFolding");
350 if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
351 PM.add(createTailDuplicatePass());
352 printAndVerify(PM, "After TailDuplicate");
355 PM.add(createGCMachineCodeAnalysisPass());
358 PM.add(createGCInfoPrinter(errs()));
360 if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
361 PM.add(createCodePlacementOptPass());
362 printAndVerify(PM, "After CodePlacementOpt");
365 if (addPreEmitPass(PM, OptLevel))
366 printAndVerify(PM, "After PreEmit passes");