1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LLVMTargetMachine class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Pass.h"
17 #include "llvm/Assembly/PrintModulePass.h"
18 #include "llvm/Analysis/LoopPass.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/Collector.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Transforms/Scalar.h"
23 #include "llvm/Support/CommandLine.h"
26 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
27 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
28 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
29 cl::desc("Print LLVM IR input to isel pass"));
30 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
31 cl::desc("Dump emitter generated instructions as assembly"));
32 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
33 cl::desc("Dump garbage collector data"));
35 // Hidden options to help debugging
37 EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
38 cl::desc("Perform sinking on machine code"));
40 AlignLoops("align-loops", cl::init(true), cl::Hidden,
41 cl::desc("Align loop headers"));
43 PerformLICM("machine-licm",
44 cl::init(false), cl::Hidden,
45 cl::desc("Perform loop-invariant code motion on machine code"));
47 // When this works it will be on by default.
49 DisablePostRAScheduler("disable-post-RA-scheduler",
50 cl::desc("Disable scheduling after register allocation"),
54 LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
56 CodeGenFileType FileType,
58 // Standard LLVM-Level Passes.
60 // Run loop strength reduction before anything else.
62 PM.add(createLoopStrengthReducePass(getTargetLowering()));
64 PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
67 PM.add(createGCLoweringPass());
69 if (!ExceptionHandling)
70 PM.add(createLowerInvokePass(getTargetLowering()));
72 // Make sure that no unreachable blocks are instruction selected.
73 PM.add(createUnreachableBlockEliminationPass());
76 PM.add(createCodeGenPreparePass(getTargetLowering()));
79 PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel *** \n",
82 // Ask the target for an isel.
83 if (addInstSelector(PM, Fast))
84 return FileModel::Error;
86 // Print the instruction selected machine code...
88 PM.add(createMachineFunctionPrinterPass(cerr));
91 PM.add(createMachineLICMPass());
94 PM.add(createMachineSinkingPass());
96 // Perform register allocation to convert to a concrete x86 representation
97 PM.add(createRegisterAllocator());
100 PM.add(createMachineFunctionPrinterPass(cerr));
102 PM.add(createLowerSubregsPass());
104 if (PrintMachineCode) // Print the subreg lowered code
105 PM.add(createMachineFunctionPrinterPass(cerr));
107 // Run post-ra passes.
108 if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
109 PM.add(createMachineFunctionPrinterPass(cerr));
111 // Insert prolog/epilog code. Eliminate abstract frame index references...
112 PM.add(createPrologEpilogCodeInserter());
114 // Second pass scheduler.
115 if (!Fast && !DisablePostRAScheduler)
116 PM.add(createPostRAScheduler());
118 // Branch folding must be run after regalloc and prolog/epilog insertion.
120 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
122 PM.add(createGCMachineCodeAnalysisPass());
123 if (PrintMachineCode)
124 PM.add(createMachineFunctionPrinterPass(cerr));
127 PM.add(createCollectorMetadataPrinter(*cerr));
129 // Fold redundant debug labels.
130 PM.add(createDebugLabelFoldingPass());
132 if (PrintMachineCode) // Print the register-allocated code
133 PM.add(createMachineFunctionPrinterPass(cerr));
135 if (addPreEmitPass(PM, Fast) && PrintMachineCode)
136 PM.add(createMachineFunctionPrinterPass(cerr));
139 PM.add(createLoopAlignerPass());
144 case TargetMachine::AssemblyFile:
145 if (addAssemblyEmitter(PM, Fast, Out))
146 return FileModel::Error;
147 return FileModel::AsmFile;
148 case TargetMachine::ObjectFile:
149 if (getMachOWriterInfo())
150 return FileModel::MachOFile;
151 else if (getELFWriterInfo())
152 return FileModel::ElfFile;
155 return FileModel::Error;
158 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
159 /// be split up (e.g., to add an object writer pass), this method can be used to
160 /// finish up adding passes to emit the file, if necessary.
161 bool LLVMTargetMachine::addPassesToEmitFileFinish(FunctionPassManager &PM,
162 MachineCodeEmitter *MCE,
165 addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
167 PM.add(createCollectorMetadataDeleter());
169 // Delete machine code for this function
170 PM.add(createMachineCodeDeleter());
172 return false; // success!
175 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
176 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
177 /// actually outputting the machine code and resolving things like the address
178 /// of functions. This method should returns true if machine code emission is
181 bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
182 MachineCodeEmitter &MCE,
184 // Standard LLVM-Level Passes.
186 // Run loop strength reduction before anything else.
188 PM.add(createLoopStrengthReducePass(getTargetLowering()));
190 PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
193 PM.add(createGCLoweringPass());
195 if (!ExceptionHandling)
196 PM.add(createLowerInvokePass(getTargetLowering()));
198 // Make sure that no unreachable blocks are instruction selected.
199 PM.add(createUnreachableBlockEliminationPass());
202 PM.add(createCodeGenPreparePass(getTargetLowering()));
205 PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel *** \n",
208 // Ask the target for an isel.
209 if (addInstSelector(PM, Fast))
212 // Print the instruction selected machine code...
213 if (PrintMachineCode)
214 PM.add(createMachineFunctionPrinterPass(cerr));
217 PM.add(createMachineLICMPass());
220 PM.add(createMachineSinkingPass());
222 // Perform register allocation to convert to a concrete x86 representation
223 PM.add(createRegisterAllocator());
225 if (PrintMachineCode)
226 PM.add(createMachineFunctionPrinterPass(cerr));
228 PM.add(createLowerSubregsPass());
230 if (PrintMachineCode) // Print the subreg lowered code
231 PM.add(createMachineFunctionPrinterPass(cerr));
233 // Run post-ra passes.
234 if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
235 PM.add(createMachineFunctionPrinterPass(cerr));
237 // Insert prolog/epilog code. Eliminate abstract frame index references...
238 PM.add(createPrologEpilogCodeInserter());
240 if (PrintMachineCode) // Print the register-allocated code
241 PM.add(createMachineFunctionPrinterPass(cerr));
243 // Second pass scheduler.
245 PM.add(createPostRAScheduler());
247 // Branch folding must be run after regalloc and prolog/epilog insertion.
249 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
251 PM.add(createGCMachineCodeAnalysisPass());
252 if (PrintMachineCode)
253 PM.add(createMachineFunctionPrinterPass(cerr));
256 PM.add(createCollectorMetadataPrinter(*cerr));
258 if (addPreEmitPass(PM, Fast) && PrintMachineCode)
259 PM.add(createMachineFunctionPrinterPass(cerr));
261 addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
263 PM.add(createCollectorMetadataDeleter());
265 // Delete machine code for this function
266 PM.add(createMachineCodeDeleter());
268 return false; // success!