1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LLVMTargetMachine class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Analysis/Verifier.h"
17 #include "llvm/Assembly/PrintModulePass.h"
18 #include "llvm/CodeGen/AsmPrinter.h"
19 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
20 #include "llvm/CodeGen/MachineModuleInfo.h"
21 #include "llvm/CodeGen/GCStrategy.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/MC/MCAsmInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/Target/TargetAsmInfo.h"
28 #include "llvm/Target/TargetData.h"
29 #include "llvm/Target/TargetRegistry.h"
30 #include "llvm/Transforms/Scalar.h"
31 #include "llvm/ADT/OwningPtr.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/FormattedStream.h"
35 #include "llvm/Support/StandardPasses.h"
42 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
43 cl::desc("Disable Post Regalloc"));
44 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
45 cl::desc("Disable branch folding"));
46 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
47 cl::desc("Disable tail duplication"));
48 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
49 cl::desc("Disable pre-register allocation tail duplication"));
50 static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
51 cl::desc("Disable code placement"));
52 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
53 cl::desc("Disable Stack Slot Coloring"));
54 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
55 cl::desc("Disable Machine LICM"));
56 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
58 cl::desc("Disable Machine LICM"));
59 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
60 cl::desc("Disable Machine Sinking"));
61 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
62 cl::desc("Disable Loop Strength Reduction Pass"));
63 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
64 cl::desc("Disable Codegen Prepare"));
65 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
66 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
67 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
68 cl::desc("Print LLVM IR input to isel pass"));
69 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
70 cl::desc("Dump garbage collector data"));
71 static cl::opt<bool> ShowMCEncoding("show-mc-encoding", cl::Hidden,
72 cl::desc("Show encoding in .s output"));
73 static cl::opt<bool> ShowMCInst("show-mc-inst", cl::Hidden,
74 cl::desc("Show instruction structure in .s output"));
75 static cl::opt<bool> EnableMCLogging("enable-mc-api-logging", cl::Hidden,
76 cl::desc("Enable MC API logging"));
77 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
78 cl::desc("Verify generated machine code"),
79 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
81 static cl::opt<cl::boolOrDefault>
82 AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
83 cl::init(cl::BOU_UNSET));
85 static bool getVerboseAsm() {
88 case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
89 case cl::BOU_TRUE: return true;
90 case cl::BOU_FALSE: return false;
94 // Enable or disable FastISel. Both options are needed, because
95 // FastISel is enabled by default with -fast, and we wish to be
96 // able to enable or disable fast-isel independently from -O0.
97 static cl::opt<cl::boolOrDefault>
98 EnableFastISelOption("fast-isel", cl::Hidden,
99 cl::desc("Enable the \"fast\" instruction selector"));
101 LLVMTargetMachine::LLVMTargetMachine(const Target &T,
102 const std::string &Triple)
103 : TargetMachine(T), TargetTriple(Triple) {
104 AsmInfo = T.createAsmInfo(TargetTriple);
107 // Set the default code model for the JIT for a generic target.
108 // FIXME: Is small right here? or .is64Bit() ? Large : Small?
109 void LLVMTargetMachine::setCodeModelForJIT() {
110 setCodeModel(CodeModel::Small);
113 // Set the default code model for static compilation for a generic target.
114 void LLVMTargetMachine::setCodeModelForStatic() {
115 setCodeModel(CodeModel::Small);
118 bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
119 formatted_raw_ostream &Out,
120 CodeGenFileType FileType,
121 CodeGenOpt::Level OptLevel,
122 bool DisableVerify) {
123 // Add common CodeGen passes.
124 MCContext *Context = 0;
125 if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Context))
127 assert(Context != 0 && "Failed to get MCContext");
129 const MCAsmInfo &MAI = *getMCAsmInfo();
130 OwningPtr<MCStreamer> AsmStreamer;
133 default: return true;
134 case CGFT_AssemblyFile: {
135 MCInstPrinter *InstPrinter =
136 getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI);
138 // Create a code emitter if asked to show the encoding.
139 MCCodeEmitter *MCE = 0;
140 TargetAsmBackend *TAB = 0;
141 if (ShowMCEncoding) {
142 MCE = getTarget().createCodeEmitter(*this, *Context);
143 TAB = getTarget().createAsmBackend(TargetTriple);
146 MCStreamer *S = getTarget().createAsmStreamer(*Context, Out,
152 AsmStreamer.reset(S);
155 case CGFT_ObjectFile: {
156 // Create the code emitter for the target if it exists. If not, .o file
158 MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context);
159 TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);
160 if (MCE == 0 || TAB == 0)
163 AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Context,
166 hasMCNoExecStack()));
167 AsmStreamer.get()->InitSections();
171 // The Null output is intended for use for performance analysis and testing,
173 AsmStreamer.reset(createNullStreamer(*Context));
178 AsmStreamer.reset(createLoggingStreamer(AsmStreamer.take(), errs()));
180 // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
181 FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
185 // If successful, createAsmPrinter took ownership of AsmStreamer.
190 // Make sure the code model is set.
191 setCodeModelForStatic();
192 PM.add(createGCInfoDeleter());
196 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
197 /// get machine code emitted. This uses a JITCodeEmitter object to handle
198 /// actually outputting the machine code and resolving things like the address
199 /// of functions. This method should returns true if machine code emission is
202 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
204 CodeGenOpt::Level OptLevel,
205 bool DisableVerify) {
206 // Make sure the code model is set.
207 setCodeModelForJIT();
209 // Add common CodeGen passes.
211 if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
214 addCodeEmitter(PM, OptLevel, JCE);
215 PM.add(createGCInfoDeleter());
217 return false; // success!
220 /// addPassesToEmitMC - Add passes to the specified pass manager to get
221 /// machine code emitted with the MCJIT. This method returns true if machine
222 /// code is not supported. It fills the MCContext Ctx pointer which can be
223 /// used to build custom MCStreamer.
225 bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
227 CodeGenOpt::Level OptLevel,
228 bool DisableVerify) {
229 // Add common CodeGen passes.
230 if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
232 // Make sure the code model is set.
233 setCodeModelForJIT();
235 return false; // success!
238 static void printNoVerify(PassManagerBase &PM, const char *Banner) {
239 if (PrintMachineCode)
240 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
243 static void printAndVerify(PassManagerBase &PM,
244 const char *Banner) {
245 if (PrintMachineCode)
246 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
248 if (VerifyMachineCode)
249 PM.add(createMachineVerifierPass(Banner));
252 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
253 /// emitting to assembly files or machine code output.
255 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
256 CodeGenOpt::Level OptLevel,
258 MCContext *&OutContext) {
259 // Standard LLVM-Level Passes.
261 // Basic AliasAnalysis support.
262 createStandardAliasAnalysisPasses(&PM);
264 // Before running any passes, run the verifier to determine if the input
265 // coming from the front-end and/or optimizer is valid.
267 PM.add(createVerifierPass());
269 // Run loop strength reduction before anything else.
270 if (OptLevel != CodeGenOpt::None && !DisableLSR) {
271 PM.add(createLoopStrengthReducePass(getTargetLowering()));
273 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
276 PM.add(createGCLoweringPass());
278 // Make sure that no unreachable blocks are instruction selected.
279 PM.add(createUnreachableBlockEliminationPass());
281 // Turn exception handling constructs into something the code generators can
283 switch (getMCAsmInfo()->getExceptionHandlingType()) {
284 case ExceptionHandling::SjLj:
285 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
286 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
287 // catch info can get misplaced when a selector ends up more than one block
288 // removed from the parent invoke(s). This could happen when a landing
289 // pad is shared by multiple invokes and is also a target of a normal
290 // edge from elsewhere.
291 PM.add(createSjLjEHPass(getTargetLowering()));
293 case ExceptionHandling::DwarfCFI:
294 case ExceptionHandling::DwarfTable:
295 case ExceptionHandling::ARM:
296 PM.add(createDwarfEHPass(this));
298 case ExceptionHandling::None:
299 PM.add(createLowerInvokePass(getTargetLowering()));
301 // The lower invoke pass may create unreachable code. Remove it.
302 PM.add(createUnreachableBlockEliminationPass());
306 if (OptLevel != CodeGenOpt::None && !DisableCGP)
307 PM.add(createCodeGenPreparePass(getTargetLowering()));
309 PM.add(createStackProtectorPass(getTargetLowering()));
311 addPreISel(PM, OptLevel);
314 PM.add(createPrintFunctionPass("\n\n"
315 "*** Final LLVM Code input to ISel ***\n",
318 // All passes which modify the LLVM IR are now complete; run the verifier
319 // to ensure that the IR is valid.
321 PM.add(createVerifierPass());
323 // Standard Lower-Level Passes.
325 // Install a MachineModuleInfo class, which is an immutable pass that holds
326 // all the per-module stuff we're generating, including MCContext.
327 TargetAsmInfo *TAI = new TargetAsmInfo(*this);
328 MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo(), TAI);
330 OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
332 // Set up a MachineFunction for the rest of CodeGen to work on.
333 PM.add(new MachineFunctionAnalysis(*this, OptLevel));
335 // Enable FastISel with -fast, but allow that to be overridden.
336 if (EnableFastISelOption == cl::BOU_TRUE ||
337 (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
338 EnableFastISel = true;
340 // Ask the target for an isel.
341 if (addInstSelector(PM, OptLevel))
344 // Print the instruction selected machine code...
345 printAndVerify(PM, "After Instruction Selection");
347 // Expand pseudo-instructions emitted by ISel.
348 PM.add(createExpandISelPseudosPass());
350 // Optimize PHIs before DCE: removing dead PHI cycles may make more
351 // instructions dead.
352 if (OptLevel != CodeGenOpt::None)
353 PM.add(createOptimizePHIsPass());
355 // If the target requests it, assign local variables to stack slots relative
356 // to one another and simplify frame index references where possible.
357 PM.add(createLocalStackSlotAllocationPass());
359 if (OptLevel != CodeGenOpt::None) {
360 // With optimization, dead code should already be eliminated. However
361 // there is one known exception: lowered code for arguments that are only
362 // used by tail calls, where the tail calls reuse the incoming stack
363 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
364 PM.add(createDeadMachineInstructionElimPass());
365 printAndVerify(PM, "After codegen DCE pass");
367 if (!DisableMachineLICM)
368 PM.add(createMachineLICMPass());
369 PM.add(createMachineCSEPass());
370 if (!DisableMachineSink)
371 PM.add(createMachineSinkingPass());
372 printAndVerify(PM, "After Machine LICM, CSE and Sinking passes");
374 PM.add(createPeepholeOptimizerPass());
375 printAndVerify(PM, "After codegen peephole optimization pass");
378 // Pre-ra tail duplication.
379 if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
380 PM.add(createTailDuplicatePass(true));
381 printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
384 // Run pre-ra passes.
385 if (addPreRegAlloc(PM, OptLevel))
386 printAndVerify(PM, "After PreRegAlloc passes");
388 // Perform register allocation.
389 PM.add(createRegisterAllocator(OptLevel));
390 printAndVerify(PM, "After Register Allocation");
392 // Perform stack slot coloring and post-ra machine LICM.
393 if (OptLevel != CodeGenOpt::None) {
394 // FIXME: Re-enable coloring with register when it's capable of adding
397 PM.add(createStackSlotColoringPass(false));
399 // Run post-ra machine LICM to hoist reloads / remats.
400 if (!DisablePostRAMachineLICM)
401 PM.add(createMachineLICMPass(false));
403 printAndVerify(PM, "After StackSlotColoring and postra Machine LICM");
406 // Run post-ra passes.
407 if (addPostRegAlloc(PM, OptLevel))
408 printAndVerify(PM, "After PostRegAlloc passes");
410 PM.add(createLowerSubregsPass());
411 printAndVerify(PM, "After LowerSubregs");
413 // Insert prolog/epilog code. Eliminate abstract frame index references...
414 PM.add(createPrologEpilogCodeInserter());
415 printAndVerify(PM, "After PrologEpilogCodeInserter");
417 // Run pre-sched2 passes.
418 if (addPreSched2(PM, OptLevel))
419 printAndVerify(PM, "After PreSched2 passes");
421 // Second pass scheduler.
422 if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
423 PM.add(createPostRAScheduler(OptLevel));
424 printAndVerify(PM, "After PostRAScheduler");
427 // Branch folding must be run after regalloc and prolog/epilog insertion.
428 if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
429 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
430 printNoVerify(PM, "After BranchFolding");
434 if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
435 PM.add(createTailDuplicatePass(false));
436 printNoVerify(PM, "After TailDuplicate");
439 PM.add(createGCMachineCodeAnalysisPass());
442 PM.add(createGCInfoPrinter(dbgs()));
444 if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
445 PM.add(createCodePlacementOptPass());
446 printNoVerify(PM, "After CodePlacementOpt");
449 if (addPreEmitPass(PM, OptLevel))
450 printNoVerify(PM, "After PreEmit passes");