1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LLVMTargetMachine class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Analysis/Passes.h"
17 #include "llvm/Analysis/Verifier.h"
18 #include "llvm/Assembly/PrintModulePass.h"
19 #include "llvm/CodeGen/AsmPrinter.h"
20 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/GCStrategy.h"
23 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCInstrInfo.h"
28 #include "llvm/MC/MCStreamer.h"
29 #include "llvm/MC/MCSubtargetInfo.h"
30 #include "llvm/Target/TargetData.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetLowering.h"
33 #include "llvm/Target/TargetLoweringObjectFile.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Target/TargetSubtargetInfo.h"
36 #include "llvm/Transforms/Scalar.h"
37 #include "llvm/ADT/OwningPtr.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/FormattedStream.h"
41 #include "llvm/Support/TargetRegistry.h"
44 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
45 cl::desc("Disable Post Regalloc"));
46 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
47 cl::desc("Disable branch folding"));
48 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
49 cl::desc("Disable tail duplication"));
50 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
51 cl::desc("Disable pre-register allocation tail duplication"));
52 static cl::opt<bool> EnableBlockPlacement("enable-block-placement",
53 cl::Hidden, cl::desc("Enable probability-driven block placement"));
54 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
55 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
56 static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
57 cl::desc("Disable code placement"));
58 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
59 cl::desc("Disable Stack Slot Coloring"));
60 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
61 cl::desc("Disable Machine Dead Code Elimination"));
62 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
63 cl::desc("Disable Machine LICM"));
64 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
65 cl::desc("Disable Machine Common Subexpression Elimination"));
66 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
68 cl::desc("Disable Machine LICM"));
69 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
70 cl::desc("Disable Machine Sinking"));
71 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
72 cl::desc("Disable Loop Strength Reduction Pass"));
73 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
74 cl::desc("Disable Codegen Prepare"));
75 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
76 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
77 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
78 cl::desc("Print LLVM IR input to isel pass"));
79 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
80 cl::desc("Dump garbage collector data"));
81 static cl::opt<bool> ShowMCEncoding("show-mc-encoding", cl::Hidden,
82 cl::desc("Show encoding in .s output"));
83 static cl::opt<bool> ShowMCInst("show-mc-inst", cl::Hidden,
84 cl::desc("Show instruction structure in .s output"));
85 static cl::opt<bool> EnableMCLogging("enable-mc-api-logging", cl::Hidden,
86 cl::desc("Enable MC API logging"));
87 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
88 cl::desc("Verify generated machine code"),
89 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
91 static cl::opt<cl::boolOrDefault>
92 AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
93 cl::init(cl::BOU_UNSET));
95 static bool getVerboseAsm() {
98 case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
99 case cl::BOU_TRUE: return true;
100 case cl::BOU_FALSE: return false;
104 // Enable or disable FastISel. Both options are needed, because
105 // FastISel is enabled by default with -fast, and we wish to be
106 // able to enable or disable fast-isel independently from -O0.
107 static cl::opt<cl::boolOrDefault>
108 EnableFastISelOption("fast-isel", cl::Hidden,
109 cl::desc("Enable the \"fast\" instruction selector"));
111 LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
112 StringRef CPU, StringRef FS,
113 TargetOptions Options,
114 Reloc::Model RM, CodeModel::Model CM,
115 CodeGenOpt::Level OL)
116 : TargetMachine(T, Triple, CPU, FS, Options) {
117 CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
118 AsmInfo = T.createMCAsmInfo(Triple);
119 // TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0,
120 // and if the old one gets included then MCAsmInfo will be NULL and
121 // we'll crash later.
122 // Provide the user with a useful error message about what's wrong.
123 assert(AsmInfo && "MCAsmInfo not initialized."
124 "Make sure you include the correct TargetSelect.h"
125 "and that InitializeAllTargetMCs() is being invoked!");
128 bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
129 formatted_raw_ostream &Out,
130 CodeGenFileType FileType,
131 bool DisableVerify) {
132 // Add common CodeGen passes.
133 MCContext *Context = 0;
134 if (addCommonCodeGenPasses(PM, DisableVerify, Context))
136 assert(Context != 0 && "Failed to get MCContext");
138 if (hasMCSaveTempLabels())
139 Context->setAllowTemporaryLabels(false);
141 const MCAsmInfo &MAI = *getMCAsmInfo();
142 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
143 OwningPtr<MCStreamer> AsmStreamer;
146 default: return true;
147 case CGFT_AssemblyFile: {
148 MCInstPrinter *InstPrinter =
149 getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI, STI);
151 // Create a code emitter if asked to show the encoding.
152 MCCodeEmitter *MCE = 0;
153 MCAsmBackend *MAB = 0;
154 if (ShowMCEncoding) {
155 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
156 MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI, *Context);
157 MAB = getTarget().createMCAsmBackend(getTargetTriple());
160 MCStreamer *S = getTarget().createAsmStreamer(*Context, Out,
164 hasMCUseDwarfDirectory(),
168 AsmStreamer.reset(S);
171 case CGFT_ObjectFile: {
172 // Create the code emitter for the target if it exists. If not, .o file
174 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI,
176 MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple());
177 if (MCE == 0 || MAB == 0)
180 AsmStreamer.reset(getTarget().createMCObjectStreamer(getTargetTriple(),
182 MCE, hasMCRelaxAll(),
183 hasMCNoExecStack()));
184 AsmStreamer.get()->InitSections();
188 // The Null output is intended for use for performance analysis and testing,
190 AsmStreamer.reset(createNullStreamer(*Context));
195 AsmStreamer.reset(createLoggingStreamer(AsmStreamer.take(), errs()));
197 // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
198 FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
202 // If successful, createAsmPrinter took ownership of AsmStreamer.
207 PM.add(createGCInfoDeleter());
211 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
212 /// get machine code emitted. This uses a JITCodeEmitter object to handle
213 /// actually outputting the machine code and resolving things like the address
214 /// of functions. This method should returns true if machine code emission is
217 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
219 bool DisableVerify) {
220 // Add common CodeGen passes.
222 if (addCommonCodeGenPasses(PM, DisableVerify, Ctx))
225 addCodeEmitter(PM, JCE);
226 PM.add(createGCInfoDeleter());
228 return false; // success!
231 /// addPassesToEmitMC - Add passes to the specified pass manager to get
232 /// machine code emitted with the MCJIT. This method returns true if machine
233 /// code is not supported. It fills the MCContext Ctx pointer which can be
234 /// used to build custom MCStreamer.
236 bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
239 bool DisableVerify) {
240 // Add common CodeGen passes.
241 if (addCommonCodeGenPasses(PM, DisableVerify, Ctx))
244 if (hasMCSaveTempLabels())
245 Ctx->setAllowTemporaryLabels(false);
247 // Create the code emitter for the target if it exists. If not, .o file
249 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
250 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(),STI, *Ctx);
251 MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple());
252 if (MCE == 0 || MAB == 0)
255 OwningPtr<MCStreamer> AsmStreamer;
256 AsmStreamer.reset(getTarget().createMCObjectStreamer(getTargetTriple(), *Ctx,
259 hasMCNoExecStack()));
260 AsmStreamer.get()->InitSections();
262 // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
263 FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
267 // If successful, createAsmPrinter took ownership of AsmStreamer.
272 return false; // success!
275 void LLVMTargetMachine::printNoVerify(PassManagerBase &PM,
276 const char *Banner) const {
277 if (Options.PrintMachineCode)
278 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
281 void LLVMTargetMachine::printAndVerify(PassManagerBase &PM,
282 const char *Banner) const {
283 if (Options.PrintMachineCode)
284 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
286 if (VerifyMachineCode)
287 PM.add(createMachineVerifierPass(Banner));
290 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
291 /// emitting to assembly files or machine code output.
293 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
295 MCContext *&OutContext) {
296 // Standard LLVM-Level Passes.
298 // Basic AliasAnalysis support.
299 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
300 // BasicAliasAnalysis wins if they disagree. This is intended to help
301 // support "obvious" type-punning idioms.
302 PM.add(createTypeBasedAliasAnalysisPass());
303 PM.add(createBasicAliasAnalysisPass());
305 // Before running any passes, run the verifier to determine if the input
306 // coming from the front-end and/or optimizer is valid.
308 PM.add(createVerifierPass());
310 // Run loop strength reduction before anything else.
311 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
312 PM.add(createLoopStrengthReducePass(getTargetLowering()));
314 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
317 PM.add(createGCLoweringPass());
319 // Make sure that no unreachable blocks are instruction selected.
320 PM.add(createUnreachableBlockEliminationPass());
322 // Turn exception handling constructs into something the code generators can
324 switch (getMCAsmInfo()->getExceptionHandlingType()) {
325 case ExceptionHandling::SjLj:
326 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
327 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
328 // catch info can get misplaced when a selector ends up more than one block
329 // removed from the parent invoke(s). This could happen when a landing
330 // pad is shared by multiple invokes and is also a target of a normal
331 // edge from elsewhere.
332 PM.add(createSjLjEHPass(getTargetLowering()));
334 case ExceptionHandling::DwarfCFI:
335 case ExceptionHandling::ARM:
336 case ExceptionHandling::Win64:
337 PM.add(createDwarfEHPass(this));
339 case ExceptionHandling::None:
340 PM.add(createLowerInvokePass(getTargetLowering()));
342 // The lower invoke pass may create unreachable code. Remove it.
343 PM.add(createUnreachableBlockEliminationPass());
347 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
348 PM.add(createCodeGenPreparePass(getTargetLowering()));
350 PM.add(createStackProtectorPass(getTargetLowering()));
355 PM.add(createPrintFunctionPass("\n\n"
356 "*** Final LLVM Code input to ISel ***\n",
359 // All passes which modify the LLVM IR are now complete; run the verifier
360 // to ensure that the IR is valid.
362 PM.add(createVerifierPass());
364 // Standard Lower-Level Passes.
366 // Install a MachineModuleInfo class, which is an immutable pass that holds
367 // all the per-module stuff we're generating, including MCContext.
368 MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo(),
370 &getTargetLowering()->getObjFileLowering());
372 OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
374 // Set up a MachineFunction for the rest of CodeGen to work on.
375 PM.add(new MachineFunctionAnalysis(*this));
377 // Enable FastISel with -fast, but allow that to be overridden.
378 if (EnableFastISelOption == cl::BOU_TRUE ||
379 (getOptLevel() == CodeGenOpt::None &&
380 EnableFastISelOption != cl::BOU_FALSE))
381 Options.EnableFastISel = true;
383 // Ask the target for an isel.
384 if (addInstSelector(PM))
387 // Print the instruction selected machine code...
388 printAndVerify(PM, "After Instruction Selection");
390 // Expand pseudo-instructions emitted by ISel.
391 PM.add(createExpandISelPseudosPass());
393 // Pre-ra tail duplication.
394 if (getOptLevel() != CodeGenOpt::None && !DisableEarlyTailDup) {
395 PM.add(createTailDuplicatePass(true));
396 printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
399 // Optimize PHIs before DCE: removing dead PHI cycles may make more
400 // instructions dead.
401 if (getOptLevel() != CodeGenOpt::None)
402 PM.add(createOptimizePHIsPass());
404 // If the target requests it, assign local variables to stack slots relative
405 // to one another and simplify frame index references where possible.
406 PM.add(createLocalStackSlotAllocationPass());
408 if (getOptLevel() != CodeGenOpt::None) {
409 // With optimization, dead code should already be eliminated. However
410 // there is one known exception: lowered code for arguments that are only
411 // used by tail calls, where the tail calls reuse the incoming stack
412 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
413 if (!DisableMachineDCE)
414 PM.add(createDeadMachineInstructionElimPass());
415 printAndVerify(PM, "After codegen DCE pass");
417 if (!DisableMachineLICM)
418 PM.add(createMachineLICMPass());
419 if (!DisableMachineCSE)
420 PM.add(createMachineCSEPass());
421 if (!DisableMachineSink)
422 PM.add(createMachineSinkingPass());
423 printAndVerify(PM, "After Machine LICM, CSE and Sinking passes");
425 PM.add(createPeepholeOptimizerPass());
426 printAndVerify(PM, "After codegen peephole optimization pass");
429 // Run pre-ra passes.
430 if (addPreRegAlloc(PM))
431 printAndVerify(PM, "After PreRegAlloc passes");
433 // Perform register allocation.
434 PM.add(createRegisterAllocator(getOptLevel()));
435 printAndVerify(PM, "After Register Allocation");
437 // Perform stack slot coloring and post-ra machine LICM.
438 if (getOptLevel() != CodeGenOpt::None) {
439 // FIXME: Re-enable coloring with register when it's capable of adding
442 PM.add(createStackSlotColoringPass(false));
444 // Run post-ra machine LICM to hoist reloads / remats.
445 if (!DisablePostRAMachineLICM)
446 PM.add(createMachineLICMPass(false));
448 printAndVerify(PM, "After StackSlotColoring and postra Machine LICM");
451 // Run post-ra passes.
452 if (addPostRegAlloc(PM))
453 printAndVerify(PM, "After PostRegAlloc passes");
455 PM.add(createExpandPostRAPseudosPass());
456 printAndVerify(PM, "After ExpandPostRAPseudos");
458 // Insert prolog/epilog code. Eliminate abstract frame index references...
459 PM.add(createPrologEpilogCodeInserter());
460 printAndVerify(PM, "After PrologEpilogCodeInserter");
462 // Run pre-sched2 passes.
463 if (addPreSched2(PM))
464 printAndVerify(PM, "After PreSched2 passes");
466 // Second pass scheduler.
467 if (getOptLevel() != CodeGenOpt::None && !DisablePostRA) {
468 PM.add(createPostRAScheduler(getOptLevel()));
469 printAndVerify(PM, "After PostRAScheduler");
472 // Branch folding must be run after regalloc and prolog/epilog insertion.
473 if (getOptLevel() != CodeGenOpt::None && !DisableBranchFold) {
474 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
475 printNoVerify(PM, "After BranchFolding");
479 if (getOptLevel() != CodeGenOpt::None && !DisableTailDuplicate) {
480 PM.add(createTailDuplicatePass(false));
481 printNoVerify(PM, "After TailDuplicate");
484 PM.add(createGCMachineCodeAnalysisPass());
487 PM.add(createGCInfoPrinter(dbgs()));
489 if (getOptLevel() != CodeGenOpt::None && !DisableCodePlace) {
490 if (EnableBlockPlacement) {
491 // MachineBlockPlacement is an experimental pass which is disabled by
492 // default currently. Eventually it should subsume CodePlacementOpt, so
493 // when enabled, the other is disabled.
494 PM.add(createMachineBlockPlacementPass());
495 printNoVerify(PM, "After MachineBlockPlacement");
497 PM.add(createCodePlacementOptPass());
498 printNoVerify(PM, "After CodePlacementOpt");
501 // Run a separate pass to collect block placement statistics.
502 if (EnableBlockPlacementStats) {
503 PM.add(createMachineBlockPlacementStatsPass());
504 printNoVerify(PM, "After MachineBlockPlacementStats");
508 if (addPreEmitPass(PM))
509 printNoVerify(PM, "After PreEmit passes");