1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LLVMTargetMachine class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Pass.h"
17 #include "llvm/Assembly/PrintModulePass.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/CodeGen/GCStrategy.h"
20 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Target/TargetAsmInfo.h"
23 #include "llvm/Target/TargetRegistry.h"
24 #include "llvm/Transforms/Scalar.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/FormattedStream.h"
33 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
34 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
35 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
36 cl::desc("Print LLVM IR input to isel pass"));
37 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
38 cl::desc("Dump emitter generated instructions as assembly"));
39 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
40 cl::desc("Dump garbage collector data"));
41 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
42 cl::desc("Verify generated machine code"),
43 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
45 // When this works it will be on by default.
47 DisablePostRAScheduler("disable-post-RA-scheduler",
48 cl::desc("Disable scheduling after register allocation"),
51 // Enable or disable FastISel. Both options are needed, because
52 // FastISel is enabled by default with -fast, and we wish to be
53 // able to enable or disable fast-isel independently from -fast.
54 static cl::opt<cl::boolOrDefault>
55 EnableFastISelOption("fast-isel", cl::Hidden,
56 cl::desc("Enable the experimental \"fast\" instruction selector"));
59 LLVMTargetMachine::LLVMTargetMachine(const Target &T,
60 const std::string &TargetTriple)
62 AsmInfo = T.createAsmInfo(TargetTriple);
68 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
69 formatted_raw_ostream &Out,
70 CodeGenFileType FileType,
71 CodeGenOpt::Level OptLevel) {
72 // Add common CodeGen passes.
73 if (addCommonCodeGenPasses(PM, OptLevel))
74 return FileModel::Error;
76 // Fold redundant debug labels.
77 PM.add(createDebugLabelFoldingPass());
80 PM.add(createMachineFunctionPrinterPass(cerr));
82 if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
83 PM.add(createMachineFunctionPrinterPass(cerr));
85 if (OptLevel != CodeGenOpt::None)
86 PM.add(createCodePlacementOptPass());
91 case TargetMachine::AssemblyFile:
92 if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
93 return FileModel::Error;
94 return FileModel::AsmFile;
95 case TargetMachine::ObjectFile:
96 if (getMachOWriterInfo())
97 return FileModel::MachOFile;
98 else if (getELFWriterInfo())
99 return FileModel::ElfFile;
102 return FileModel::Error;
105 bool LLVMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
106 CodeGenOpt::Level OptLevel,
108 formatted_raw_ostream &Out) {
109 FunctionPass *Printer = getTarget().createAsmPrinter(Out, *this, Verbose);
117 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
118 /// be split up (e.g., to add an object writer pass), this method can be used to
119 /// finish up adding passes to emit the file, if necessary.
120 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
121 MachineCodeEmitter *MCE,
122 CodeGenOpt::Level OptLevel) {
124 addSimpleCodeEmitter(PM, OptLevel, *MCE);
126 addAssemblyEmitter(PM, OptLevel, true, ferrs());
128 PM.add(createGCInfoDeleter());
130 return false; // success!
133 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
134 /// be split up (e.g., to add an object writer pass), this method can be used to
135 /// finish up adding passes to emit the file, if necessary.
136 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
138 CodeGenOpt::Level OptLevel) {
140 addSimpleCodeEmitter(PM, OptLevel, *JCE);
142 addAssemblyEmitter(PM, OptLevel, true, ferrs());
144 PM.add(createGCInfoDeleter());
146 return false; // success!
149 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
150 /// be split up (e.g., to add an object writer pass), this method can be used to
151 /// finish up adding passes to emit the file, if necessary.
152 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
153 ObjectCodeEmitter *OCE,
154 CodeGenOpt::Level OptLevel) {
156 addSimpleCodeEmitter(PM, OptLevel, *OCE);
158 addAssemblyEmitter(PM, OptLevel, true, ferrs());
160 PM.add(createGCInfoDeleter());
162 return false; // success!
165 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
166 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
167 /// actually outputting the machine code and resolving things like the address
168 /// of functions. This method should returns true if machine code emission is
171 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
172 MachineCodeEmitter &MCE,
173 CodeGenOpt::Level OptLevel) {
174 // Add common CodeGen passes.
175 if (addCommonCodeGenPasses(PM, OptLevel))
178 if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
179 PM.add(createMachineFunctionPrinterPass(cerr));
181 addCodeEmitter(PM, OptLevel, MCE);
183 addAssemblyEmitter(PM, OptLevel, true, ferrs());
185 PM.add(createGCInfoDeleter());
187 return false; // success!
190 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
191 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
192 /// actually outputting the machine code and resolving things like the address
193 /// of functions. This method should returns true if machine code emission is
196 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
198 CodeGenOpt::Level OptLevel) {
199 // Add common CodeGen passes.
200 if (addCommonCodeGenPasses(PM, OptLevel))
203 if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
204 PM.add(createMachineFunctionPrinterPass(cerr));
206 addCodeEmitter(PM, OptLevel, JCE);
208 addAssemblyEmitter(PM, OptLevel, true, ferrs());
210 PM.add(createGCInfoDeleter());
212 return false; // success!
215 static void printAndVerify(PassManagerBase &PM,
216 bool allowDoubleDefs = false) {
217 if (PrintMachineCode)
218 PM.add(createMachineFunctionPrinterPass(cerr));
220 if (VerifyMachineCode)
221 PM.add(createMachineVerifierPass(allowDoubleDefs));
224 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
225 /// emitting to assembly files or machine code output.
227 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
228 CodeGenOpt::Level OptLevel) {
229 // Standard LLVM-Level Passes.
231 // Run loop strength reduction before anything else.
232 if (OptLevel != CodeGenOpt::None) {
233 PM.add(createLoopStrengthReducePass(getTargetLowering()));
235 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
238 // Turn exception handling constructs into something the code generators can
240 switch (getTargetAsmInfo()->getExceptionHandlingType())
242 // SjLj piggy-backs on dwarf for this bit
243 case ExceptionHandling::SjLj:
244 case ExceptionHandling::Dwarf:
245 PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
247 case ExceptionHandling::None:
248 PM.add(createLowerInvokePass(getTargetLowering()));
252 PM.add(createGCLoweringPass());
254 // Make sure that no unreachable blocks are instruction selected.
255 PM.add(createUnreachableBlockEliminationPass());
257 if (OptLevel != CodeGenOpt::None)
258 PM.add(createCodeGenPreparePass(getTargetLowering()));
260 PM.add(createStackProtectorPass(getTargetLowering()));
263 PM.add(createPrintFunctionPass("\n\n"
264 "*** Final LLVM Code input to ISel ***\n",
267 // Standard Lower-Level Passes.
269 // Set up a MachineFunction for the rest of CodeGen to work on.
270 PM.add(new MachineFunctionAnalysis(*this, OptLevel));
272 // Enable FastISel with -fast, but allow that to be overridden.
273 if (EnableFastISelOption == cl::BOU_TRUE ||
274 (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
275 EnableFastISel = true;
277 // Ask the target for an isel.
278 if (addInstSelector(PM, OptLevel))
281 // Print the instruction selected machine code...
282 printAndVerify(PM, /* allowDoubleDefs= */ true);
284 if (OptLevel != CodeGenOpt::None) {
285 PM.add(createMachineLICMPass());
286 PM.add(createMachineSinkingPass());
287 printAndVerify(PM, /* allowDoubleDefs= */ true);
290 // Run pre-ra passes.
291 if (addPreRegAlloc(PM, OptLevel))
294 // Perform register allocation.
295 PM.add(createRegisterAllocator());
297 // Perform stack slot coloring.
298 if (OptLevel != CodeGenOpt::None)
299 // FIXME: Re-enable coloring with register when it's capable of adding
301 PM.add(createStackSlotColoringPass(false));
303 printAndVerify(PM); // Print the register-allocated code
305 // Run post-ra passes.
306 if (addPostRegAlloc(PM, OptLevel))
309 PM.add(createLowerSubregsPass());
312 // Insert prolog/epilog code. Eliminate abstract frame index references...
313 PM.add(createPrologEpilogCodeInserter());
316 // Second pass scheduler.
317 if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
318 PM.add(createPostRAScheduler());
322 // Branch folding must be run after regalloc and prolog/epilog insertion.
323 if (OptLevel != CodeGenOpt::None) {
324 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
328 PM.add(createGCMachineCodeAnalysisPass());
332 PM.add(createGCInfoPrinter(*cerr));