1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LLVMTargetMachine class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Pass.h"
17 #include "llvm/Assembly/PrintModulePass.h"
18 #include "llvm/CodeGen/AsmPrinter.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/FileWriters.h"
21 #include "llvm/CodeGen/GCStrategy.h"
22 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/MC/MCAsmInfo.h"
25 #include "llvm/Target/TargetRegistry.h"
26 #include "llvm/Transforms/Scalar.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/FormattedStream.h"
36 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
37 cl::desc("Disable Post Regalloc"));
38 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
39 cl::desc("Disable branch folding"));
40 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
41 cl::desc("Disable tail duplication"));
42 static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
43 cl::desc("Disable code placement"));
44 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
45 cl::desc("Disable Stack Slot Coloring"));
46 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
47 cl::desc("Disable Machine LICM"));
48 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
49 cl::desc("Disable Machine Sinking"));
50 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
51 cl::desc("Disable Loop Strength Reduction Pass"));
52 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
53 cl::desc("Disable Codegen Prepare"));
54 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
55 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
56 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
57 cl::desc("Print LLVM IR input to isel pass"));
58 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
59 cl::desc("Dump emitter generated instructions as assembly"));
60 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
61 cl::desc("Dump garbage collector data"));
62 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
63 cl::desc("Verify generated machine code"),
64 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
67 // Enable or disable FastISel. Both options are needed, because
68 // FastISel is enabled by default with -fast, and we wish to be
69 // able to enable or disable fast-isel independently from -O0.
70 static cl::opt<cl::boolOrDefault>
71 EnableFastISelOption("fast-isel", cl::Hidden,
72 cl::desc("Enable the \"fast\" instruction selector"));
74 // Enable or disable an experimental optimization to split GEPs
75 // and run a special GVN pass which does not examine loads, in
76 // an effort to factor out redundancy implicit in complex GEPs.
77 static cl::opt<bool> EnableSplitGEPGVN("split-gep-gvn", cl::Hidden,
78 cl::desc("Split GEPs and run no-load GVN"));
80 static cl::opt<bool> PreAllocTailDup("pre-regalloc-taildup", cl::Hidden,
81 cl::desc("Pre-register allocation tail duplication"));
83 LLVMTargetMachine::LLVMTargetMachine(const Target &T,
84 const std::string &TargetTriple)
86 AsmInfo = T.createAsmInfo(TargetTriple);
89 // Set the default code model for the JIT for a generic target.
90 // FIXME: Is small right here? or .is64Bit() ? Large : Small?
92 LLVMTargetMachine::setCodeModelForJIT() {
93 setCodeModel(CodeModel::Small);
96 // Set the default code model for static compilation for a generic target.
98 LLVMTargetMachine::setCodeModelForStatic() {
99 setCodeModel(CodeModel::Small);
103 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
104 formatted_raw_ostream &Out,
105 CodeGenFileType FileType,
106 CodeGenOpt::Level OptLevel) {
107 // Add common CodeGen passes.
108 if (addCommonCodeGenPasses(PM, OptLevel))
109 return FileModel::Error;
114 case TargetMachine::AssemblyFile:
115 if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
116 return FileModel::Error;
117 return FileModel::AsmFile;
118 case TargetMachine::ObjectFile:
119 if (!addObjectFileEmitter(PM, OptLevel, Out))
120 return FileModel::MachOFile;
121 else if (getELFWriterInfo())
122 return FileModel::ElfFile;
124 return FileModel::Error;
127 bool LLVMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
128 CodeGenOpt::Level OptLevel,
130 formatted_raw_ostream &Out) {
131 FunctionPass *Printer =
132 getTarget().createAsmPrinter(Out, *this, getMCAsmInfo(), Verbose);
140 bool LLVMTargetMachine::addObjectFileEmitter(PassManagerBase &PM,
141 CodeGenOpt::Level OptLevel,
142 formatted_raw_ostream &Out) {
143 MCCodeEmitter *Emitter = getTarget().createCodeEmitter(*this);
147 PM.add(createMachOWriter(Out, *this, getMCAsmInfo(), Emitter));
151 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
152 /// be split up (e.g., to add an object writer pass), this method can be used to
153 /// finish up adding passes to emit the file, if necessary.
154 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
155 MachineCodeEmitter *MCE,
156 CodeGenOpt::Level OptLevel) {
157 // Make sure the code model is set.
158 setCodeModelForStatic();
161 addSimpleCodeEmitter(PM, OptLevel, *MCE);
163 addAssemblyEmitter(PM, OptLevel, true, ferrs());
165 PM.add(createGCInfoDeleter());
167 return false; // success!
170 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
171 /// be split up (e.g., to add an object writer pass), this method can be used to
172 /// finish up adding passes to emit the file, if necessary.
173 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
175 CodeGenOpt::Level OptLevel) {
176 // Make sure the code model is set.
177 setCodeModelForJIT();
180 addSimpleCodeEmitter(PM, OptLevel, *JCE);
182 addAssemblyEmitter(PM, OptLevel, true, ferrs());
184 PM.add(createGCInfoDeleter());
186 return false; // success!
189 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
190 /// be split up (e.g., to add an object writer pass), this method can be used to
191 /// finish up adding passes to emit the file, if necessary.
192 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
193 ObjectCodeEmitter *OCE,
194 CodeGenOpt::Level OptLevel) {
195 // Make sure the code model is set.
196 setCodeModelForStatic();
199 addSimpleCodeEmitter(PM, OptLevel, *OCE);
201 addAssemblyEmitter(PM, OptLevel, true, ferrs());
203 PM.add(createGCInfoDeleter());
205 return false; // success!
208 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
209 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
210 /// actually outputting the machine code and resolving things like the address
211 /// of functions. This method should returns true if machine code emission is
214 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
215 MachineCodeEmitter &MCE,
216 CodeGenOpt::Level OptLevel) {
217 // Make sure the code model is set.
218 setCodeModelForJIT();
220 // Add common CodeGen passes.
221 if (addCommonCodeGenPasses(PM, OptLevel))
224 addCodeEmitter(PM, OptLevel, MCE);
226 addAssemblyEmitter(PM, OptLevel, true, ferrs());
228 PM.add(createGCInfoDeleter());
230 return false; // success!
233 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
234 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
235 /// actually outputting the machine code and resolving things like the address
236 /// of functions. This method should returns true if machine code emission is
239 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
241 CodeGenOpt::Level OptLevel) {
242 // Make sure the code model is set.
243 setCodeModelForJIT();
245 // Add common CodeGen passes.
246 if (addCommonCodeGenPasses(PM, OptLevel))
249 addCodeEmitter(PM, OptLevel, JCE);
251 addAssemblyEmitter(PM, OptLevel, true, ferrs());
253 PM.add(createGCInfoDeleter());
255 return false; // success!
258 static void printAndVerify(PassManagerBase &PM,
260 bool allowDoubleDefs = false) {
261 if (PrintMachineCode)
262 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
264 if (VerifyMachineCode)
265 PM.add(createMachineVerifierPass(allowDoubleDefs));
268 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
269 /// emitting to assembly files or machine code output.
271 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
272 CodeGenOpt::Level OptLevel) {
273 // Standard LLVM-Level Passes.
275 // Optionally, tun split-GEPs and no-load GVN.
276 if (EnableSplitGEPGVN) {
277 PM.add(createGEPSplitterPass());
278 PM.add(createGVNPass(/*NoPRE=*/false, /*NoLoads=*/true));
281 // Run loop strength reduction before anything else.
282 if (OptLevel != CodeGenOpt::None && !DisableLSR) {
283 PM.add(createLoopStrengthReducePass(getTargetLowering()));
285 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
288 // Turn exception handling constructs into something the code generators can
290 switch (getMCAsmInfo()->getExceptionHandlingType())
292 case ExceptionHandling::SjLj:
293 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
294 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
295 // catch info can get misplaced when a selector ends up more than one block
296 // removed from the parent invoke(s). This could happen when a landing
297 // pad is shared by multiple invokes and is also a target of a normal
298 // edge from elsewhere.
299 PM.add(createSjLjEHPass(getTargetLowering()));
300 PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
302 case ExceptionHandling::Dwarf:
303 PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
305 case ExceptionHandling::None:
306 PM.add(createLowerInvokePass(getTargetLowering()));
310 PM.add(createGCLoweringPass());
312 // Make sure that no unreachable blocks are instruction selected.
313 PM.add(createUnreachableBlockEliminationPass());
315 if (OptLevel != CodeGenOpt::None && !DisableCGP)
316 PM.add(createCodeGenPreparePass(getTargetLowering()));
318 PM.add(createStackProtectorPass(getTargetLowering()));
321 PM.add(createPrintFunctionPass("\n\n"
322 "*** Final LLVM Code input to ISel ***\n",
325 // Standard Lower-Level Passes.
327 // Set up a MachineFunction for the rest of CodeGen to work on.
328 PM.add(new MachineFunctionAnalysis(*this, OptLevel));
330 // Enable FastISel with -fast, but allow that to be overridden.
331 if (EnableFastISelOption == cl::BOU_TRUE ||
332 (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
333 EnableFastISel = true;
335 // Ask the target for an isel.
336 if (addInstSelector(PM, OptLevel))
339 // Print the instruction selected machine code...
340 printAndVerify(PM, "After Instruction Selection",
341 /* allowDoubleDefs= */ true);
343 if (OptLevel != CodeGenOpt::None) {
344 PM.add(createOptimizeExtsPass());
345 if (!DisableMachineLICM)
346 PM.add(createMachineLICMPass());
347 if (!DisableMachineSink)
348 PM.add(createMachineSinkingPass());
349 printAndVerify(PM, "After MachineLICM and MachineSinking",
350 /* allowDoubleDefs= */ true);
353 // Pre-ra tail duplication.
354 if (OptLevel != CodeGenOpt::None &&
355 !DisableTailDuplicate && PreAllocTailDup) {
356 PM.add(createTailDuplicatePass(true));
357 printAndVerify(PM, "After Pre-RegAlloc TailDuplicate",
358 /* allowDoubleDefs= */ true);
361 // Run pre-ra passes.
362 if (addPreRegAlloc(PM, OptLevel))
363 printAndVerify(PM, "After PreRegAlloc passes",
364 /* allowDoubleDefs= */ true);
366 // Perform register allocation.
367 PM.add(createRegisterAllocator());
368 printAndVerify(PM, "After Register Allocation");
370 // Perform stack slot coloring.
371 if (OptLevel != CodeGenOpt::None && !DisableSSC) {
372 // FIXME: Re-enable coloring with register when it's capable of adding
374 PM.add(createStackSlotColoringPass(false));
375 printAndVerify(PM, "After StackSlotColoring");
378 // Run post-ra passes.
379 if (addPostRegAlloc(PM, OptLevel))
380 printAndVerify(PM, "After PostRegAlloc passes");
382 PM.add(createLowerSubregsPass());
383 printAndVerify(PM, "After LowerSubregs");
385 // Insert prolog/epilog code. Eliminate abstract frame index references...
386 PM.add(createPrologEpilogCodeInserter());
387 printAndVerify(PM, "After PrologEpilogCodeInserter");
389 // Run pre-sched2 passes.
390 if (addPreSched2(PM, OptLevel))
391 printAndVerify(PM, "After PreSched2 passes");
393 // Second pass scheduler.
394 if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
395 PM.add(createPostRAScheduler(OptLevel));
396 printAndVerify(PM, "After PostRAScheduler");
399 // Branch folding must be run after regalloc and prolog/epilog insertion.
400 if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
401 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
402 printAndVerify(PM, "After BranchFolding");
406 if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
407 PM.add(createTailDuplicatePass(false));
408 printAndVerify(PM, "After TailDuplicate");
411 PM.add(createGCMachineCodeAnalysisPass());
414 PM.add(createGCInfoPrinter(dbgs()));
416 if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
417 PM.add(createCodePlacementOptPass());
418 printAndVerify(PM, "After CodePlacementOpt");
421 if (addPreEmitPass(PM, OptLevel))
422 printAndVerify(PM, "After PreEmit passes");