lib/CodeGen/LLVMTargetMachine.cpp

   1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the LLVMTargetMachine class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/Target/TargetMachine.h"
  15 #include "llvm/PassManager.h"
  16 #include "llvm/Pass.h"
  17 #include "llvm/Assembly/PrintModulePass.h"
  18 #include "llvm/Analysis/LoopPass.h"
  19 #include "llvm/CodeGen/Passes.h"
  20 #include "llvm/CodeGen/GCStrategy.h"
  21 #include "llvm/Target/TargetOptions.h"
  22 #include "llvm/Target/TargetAsmInfo.h"
  23 #include "llvm/Transforms/Scalar.h"
  24 #include "llvm/Support/CommandLine.h"
  25 #include "llvm/Support/raw_ostream.h"
  26 using namespace llvm;
  27
  28 namespace llvm {
  29   bool EnableFastISel;
  30 }
  31
  32 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
  33     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
  34 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
  35     cl::desc("Print LLVM IR input to isel pass"));
  36 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
  37     cl::desc("Dump emitter generated instructions as assembly"));
  38 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
  39     cl::desc("Dump garbage collector data"));
  40
  41 // Hidden options to help debugging
  42 static cl::opt<bool>
  43 EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
  44               cl::desc("Perform sinking on machine code"));
  45
  46 // When this works it will be on by default.
  47 static cl::opt<bool>
  48 DisablePostRAScheduler("disable-post-RA-scheduler",
  49                        cl::desc("Disable scheduling after register allocation"),
  50                        cl::init(true));
  51
  52 // Enable or disable FastISel. Both options are needed, because
  53 // FastISel is enabled by default with -fast, and we wish to be
  54 // able to enable or disable fast-isel independently from -fast.
  55 static cl::opt<cl::boolOrDefault>
  56 EnableFastISelOption("fast-isel", cl::Hidden,
  57   cl::desc("Enable the experimental \"fast\" instruction selector"));
  58
  59 FileModel::Model
  60 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
  61                                        raw_ostream &Out,
  62                                        CodeGenFileType FileType,
  63                                        bool Fast) {
  64   // Add common CodeGen passes.
  65   if (addCommonCodeGenPasses(PM, Fast))
  66     return FileModel::Error;
  67
  68   // Fold redundant debug labels.
  69   PM.add(createDebugLabelFoldingPass());
  70
  71   if (PrintMachineCode)
  72     PM.add(createMachineFunctionPrinterPass(cerr));
  73
  74   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
  75     PM.add(createMachineFunctionPrinterPass(cerr));
  76
  77   if (!Fast)
  78     PM.add(createLoopAlignerPass());
  79
  80   switch (FileType) {
  81   default:
  82     break;
  83   case TargetMachine::AssemblyFile:
  84     if (addAssemblyEmitter(PM, Fast, Out))
  85       return FileModel::Error;
  86     return FileModel::AsmFile;
  87   case TargetMachine::ObjectFile:
  88     if (getMachOWriterInfo())
  89       return FileModel::MachOFile;
  90     else if (getELFWriterInfo())
  91       return FileModel::ElfFile;
  92   }
  93
  94   return FileModel::Error;
  95 }
  96
  97 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
  98 /// be split up (e.g., to add an object writer pass), this method can be used to
  99 /// finish up adding passes to emit the file, if necessary.
 100 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
 101                                                   MachineCodeEmitter *MCE,
 102                                                   bool Fast) {
 103   if (MCE)
 104     addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
 105
 106   PM.add(createGCInfoDeleter());
 107
 108   // Delete machine code for this function
 109   PM.add(createMachineCodeDeleter());
 110
 111   return false; // success!
 112 }
 113
 114 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
 115 /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
 116 /// actually outputting the machine code and resolving things like the address
 117 /// of functions.  This method should returns true if machine code emission is
 118 /// not supported.
 119 ///
 120 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
 121                                                    MachineCodeEmitter &MCE,
 122                                                    bool Fast) {
 123   // Add common CodeGen passes.
 124   if (addCommonCodeGenPasses(PM, Fast))
 125     return true;
 126
 127   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
 128     PM.add(createMachineFunctionPrinterPass(cerr));
 129
 130   addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
 131
 132   PM.add(createGCInfoDeleter());
 133
 134   // Delete machine code for this function
 135   PM.add(createMachineCodeDeleter());
 136
 137   return false; // success!
 138 }
 139
 140 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
 141 /// both emitting to assembly files or machine code output.
 142 ///
 143 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
 144   // Standard LLVM-Level Passes.
 145
 146   // Run loop strength reduction before anything else.
 147   if (!Fast) {
 148     PM.add(createLoopStrengthReducePass(getTargetLowering()));
 149     if (PrintLSR)
 150       PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
 151   }
 152
 153   PM.add(createGCLoweringPass());
 154
 155   if (!getTargetAsmInfo()->doesSupportExceptionHandling())
 156     PM.add(createLowerInvokePass(getTargetLowering()));
 157
 158   // Make sure that no unreachable blocks are instruction selected.
 159   PM.add(createUnreachableBlockEliminationPass());
 160
 161   if (!Fast)
 162     PM.add(createCodeGenPreparePass(getTargetLowering()));
 163
 164   PM.add(createStackProtectorPass(getTargetLowering()));
 165
 166   if (PrintISelInput)
 167     PM.add(createPrintFunctionPass("\n\n"
 168                                    "*** Final LLVM Code input to ISel ***\n",
 169                                    &errs()));
 170
 171   // Standard Lower-Level Passes.
 172
 173   // Enable FastISel with -fast, but allow that to be overridden.
 174   if (EnableFastISelOption == cl::BOU_TRUE ||
 175       (Fast && EnableFastISelOption != cl::BOU_FALSE))
 176     EnableFastISel = true;
 177
 178   // Ask the target for an isel.
 179   if (addInstSelector(PM, Fast))
 180     return true;
 181
 182   // Print the instruction selected machine code...
 183   if (PrintMachineCode)
 184     PM.add(createMachineFunctionPrinterPass(cerr));
 185
 186   if (!Fast)
 187     PM.add(createMachineLICMPass());
 188
 189   if (EnableSinking)
 190     PM.add(createMachineSinkingPass());
 191
 192   // Run pre-ra passes.
 193   if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
 194     PM.add(createMachineFunctionPrinterPass(cerr));
 195
 196   // Perform register allocation.
 197   PM.add(createRegisterAllocator());
 198
 199   // Perform stack slot coloring.
 200   if (!Fast)
 201     PM.add(createStackSlotColoringPass());
 202
 203   if (PrintMachineCode)  // Print the register-allocated code
 204     PM.add(createMachineFunctionPrinterPass(cerr));
 205
 206   // Run post-ra passes.
 207   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
 208     PM.add(createMachineFunctionPrinterPass(cerr));
 209
 210   if (PrintMachineCode)
 211     PM.add(createMachineFunctionPrinterPass(cerr));
 212
 213   PM.add(createLowerSubregsPass());
 214
 215   if (PrintMachineCode)  // Print the subreg lowered code
 216     PM.add(createMachineFunctionPrinterPass(cerr));
 217
 218   // Insert prolog/epilog code.  Eliminate abstract frame index references...
 219   PM.add(createPrologEpilogCodeInserter());
 220
 221   if (PrintMachineCode)
 222     PM.add(createMachineFunctionPrinterPass(cerr));
 223
 224   // Second pass scheduler.
 225   if (!Fast && !DisablePostRAScheduler) {
 226     PM.add(createPostRAScheduler());
 227
 228     if (PrintMachineCode)
 229       PM.add(createMachineFunctionPrinterPass(cerr));
 230   }
 231
 232   // Branch folding must be run after regalloc and prolog/epilog insertion.
 233   if (!Fast)
 234     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 235
 236   if (PrintMachineCode)
 237     PM.add(createMachineFunctionPrinterPass(cerr));
 238
 239   PM.add(createGCMachineCodeAnalysisPass());
 240
 241   if (PrintMachineCode)
 242     PM.add(createMachineFunctionPrinterPass(cerr));
 243
 244   if (PrintGCInfo)
 245     PM.add(createGCInfoPrinter(*cerr));
 246
 247   return false;
 248 }