1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LLVMTargetMachine class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Analysis/Verifier.h"
17 #include "llvm/Assembly/PrintModulePass.h"
18 #include "llvm/CodeGen/AsmPrinter.h"
19 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
20 #include "llvm/CodeGen/MachineModuleInfo.h"
21 #include "llvm/CodeGen/GCStrategy.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/MC/MCAsmInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/Target/TargetAsmInfo.h"
28 #include "llvm/Target/TargetData.h"
29 #include "llvm/Target/TargetRegistry.h"
30 #include "llvm/Transforms/Scalar.h"
31 #include "llvm/ADT/OwningPtr.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/FormattedStream.h"
35 #include "llvm/Support/StandardPasses.h"
42 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
43 cl::desc("Disable Post Regalloc"));
44 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
45 cl::desc("Disable branch folding"));
46 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
47 cl::desc("Disable tail duplication"));
48 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
49 cl::desc("Disable pre-register allocation tail duplication"));
50 static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
51 cl::desc("Disable code placement"));
52 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
53 cl::desc("Disable Stack Slot Coloring"));
54 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
55 cl::desc("Disable Machine LICM"));
56 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
58 cl::desc("Disable Machine LICM"));
59 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
60 cl::desc("Disable Machine Sinking"));
61 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
62 cl::desc("Disable Loop Strength Reduction Pass"));
63 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
64 cl::desc("Disable Codegen Prepare"));
65 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
66 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
67 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
68 cl::desc("Print LLVM IR input to isel pass"));
69 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
70 cl::desc("Dump garbage collector data"));
71 static cl::opt<bool> ShowMCEncoding("show-mc-encoding", cl::Hidden,
72 cl::desc("Show encoding in .s output"));
73 static cl::opt<bool> ShowMCInst("show-mc-inst", cl::Hidden,
74 cl::desc("Show instruction structure in .s output"));
75 static cl::opt<bool> EnableMCLogging("enable-mc-api-logging", cl::Hidden,
76 cl::desc("Enable MC API logging"));
77 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
78 cl::desc("Verify generated machine code"),
79 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
81 static cl::opt<cl::boolOrDefault>
82 AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
83 cl::init(cl::BOU_UNSET));
85 static bool getVerboseAsm() {
88 case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
89 case cl::BOU_TRUE: return true;
90 case cl::BOU_FALSE: return false;
94 // Enable or disable FastISel. Both options are needed, because
95 // FastISel is enabled by default with -fast, and we wish to be
96 // able to enable or disable fast-isel independently from -O0.
97 static cl::opt<cl::boolOrDefault>
98 EnableFastISelOption("fast-isel", cl::Hidden,
99 cl::desc("Enable the \"fast\" instruction selector"));
101 // Enable or disable an experimental optimization to split GEPs
102 // and run a special GVN pass which does not examine loads, in
103 // an effort to factor out redundancy implicit in complex GEPs.
104 static cl::opt<bool> EnableSplitGEPGVN("split-gep-gvn", cl::Hidden,
105 cl::desc("Split GEPs and run no-load GVN"));
107 LLVMTargetMachine::LLVMTargetMachine(const Target &T,
108 const std::string &Triple)
109 : TargetMachine(T), TargetTriple(Triple) {
110 AsmInfo = T.createAsmInfo(TargetTriple);
113 // Set the default code model for the JIT for a generic target.
114 // FIXME: Is small right here? or .is64Bit() ? Large : Small?
115 void LLVMTargetMachine::setCodeModelForJIT() {
116 setCodeModel(CodeModel::Small);
119 // Set the default code model for static compilation for a generic target.
120 void LLVMTargetMachine::setCodeModelForStatic() {
121 setCodeModel(CodeModel::Small);
124 bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
125 formatted_raw_ostream &Out,
126 CodeGenFileType FileType,
127 CodeGenOpt::Level OptLevel,
128 bool DisableVerify) {
129 // Add common CodeGen passes.
130 MCContext *Context = 0;
131 if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Context))
133 assert(Context != 0 && "Failed to get MCContext");
135 const MCAsmInfo &MAI = *getMCAsmInfo();
136 OwningPtr<MCStreamer> AsmStreamer;
139 default: return true;
140 case CGFT_AssemblyFile: {
141 MCInstPrinter *InstPrinter =
142 getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI);
144 // Create a code emitter if asked to show the encoding.
145 MCCodeEmitter *MCE = 0;
146 TargetAsmBackend *TAB = 0;
147 if (ShowMCEncoding) {
148 MCE = getTarget().createCodeEmitter(*this, *Context);
149 TAB = getTarget().createAsmBackend(TargetTriple);
152 MCStreamer *S = getTarget().createAsmStreamer(*Context, Out,
158 AsmStreamer.reset(S);
161 case CGFT_ObjectFile: {
162 // Create the code emitter for the target if it exists. If not, .o file
164 MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context);
165 TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);
166 if (MCE == 0 || TAB == 0)
169 AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Context,
172 hasMCNoExecStack()));
173 AsmStreamer.get()->InitSections();
177 // The Null output is intended for use for performance analysis and testing,
179 AsmStreamer.reset(createNullStreamer(*Context));
184 AsmStreamer.reset(createLoggingStreamer(AsmStreamer.take(), errs()));
186 // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
187 FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
191 // If successful, createAsmPrinter took ownership of AsmStreamer.
196 // Make sure the code model is set.
197 setCodeModelForStatic();
198 PM.add(createGCInfoDeleter());
202 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
203 /// get machine code emitted. This uses a JITCodeEmitter object to handle
204 /// actually outputting the machine code and resolving things like the address
205 /// of functions. This method should returns true if machine code emission is
208 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
210 CodeGenOpt::Level OptLevel,
211 bool DisableVerify) {
212 // Make sure the code model is set.
213 setCodeModelForJIT();
215 // Add common CodeGen passes.
217 if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
220 addCodeEmitter(PM, OptLevel, JCE);
221 PM.add(createGCInfoDeleter());
223 return false; // success!
226 /// addPassesToEmitMC - Add passes to the specified pass manager to get
227 /// machine code emitted with the MCJIT. This method returns true if machine
228 /// code is not supported. It fills the MCContext Ctx pointer which can be
229 /// used to build custom MCStreamer.
231 bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
233 CodeGenOpt::Level OptLevel,
234 bool DisableVerify) {
235 // Add common CodeGen passes.
236 if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
238 // Make sure the code model is set.
239 setCodeModelForJIT();
241 return false; // success!
244 static void printNoVerify(PassManagerBase &PM, const char *Banner) {
245 if (PrintMachineCode)
246 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
249 static void printAndVerify(PassManagerBase &PM,
250 const char *Banner) {
251 if (PrintMachineCode)
252 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
254 if (VerifyMachineCode)
255 PM.add(createMachineVerifierPass(Banner));
258 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
259 /// emitting to assembly files or machine code output.
261 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
262 CodeGenOpt::Level OptLevel,
264 MCContext *&OutContext) {
265 // Standard LLVM-Level Passes.
267 // Basic AliasAnalysis support.
268 createStandardAliasAnalysisPasses(&PM);
270 // Before running any passes, run the verifier to determine if the input
271 // coming from the front-end and/or optimizer is valid.
273 PM.add(createVerifierPass());
275 // Optionally, tun split-GEPs and no-load GVN.
276 if (EnableSplitGEPGVN) {
277 PM.add(createGEPSplitterPass());
278 PM.add(createGVNPass(/*NoLoads=*/true));
281 // Run loop strength reduction before anything else.
282 if (OptLevel != CodeGenOpt::None && !DisableLSR) {
283 PM.add(createLoopStrengthReducePass(getTargetLowering()));
285 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
288 PM.add(createGCLoweringPass());
290 // Make sure that no unreachable blocks are instruction selected.
291 PM.add(createUnreachableBlockEliminationPass());
293 // Turn exception handling constructs into something the code generators can
295 switch (getMCAsmInfo()->getExceptionHandlingType()) {
296 case ExceptionHandling::SjLj:
297 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
298 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
299 // catch info can get misplaced when a selector ends up more than one block
300 // removed from the parent invoke(s). This could happen when a landing
301 // pad is shared by multiple invokes and is also a target of a normal
302 // edge from elsewhere.
303 PM.add(createSjLjEHPass(getTargetLowering()));
305 case ExceptionHandling::DwarfCFI:
306 case ExceptionHandling::DwarfTable:
307 PM.add(createDwarfEHPass(this));
309 case ExceptionHandling::None:
310 PM.add(createLowerInvokePass(getTargetLowering()));
312 // The lower invoke pass may create unreachable code. Remove it.
313 PM.add(createUnreachableBlockEliminationPass());
317 if (OptLevel != CodeGenOpt::None && !DisableCGP)
318 PM.add(createCodeGenPreparePass(getTargetLowering()));
320 PM.add(createStackProtectorPass(getTargetLowering()));
322 addPreISel(PM, OptLevel);
325 PM.add(createPrintFunctionPass("\n\n"
326 "*** Final LLVM Code input to ISel ***\n",
329 // All passes which modify the LLVM IR are now complete; run the verifier
330 // to ensure that the IR is valid.
332 PM.add(createVerifierPass());
334 // Standard Lower-Level Passes.
336 // Install a MachineModuleInfo class, which is an immutable pass that holds
337 // all the per-module stuff we're generating, including MCContext.
338 TargetAsmInfo *TAI = new TargetAsmInfo(*this);
339 MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo(), TAI);
341 OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
343 // Set up a MachineFunction for the rest of CodeGen to work on.
344 PM.add(new MachineFunctionAnalysis(*this, OptLevel));
346 // Enable FastISel with -fast, but allow that to be overridden.
347 if (EnableFastISelOption == cl::BOU_TRUE ||
348 (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
349 EnableFastISel = true;
351 // Ask the target for an isel.
352 if (addInstSelector(PM, OptLevel))
355 // Print the instruction selected machine code...
356 printAndVerify(PM, "After Instruction Selection");
358 // Expand pseudo-instructions emitted by ISel.
359 PM.add(createExpandISelPseudosPass());
361 // Optimize PHIs before DCE: removing dead PHI cycles may make more
362 // instructions dead.
363 if (OptLevel != CodeGenOpt::None)
364 PM.add(createOptimizePHIsPass());
366 // If the target requests it, assign local variables to stack slots relative
367 // to one another and simplify frame index references where possible.
368 PM.add(createLocalStackSlotAllocationPass());
370 if (OptLevel != CodeGenOpt::None) {
371 // With optimization, dead code should already be eliminated. However
372 // there is one known exception: lowered code for arguments that are only
373 // used by tail calls, where the tail calls reuse the incoming stack
374 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
375 PM.add(createDeadMachineInstructionElimPass());
376 printAndVerify(PM, "After codegen DCE pass");
378 if (!DisableMachineLICM)
379 PM.add(createMachineLICMPass());
380 PM.add(createMachineCSEPass());
381 if (!DisableMachineSink)
382 PM.add(createMachineSinkingPass());
383 printAndVerify(PM, "After Machine LICM, CSE and Sinking passes");
385 PM.add(createPeepholeOptimizerPass());
386 printAndVerify(PM, "After codegen peephole optimization pass");
389 // Pre-ra tail duplication.
390 if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
391 PM.add(createTailDuplicatePass(true));
392 printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
395 // Run pre-ra passes.
396 if (addPreRegAlloc(PM, OptLevel))
397 printAndVerify(PM, "After PreRegAlloc passes");
399 // Perform register allocation.
400 PM.add(createRegisterAllocator(OptLevel));
401 printAndVerify(PM, "After Register Allocation");
403 // Perform stack slot coloring and post-ra machine LICM.
404 if (OptLevel != CodeGenOpt::None) {
405 // FIXME: Re-enable coloring with register when it's capable of adding
408 PM.add(createStackSlotColoringPass(false));
410 // Run post-ra machine LICM to hoist reloads / remats.
411 if (!DisablePostRAMachineLICM)
412 PM.add(createMachineLICMPass(false));
414 printAndVerify(PM, "After StackSlotColoring and postra Machine LICM");
417 // Run post-ra passes.
418 if (addPostRegAlloc(PM, OptLevel))
419 printAndVerify(PM, "After PostRegAlloc passes");
421 PM.add(createLowerSubregsPass());
422 printAndVerify(PM, "After LowerSubregs");
424 // Insert prolog/epilog code. Eliminate abstract frame index references...
425 PM.add(createPrologEpilogCodeInserter());
426 printAndVerify(PM, "After PrologEpilogCodeInserter");
428 // Run pre-sched2 passes.
429 if (addPreSched2(PM, OptLevel))
430 printAndVerify(PM, "After PreSched2 passes");
432 // Second pass scheduler.
433 if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
434 PM.add(createPostRAScheduler(OptLevel));
435 printAndVerify(PM, "After PostRAScheduler");
438 // Branch folding must be run after regalloc and prolog/epilog insertion.
439 if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
440 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
441 printNoVerify(PM, "After BranchFolding");
445 if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
446 PM.add(createTailDuplicatePass(false));
447 printNoVerify(PM, "After TailDuplicate");
450 PM.add(createGCMachineCodeAnalysisPass());
453 PM.add(createGCInfoPrinter(dbgs()));
455 if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
456 PM.add(createCodePlacementOptPass());
457 printNoVerify(PM, "After CodePlacementOpt");
460 if (addPreEmitPass(PM, OptLevel))
461 printNoVerify(PM, "After PreEmit passes");