1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LLVMTargetMachine class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Pass.h"
17 #include "llvm/Assembly/PrintModulePass.h"
18 #include "llvm/Analysis/LoopPass.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/GCStrategy.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Target/TargetAsmInfo.h"
23 #include "llvm/Transforms/Scalar.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/raw_ostream.h"
32 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
33 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
34 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
35 cl::desc("Print LLVM IR input to isel pass"));
36 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
37 cl::desc("Dump emitter generated instructions as assembly"));
38 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
39 cl::desc("Dump garbage collector data"));
40 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
41 cl::desc("Verify generated machine code"),
42 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
44 // When this works it will be on by default.
46 DisablePostRAScheduler("disable-post-RA-scheduler",
47 cl::desc("Disable scheduling after register allocation"),
50 // Enable or disable FastISel. Both options are needed, because
51 // FastISel is enabled by default with -fast, and we wish to be
52 // able to enable or disable fast-isel independently from -fast.
53 static cl::opt<cl::boolOrDefault>
54 EnableFastISelOption("fast-isel", cl::Hidden,
55 cl::desc("Enable the experimental \"fast\" instruction selector"));
58 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
60 CodeGenFileType FileType,
61 CodeGenOpt::Level OptLevel) {
62 // Add common CodeGen passes.
63 if (addCommonCodeGenPasses(PM, OptLevel))
64 return FileModel::Error;
66 // Fold redundant debug labels.
67 PM.add(createDebugLabelFoldingPass());
70 PM.add(createMachineFunctionPrinterPass(cerr));
72 if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
73 PM.add(createMachineFunctionPrinterPass(cerr));
75 if (OptLevel != CodeGenOpt::None)
76 PM.add(createCodePlacementOptPass());
81 case TargetMachine::AssemblyFile:
82 if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
83 return FileModel::Error;
84 return FileModel::AsmFile;
85 case TargetMachine::ObjectFile:
86 if (getMachOWriterInfo())
87 return FileModel::MachOFile;
88 else if (getELFWriterInfo())
89 return FileModel::ElfFile;
92 return FileModel::Error;
95 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
96 /// be split up (e.g., to add an object writer pass), this method can be used to
97 /// finish up adding passes to emit the file, if necessary.
98 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
99 MachineCodeEmitter *MCE,
100 CodeGenOpt::Level OptLevel) {
102 addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
104 PM.add(createGCInfoDeleter());
106 // Delete machine code for this function
107 PM.add(createMachineCodeDeleter());
109 return false; // success!
112 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
113 /// be split up (e.g., to add an object writer pass), this method can be used to
114 /// finish up adding passes to emit the file, if necessary.
115 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
117 CodeGenOpt::Level OptLevel) {
119 addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *JCE);
121 PM.add(createGCInfoDeleter());
123 // Delete machine code for this function
124 PM.add(createMachineCodeDeleter());
126 return false; // success!
129 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
130 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
131 /// actually outputting the machine code and resolving things like the address
132 /// of functions. This method should returns true if machine code emission is
135 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
136 MachineCodeEmitter &MCE,
137 CodeGenOpt::Level OptLevel) {
138 // Add common CodeGen passes.
139 if (addCommonCodeGenPasses(PM, OptLevel))
142 if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
143 PM.add(createMachineFunctionPrinterPass(cerr));
145 addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE);
147 PM.add(createGCInfoDeleter());
149 // Delete machine code for this function
150 PM.add(createMachineCodeDeleter());
152 return false; // success!
155 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
156 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
157 /// actually outputting the machine code and resolving things like the address
158 /// of functions. This method should returns true if machine code emission is
161 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
163 CodeGenOpt::Level OptLevel) {
164 // Add common CodeGen passes.
165 if (addCommonCodeGenPasses(PM, OptLevel))
168 if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
169 PM.add(createMachineFunctionPrinterPass(cerr));
171 addCodeEmitter(PM, OptLevel, PrintEmittedAsm, JCE);
173 PM.add(createGCInfoDeleter());
175 // Delete machine code for this function
176 PM.add(createMachineCodeDeleter());
178 return false; // success!
181 static void printAndVerify(PassManagerBase &PM,
182 bool allowDoubleDefs = false) {
183 if (PrintMachineCode)
184 PM.add(createMachineFunctionPrinterPass(cerr));
186 if (VerifyMachineCode)
187 PM.add(createMachineVerifierPass(allowDoubleDefs));
190 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
191 /// emitting to assembly files or machine code output.
193 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
194 CodeGenOpt::Level OptLevel) {
195 // Standard LLVM-Level Passes.
197 // Run loop strength reduction before anything else.
198 if (OptLevel != CodeGenOpt::None) {
199 PM.add(createLoopStrengthReducePass(getTargetLowering()));
201 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
204 // Turn exception handling constructs into something the code generators can
206 if (!getTargetAsmInfo()->doesSupportExceptionHandling())
207 PM.add(createLowerInvokePass(getTargetLowering()));
209 PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
211 PM.add(createGCLoweringPass());
213 // Make sure that no unreachable blocks are instruction selected.
214 PM.add(createUnreachableBlockEliminationPass());
216 if (OptLevel != CodeGenOpt::None)
217 PM.add(createCodeGenPreparePass(getTargetLowering()));
219 PM.add(createStackProtectorPass(getTargetLowering()));
222 PM.add(createPrintFunctionPass("\n\n"
223 "*** Final LLVM Code input to ISel ***\n",
226 // Standard Lower-Level Passes.
228 // Enable FastISel with -fast, but allow that to be overridden.
229 if (EnableFastISelOption == cl::BOU_TRUE ||
230 (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
231 EnableFastISel = true;
233 // Ask the target for an isel.
234 if (addInstSelector(PM, OptLevel))
237 // Print the instruction selected machine code...
238 printAndVerify(PM, /* allowDoubleDefs= */ true);
240 if (OptLevel != CodeGenOpt::None) {
241 PM.add(createMachineLICMPass());
242 PM.add(createMachineSinkingPass());
243 printAndVerify(PM, /* allowDoubleDefs= */ true);
246 // Run pre-ra passes.
247 if (addPreRegAlloc(PM, OptLevel))
250 // Perform register allocation.
251 PM.add(createRegisterAllocator());
253 // Perform stack slot coloring.
254 if (OptLevel != CodeGenOpt::None)
255 PM.add(createStackSlotColoringPass(OptLevel >= CodeGenOpt::Aggressive));
257 printAndVerify(PM); // Print the register-allocated code
259 // Run post-ra passes.
260 if (addPostRegAlloc(PM, OptLevel))
263 PM.add(createLowerSubregsPass());
266 // Insert prolog/epilog code. Eliminate abstract frame index references...
267 PM.add(createPrologEpilogCodeInserter());
270 // Second pass scheduler.
271 if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
272 PM.add(createPostRAScheduler());
276 // Branch folding must be run after regalloc and prolog/epilog insertion.
277 if (OptLevel != CodeGenOpt::None) {
278 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
282 PM.add(createGCMachineCodeAnalysisPass());
286 PM.add(createGCInfoPrinter(*cerr));