1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LLVMTargetMachine class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Analysis/Verifier.h"
17 #include "llvm/Assembly/PrintModulePass.h"
18 #include "llvm/CodeGen/AsmPrinter.h"
19 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
20 #include "llvm/CodeGen/MachineModuleInfo.h"
21 #include "llvm/CodeGen/GCStrategy.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/MC/MCAsmInfo.h"
25 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/Target/TargetData.h"
27 #include "llvm/Target/TargetRegistry.h"
28 #include "llvm/Transforms/Scalar.h"
29 #include "llvm/ADT/OwningPtr.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/FormattedStream.h"
39 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
40 cl::desc("Disable Post Regalloc"));
41 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
42 cl::desc("Disable branch folding"));
43 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
44 cl::desc("Disable tail duplication"));
45 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
46 cl::desc("Disable pre-register allocation tail duplication"));
47 static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
48 cl::desc("Disable code placement"));
49 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
50 cl::desc("Disable Stack Slot Coloring"));
51 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
52 cl::desc("Disable Machine LICM"));
53 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
55 cl::desc("Disable Machine LICM"));
56 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
57 cl::desc("Disable Machine Sinking"));
58 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
59 cl::desc("Disable Loop Strength Reduction Pass"));
60 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
61 cl::desc("Disable Codegen Prepare"));
62 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
63 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
64 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
65 cl::desc("Print LLVM IR input to isel pass"));
66 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
67 cl::desc("Dump garbage collector data"));
68 static cl::opt<bool> ShowMCEncoding("show-mc-encoding", cl::Hidden,
69 cl::desc("Show encoding in .s output"));
70 static cl::opt<bool> ShowMCInst("show-mc-inst", cl::Hidden,
71 cl::desc("Show instruction structure in .s output"));
72 static cl::opt<bool> EnableMCLogging("enable-mc-api-logging", cl::Hidden,
73 cl::desc("Enable MC API logging"));
74 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
75 cl::desc("Verify generated machine code"),
76 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
77 // Enabled or disable local stack object block allocation. This is an
78 // experimental pass that allocates locals relative to one another before
79 // register allocation and then assigns them to actual stack slots as a block
80 // later in PEI. This will eventually allow targets with limited index offset
81 // range to allocate additional base registers (not just FP and SP) to
82 // more efficiently reference locals, as well as handle situations where
83 // locals cannot be referenced via SP or FP at all (dynamic stack realignment
84 // together with variable sized objects, for example).
85 cl::opt<bool> EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(false),
86 cl::Hidden, cl::desc("Enable pre-regalloc stack frame index allocation"));
88 static cl::opt<cl::boolOrDefault>
89 AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
90 cl::init(cl::BOU_UNSET));
92 static bool getVerboseAsm() {
95 case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
96 case cl::BOU_TRUE: return true;
97 case cl::BOU_FALSE: return false;
101 // Enable or disable FastISel. Both options are needed, because
102 // FastISel is enabled by default with -fast, and we wish to be
103 // able to enable or disable fast-isel independently from -O0.
104 static cl::opt<cl::boolOrDefault>
105 EnableFastISelOption("fast-isel", cl::Hidden,
106 cl::desc("Enable the \"fast\" instruction selector"));
108 // Enable or disable an experimental optimization to split GEPs
109 // and run a special GVN pass which does not examine loads, in
110 // an effort to factor out redundancy implicit in complex GEPs.
111 static cl::opt<bool> EnableSplitGEPGVN("split-gep-gvn", cl::Hidden,
112 cl::desc("Split GEPs and run no-load GVN"));
114 LLVMTargetMachine::LLVMTargetMachine(const Target &T,
115 const std::string &Triple)
116 : TargetMachine(T), TargetTriple(Triple) {
117 AsmInfo = T.createAsmInfo(TargetTriple);
120 // Set the default code model for the JIT for a generic target.
121 // FIXME: Is small right here? or .is64Bit() ? Large : Small?
122 void LLVMTargetMachine::setCodeModelForJIT() {
123 setCodeModel(CodeModel::Small);
126 // Set the default code model for static compilation for a generic target.
127 void LLVMTargetMachine::setCodeModelForStatic() {
128 setCodeModel(CodeModel::Small);
131 bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
132 formatted_raw_ostream &Out,
133 CodeGenFileType FileType,
134 CodeGenOpt::Level OptLevel,
135 bool DisableVerify) {
136 // Add common CodeGen passes.
137 MCContext *Context = 0;
138 if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Context))
140 assert(Context != 0 && "Failed to get MCContext");
142 const MCAsmInfo &MAI = *getMCAsmInfo();
143 OwningPtr<MCStreamer> AsmStreamer;
146 default: return true;
147 case CGFT_AssemblyFile: {
148 MCInstPrinter *InstPrinter =
149 getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI);
151 // Create a code emitter if asked to show the encoding.
152 MCCodeEmitter *MCE = 0;
154 MCE = getTarget().createCodeEmitter(*this, *Context);
156 AsmStreamer.reset(createAsmStreamer(*Context, Out,
157 getTargetData()->isLittleEndian(),
158 getVerboseAsm(), InstPrinter,
162 case CGFT_ObjectFile: {
163 // Create the code emitter for the target if it exists. If not, .o file
165 MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context);
166 TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);
167 if (MCE == 0 || TAB == 0)
170 AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Context,
176 // The Null output is intended for use for performance analysis and testing,
178 AsmStreamer.reset(createNullStreamer(*Context));
183 AsmStreamer.reset(createLoggingStreamer(AsmStreamer.take(), errs()));
185 // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
186 FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
190 // If successful, createAsmPrinter took ownership of AsmStreamer.
195 // Make sure the code model is set.
196 setCodeModelForStatic();
197 PM.add(createGCInfoDeleter());
201 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
202 /// get machine code emitted. This uses a JITCodeEmitter object to handle
203 /// actually outputting the machine code and resolving things like the address
204 /// of functions. This method should returns true if machine code emission is
207 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
209 CodeGenOpt::Level OptLevel,
210 bool DisableVerify) {
211 // Make sure the code model is set.
212 setCodeModelForJIT();
214 // Add common CodeGen passes.
216 if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
219 addCodeEmitter(PM, OptLevel, JCE);
220 PM.add(createGCInfoDeleter());
222 return false; // success!
225 /// addPassesToEmitMC - Add passes to the specified pass manager to get
226 /// machine code emitted with the MCJIT. This method returns true if machine
227 /// code is not supported. It fills the MCContext Ctx pointer which can be
228 /// used to build custom MCStreamer.
230 bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
232 CodeGenOpt::Level OptLevel,
233 bool DisableVerify) {
234 // Add common CodeGen passes.
235 if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
237 // Make sure the code model is set.
238 setCodeModelForJIT();
240 return false; // success!
243 static void printNoVerify(PassManagerBase &PM, const char *Banner) {
244 if (PrintMachineCode)
245 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
248 static void printAndVerify(PassManagerBase &PM,
249 const char *Banner) {
250 if (PrintMachineCode)
251 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
253 if (VerifyMachineCode)
254 PM.add(createMachineVerifierPass());
257 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
258 /// emitting to assembly files or machine code output.
260 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
261 CodeGenOpt::Level OptLevel,
263 MCContext *&OutContext) {
264 // Standard LLVM-Level Passes.
266 // Before running any passes, run the verifier to determine if the input
267 // coming from the front-end and/or optimizer is valid.
269 PM.add(createVerifierPass());
271 // Optionally, tun split-GEPs and no-load GVN.
272 if (EnableSplitGEPGVN) {
273 PM.add(createGEPSplitterPass());
274 PM.add(createGVNPass(/*NoLoads=*/true));
277 // Run loop strength reduction before anything else.
278 if (OptLevel != CodeGenOpt::None && !DisableLSR) {
279 PM.add(createLoopStrengthReducePass(getTargetLowering()));
281 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
284 PM.add(createGCLoweringPass());
286 // Make sure that no unreachable blocks are instruction selected.
287 PM.add(createUnreachableBlockEliminationPass());
289 // Turn exception handling constructs into something the code generators can
291 switch (getMCAsmInfo()->getExceptionHandlingType()) {
292 case ExceptionHandling::SjLj:
293 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
294 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
295 // catch info can get misplaced when a selector ends up more than one block
296 // removed from the parent invoke(s). This could happen when a landing
297 // pad is shared by multiple invokes and is also a target of a normal
298 // edge from elsewhere.
299 PM.add(createSjLjEHPass(getTargetLowering()));
301 case ExceptionHandling::Dwarf:
302 PM.add(createDwarfEHPass(this, OptLevel==CodeGenOpt::None));
304 case ExceptionHandling::None:
305 PM.add(createLowerInvokePass(getTargetLowering()));
307 // The lower invoke pass may create unreachable code. Remove it.
308 PM.add(createUnreachableBlockEliminationPass());
312 if (OptLevel != CodeGenOpt::None && !DisableCGP)
313 PM.add(createCodeGenPreparePass(getTargetLowering()));
315 PM.add(createStackProtectorPass(getTargetLowering()));
317 addPreISel(PM, OptLevel);
320 PM.add(createPrintFunctionPass("\n\n"
321 "*** Final LLVM Code input to ISel ***\n",
324 // All passes which modify the LLVM IR are now complete; run the verifier
325 // to ensure that the IR is valid.
327 PM.add(createVerifierPass());
329 // Standard Lower-Level Passes.
331 // Install a MachineModuleInfo class, which is an immutable pass that holds
332 // all the per-module stuff we're generating, including MCContext.
333 MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo());
335 OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
337 // Set up a MachineFunction for the rest of CodeGen to work on.
338 PM.add(new MachineFunctionAnalysis(*this, OptLevel));
340 // Enable FastISel with -fast, but allow that to be overridden.
341 if (EnableFastISelOption == cl::BOU_TRUE ||
342 (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
343 EnableFastISel = true;
345 // Ask the target for an isel.
346 if (addInstSelector(PM, OptLevel))
349 // Print the instruction selected machine code...
350 printAndVerify(PM, "After Instruction Selection");
352 // Optimize PHIs before DCE: removing dead PHI cycles may make more
353 // instructions dead.
354 if (OptLevel != CodeGenOpt::None)
355 PM.add(createOptimizePHIsPass());
357 // Assign local variables to stack slots relative to one another and simplify
358 // frame index references where possible. Final stack slot locations will be
360 if (EnableLocalStackAlloc)
361 PM.add(createLocalStackSlotAllocationPass());
363 if (OptLevel != CodeGenOpt::None) {
364 // With optimization, dead code should already be eliminated. However
365 // there is one known exception: lowered code for arguments that are only
366 // used by tail calls, where the tail calls reuse the incoming stack
367 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
368 PM.add(createDeadMachineInstructionElimPass());
369 printAndVerify(PM, "After codegen DCE pass");
371 PM.add(createPeepholeOptimizerPass());
372 if (!DisableMachineLICM)
373 PM.add(createMachineLICMPass());
374 PM.add(createMachineCSEPass());
375 if (!DisableMachineSink)
376 PM.add(createMachineSinkingPass());
377 printAndVerify(PM, "After Machine LICM, CSE and Sinking passes");
380 // Pre-ra tail duplication.
381 if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
382 PM.add(createTailDuplicatePass(true));
383 printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
386 // Run pre-ra passes.
387 if (addPreRegAlloc(PM, OptLevel))
388 printAndVerify(PM, "After PreRegAlloc passes");
390 // Perform register allocation.
391 PM.add(createRegisterAllocator(OptLevel));
392 printAndVerify(PM, "After Register Allocation");
394 // Perform stack slot coloring and post-ra machine LICM.
395 if (OptLevel != CodeGenOpt::None) {
396 // FIXME: Re-enable coloring with register when it's capable of adding
399 PM.add(createStackSlotColoringPass(false));
401 // Run post-ra machine LICM to hoist reloads / remats.
402 if (!DisablePostRAMachineLICM)
403 PM.add(createMachineLICMPass(false));
405 printAndVerify(PM, "After StackSlotColoring and postra Machine LICM");
408 // Run post-ra passes.
409 if (addPostRegAlloc(PM, OptLevel))
410 printAndVerify(PM, "After PostRegAlloc passes");
412 PM.add(createLowerSubregsPass());
413 printAndVerify(PM, "After LowerSubregs");
415 // Insert prolog/epilog code. Eliminate abstract frame index references...
416 PM.add(createPrologEpilogCodeInserter());
417 printAndVerify(PM, "After PrologEpilogCodeInserter");
419 // Run pre-sched2 passes.
420 if (addPreSched2(PM, OptLevel))
421 printAndVerify(PM, "After PreSched2 passes");
423 // Second pass scheduler.
424 if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
425 PM.add(createPostRAScheduler(OptLevel));
426 printAndVerify(PM, "After PostRAScheduler");
429 // Branch folding must be run after regalloc and prolog/epilog insertion.
430 if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
431 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
432 printNoVerify(PM, "After BranchFolding");
436 if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
437 PM.add(createTailDuplicatePass(false));
438 printNoVerify(PM, "After TailDuplicate");
441 PM.add(createGCMachineCodeAnalysisPass());
444 PM.add(createGCInfoPrinter(dbgs()));
446 if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
447 PM.add(createCodePlacementOptPass());
448 printNoVerify(PM, "After CodePlacementOpt");
451 if (addPreEmitPass(PM, OptLevel))
452 printNoVerify(PM, "After PreEmit passes");