1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LLVMTargetMachine class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Pass.h"
17 #include "llvm/Assembly/PrintModulePass.h"
18 #include "llvm/Analysis/LoopPass.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/Collector.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Target/TargetAsmInfo.h"
23 #include "llvm/Transforms/Scalar.h"
24 #include "llvm/Support/CommandLine.h"
27 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
28 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
29 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
30 cl::desc("Print LLVM IR input to isel pass"));
31 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
32 cl::desc("Dump emitter generated instructions as assembly"));
33 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
34 cl::desc("Dump garbage collector data"));
36 // Hidden options to help debugging
38 EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
39 cl::desc("Perform sinking on machine code"));
41 AlignLoops("align-loops", cl::init(true), cl::Hidden,
42 cl::desc("Align loop headers"));
44 PerformLICM("machine-licm",
45 cl::init(false), cl::Hidden,
46 cl::desc("Perform loop-invariant code motion on machine code"));
48 // When this works it will be on by default.
50 DisablePostRAScheduler("disable-post-RA-scheduler",
51 cl::desc("Disable scheduling after register allocation"),
55 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
57 CodeGenFileType FileType,
59 // Standard LLVM-Level Passes.
61 // Run loop strength reduction before anything else.
63 PM.add(createLoopStrengthReducePass(getTargetLowering()));
65 PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
68 PM.add(createGCLoweringPass());
70 if (!getTargetAsmInfo()->doesSupportExceptionHandling())
71 PM.add(createLowerInvokePass(getTargetLowering()));
73 // Make sure that no unreachable blocks are instruction selected.
74 PM.add(createUnreachableBlockEliminationPass());
77 PM.add(createCodeGenPreparePass(getTargetLowering()));
80 PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
83 // Ask the target for an isel.
84 if (addInstSelector(PM, Fast))
85 return FileModel::Error;
87 // Print the instruction selected machine code...
89 PM.add(createMachineFunctionPrinterPass(cerr));
92 PM.add(createMachineLICMPass());
95 PM.add(createMachineSinkingPass());
97 // Perform register allocation to convert to a concrete x86 representation
98 PM.add(createRegisterAllocator());
100 if (PrintMachineCode)
101 PM.add(createMachineFunctionPrinterPass(cerr));
103 PM.add(createLowerSubregsPass());
105 if (PrintMachineCode) // Print the subreg lowered code
106 PM.add(createMachineFunctionPrinterPass(cerr));
108 // Run post-ra passes.
109 if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
110 PM.add(createMachineFunctionPrinterPass(cerr));
112 // Insert prolog/epilog code. Eliminate abstract frame index references...
113 PM.add(createPrologEpilogCodeInserter());
115 // Second pass scheduler.
116 if (!Fast && !DisablePostRAScheduler)
117 PM.add(createPostRAScheduler());
119 // Branch folding must be run after regalloc and prolog/epilog insertion.
121 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
123 PM.add(createGCMachineCodeAnalysisPass());
124 if (PrintMachineCode)
125 PM.add(createMachineFunctionPrinterPass(cerr));
128 PM.add(createCollectorMetadataPrinter(*cerr));
130 // Fold redundant debug labels.
131 PM.add(createDebugLabelFoldingPass());
133 if (PrintMachineCode) // Print the register-allocated code
134 PM.add(createMachineFunctionPrinterPass(cerr));
136 if (addPreEmitPass(PM, Fast) && PrintMachineCode)
137 PM.add(createMachineFunctionPrinterPass(cerr));
139 if (AlignLoops && !OptimizeForSize)
140 PM.add(createLoopAlignerPass());
145 case TargetMachine::AssemblyFile:
146 if (addAssemblyEmitter(PM, Fast, Out))
147 return FileModel::Error;
148 return FileModel::AsmFile;
149 case TargetMachine::ObjectFile:
150 if (getMachOWriterInfo())
151 return FileModel::MachOFile;
152 else if (getELFWriterInfo())
153 return FileModel::ElfFile;
156 return FileModel::Error;
159 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
160 /// be split up (e.g., to add an object writer pass), this method can be used to
161 /// finish up adding passes to emit the file, if necessary.
162 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
163 MachineCodeEmitter *MCE,
166 addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
168 PM.add(createCollectorMetadataDeleter());
170 // Delete machine code for this function
171 PM.add(createMachineCodeDeleter());
173 return false; // success!
176 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
177 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
178 /// actually outputting the machine code and resolving things like the address
179 /// of functions. This method should returns true if machine code emission is
182 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
183 MachineCodeEmitter &MCE,
185 // Standard LLVM-Level Passes.
187 // Run loop strength reduction before anything else.
189 PM.add(createLoopStrengthReducePass(getTargetLowering()));
191 PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
194 PM.add(createGCLoweringPass());
196 if (!getTargetAsmInfo()->doesSupportExceptionHandling())
197 PM.add(createLowerInvokePass(getTargetLowering()));
199 // Make sure that no unreachable blocks are instruction selected.
200 PM.add(createUnreachableBlockEliminationPass());
203 PM.add(createCodeGenPreparePass(getTargetLowering()));
206 PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
209 // Ask the target for an isel.
210 if (addInstSelector(PM, Fast))
213 // Print the instruction selected machine code...
214 if (PrintMachineCode)
215 PM.add(createMachineFunctionPrinterPass(cerr));
218 PM.add(createMachineLICMPass());
221 PM.add(createMachineSinkingPass());
223 // Perform register allocation to convert to a concrete x86 representation
224 PM.add(createRegisterAllocator());
226 if (PrintMachineCode)
227 PM.add(createMachineFunctionPrinterPass(cerr));
229 PM.add(createLowerSubregsPass());
231 if (PrintMachineCode) // Print the subreg lowered code
232 PM.add(createMachineFunctionPrinterPass(cerr));
234 // Run post-ra passes.
235 if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
236 PM.add(createMachineFunctionPrinterPass(cerr));
238 // Insert prolog/epilog code. Eliminate abstract frame index references...
239 PM.add(createPrologEpilogCodeInserter());
241 if (PrintMachineCode) // Print the register-allocated code
242 PM.add(createMachineFunctionPrinterPass(cerr));
244 // Second pass scheduler.
246 PM.add(createPostRAScheduler());
248 // Branch folding must be run after regalloc and prolog/epilog insertion.
250 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
252 PM.add(createGCMachineCodeAnalysisPass());
253 if (PrintMachineCode)
254 PM.add(createMachineFunctionPrinterPass(cerr));
257 PM.add(createCollectorMetadataPrinter(*cerr));
259 if (addPreEmitPass(PM, Fast) && PrintMachineCode)
260 PM.add(createMachineFunctionPrinterPass(cerr));
262 addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
264 PM.add(createCollectorMetadataDeleter());
266 // Delete machine code for this function
267 PM.add(createMachineCodeDeleter());
269 return false; // success!