lib/CodeGen/LLVMTargetMachine.cpp

   1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the LLVMTargetMachine class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/Target/TargetMachine.h"
  15 #include "llvm/PassManager.h"
  16 #include "llvm/Pass.h"
  17 #include "llvm/Assembly/PrintModulePass.h"
  18 #include "llvm/Analysis/LoopPass.h"
  19 #include "llvm/CodeGen/Passes.h"
  20 #include "llvm/CodeGen/GCStrategy.h"
  21 #include "llvm/Target/TargetOptions.h"
  22 #include "llvm/Target/TargetAsmInfo.h"
  23 #include "llvm/Transforms/Scalar.h"
  24 #include "llvm/Support/CommandLine.h"
  25 #include "llvm/Support/raw_ostream.h"
  26 using namespace llvm;
  27
  28 namespace llvm {
  29   bool EnableFastISel;
  30 }
  31
  32 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
  33     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
  34 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
  35     cl::desc("Print LLVM IR input to isel pass"));
  36 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
  37     cl::desc("Dump emitter generated instructions as assembly"));
  38 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
  39     cl::desc("Dump garbage collector data"));
  40
  41 // Hidden options to help debugging
  42 static cl::opt<bool>
  43 EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
  44               cl::desc("Perform sinking on machine code"));
  45 static cl::opt<bool>
  46 EnableLICM("machine-licm",
  47            cl::init(false), cl::Hidden,
  48            cl::desc("Perform loop-invariant code motion on machine code"));
  49
  50 // When this works it will be on by default.
  51 static cl::opt<bool>
  52 DisablePostRAScheduler("disable-post-RA-scheduler",
  53                        cl::desc("Disable scheduling after register allocation"),
  54                        cl::init(true));
  55
  56 // Enable or disable FastISel. Both options are needed, because
  57 // FastISel is enabled by default with -fast, and we wish to be
  58 // able to enable or disable fast-isel independently from -fast.
  59 static cl::opt<cl::boolOrDefault>
  60 EnableFastISelOption("fast-isel", cl::Hidden,
  61   cl::desc("Enable the experimental \"fast\" instruction selector"));
  62
  63 FileModel::Model
  64 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
  65                                        raw_ostream &Out,
  66                                        CodeGenFileType FileType,
  67                                        bool Fast) {
  68   // Add common CodeGen passes.
  69   if (addCommonCodeGenPasses(PM, Fast))
  70     return FileModel::Error;
  71
  72   // Fold redundant debug labels.
  73   PM.add(createDebugLabelFoldingPass());
  74
  75   if (PrintMachineCode)
  76     PM.add(createMachineFunctionPrinterPass(cerr));
  77
  78   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
  79     PM.add(createMachineFunctionPrinterPass(cerr));
  80
  81   if (!Fast)
  82     PM.add(createLoopAlignerPass());
  83
  84   switch (FileType) {
  85   default:
  86     break;
  87   case TargetMachine::AssemblyFile:
  88     if (addAssemblyEmitter(PM, Fast, Out))
  89       return FileModel::Error;
  90     return FileModel::AsmFile;
  91   case TargetMachine::ObjectFile:
  92     if (getMachOWriterInfo())
  93       return FileModel::MachOFile;
  94     else if (getELFWriterInfo())
  95       return FileModel::ElfFile;
  96   }
  97
  98   return FileModel::Error;
  99 }
 100
 101 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
 102 /// be split up (e.g., to add an object writer pass), this method can be used to
 103 /// finish up adding passes to emit the file, if necessary.
 104 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
 105                                                   MachineCodeEmitter *MCE,
 106                                                   bool Fast) {
 107   if (MCE)
 108     addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
 109
 110   PM.add(createGCInfoDeleter());
 111
 112   // Delete machine code for this function
 113   PM.add(createMachineCodeDeleter());
 114
 115   return false; // success!
 116 }
 117
 118 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
 119 /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
 120 /// actually outputting the machine code and resolving things like the address
 121 /// of functions.  This method should returns true if machine code emission is
 122 /// not supported.
 123 ///
 124 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
 125                                                    MachineCodeEmitter &MCE,
 126                                                    bool Fast) {
 127   // Add common CodeGen passes.
 128   if (addCommonCodeGenPasses(PM, Fast))
 129     return true;
 130
 131   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
 132     PM.add(createMachineFunctionPrinterPass(cerr));
 133
 134   addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
 135
 136   PM.add(createGCInfoDeleter());
 137
 138   // Delete machine code for this function
 139   PM.add(createMachineCodeDeleter());
 140
 141   return false; // success!
 142 }
 143
 144 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
 145 /// both emitting to assembly files or machine code output.
 146 ///
 147 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
 148   // Standard LLVM-Level Passes.
 149
 150   // Run loop strength reduction before anything else.
 151   if (!Fast) {
 152     PM.add(createLoopStrengthReducePass(getTargetLowering()));
 153     if (PrintLSR)
 154       PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
 155   }
 156
 157   PM.add(createGCLoweringPass());
 158
 159   if (!getTargetAsmInfo()->doesSupportExceptionHandling())
 160     PM.add(createLowerInvokePass(getTargetLowering()));
 161
 162   // Make sure that no unreachable blocks are instruction selected.
 163   PM.add(createUnreachableBlockEliminationPass());
 164
 165   if (!Fast)
 166     PM.add(createCodeGenPreparePass(getTargetLowering()));
 167
 168   PM.add(createStackProtectorPass(getTargetLowering()));
 169
 170   if (PrintISelInput)
 171     PM.add(createPrintFunctionPass("\n\n"
 172                                    "*** Final LLVM Code input to ISel ***\n",
 173                                    &errs()));
 174
 175   // Standard Lower-Level Passes.
 176
 177   // Enable FastISel with -fast, but allow that to be overridden.
 178   if (EnableFastISelOption == cl::BOU_TRUE ||
 179       (Fast && EnableFastISelOption != cl::BOU_FALSE))
 180     EnableFastISel = true;
 181
 182   // Ask the target for an isel.
 183   if (addInstSelector(PM, Fast))
 184     return true;
 185
 186   // Print the instruction selected machine code...
 187   if (PrintMachineCode)
 188     PM.add(createMachineFunctionPrinterPass(cerr));
 189
 190   if (EnableLICM)
 191     PM.add(createMachineLICMPass());
 192
 193   if (EnableSinking)
 194     PM.add(createMachineSinkingPass());
 195
 196   // Run pre-ra passes.
 197   if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
 198     PM.add(createMachineFunctionPrinterPass(cerr));
 199
 200   // Perform register allocation.
 201   PM.add(createRegisterAllocator());
 202
 203   // Perform stack slot coloring.
 204   if (!Fast)
 205     PM.add(createStackSlotColoringPass());
 206
 207   if (PrintMachineCode)  // Print the register-allocated code
 208     PM.add(createMachineFunctionPrinterPass(cerr));
 209
 210   // Run post-ra passes.
 211   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
 212     PM.add(createMachineFunctionPrinterPass(cerr));
 213
 214   if (PrintMachineCode)
 215     PM.add(createMachineFunctionPrinterPass(cerr));
 216
 217   PM.add(createLowerSubregsPass());
 218
 219   if (PrintMachineCode)  // Print the subreg lowered code
 220     PM.add(createMachineFunctionPrinterPass(cerr));
 221
 222   // Insert prolog/epilog code.  Eliminate abstract frame index references...
 223   PM.add(createPrologEpilogCodeInserter());
 224
 225   if (PrintMachineCode)
 226     PM.add(createMachineFunctionPrinterPass(cerr));
 227
 228   // Second pass scheduler.
 229   if (!Fast && !DisablePostRAScheduler) {
 230     PM.add(createPostRAScheduler());
 231
 232     if (PrintMachineCode)
 233       PM.add(createMachineFunctionPrinterPass(cerr));
 234   }
 235
 236   // Branch folding must be run after regalloc and prolog/epilog insertion.
 237   if (!Fast)
 238     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 239
 240   if (PrintMachineCode)
 241     PM.add(createMachineFunctionPrinterPass(cerr));
 242
 243   PM.add(createGCMachineCodeAnalysisPass());
 244
 245   if (PrintMachineCode)
 246     PM.add(createMachineFunctionPrinterPass(cerr));
 247
 248   if (PrintGCInfo)
 249     PM.add(createGCInfoPrinter(*cerr));
 250
 251   return false;
 252 }