lib/CodeGen/LLVMTargetMachine.cpp

   1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the LLVMTargetMachine class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/Target/TargetMachine.h"
  15 #include "llvm/PassManager.h"
  16 #include "llvm/Pass.h"
  17 #include "llvm/Assembly/PrintModulePass.h"
  18 #include "llvm/Analysis/LoopPass.h"
  19 #include "llvm/CodeGen/Passes.h"
  20 #include "llvm/CodeGen/GCStrategy.h"
  21 #include "llvm/Target/TargetOptions.h"
  22 #include "llvm/Target/TargetAsmInfo.h"
  23 #include "llvm/Transforms/Scalar.h"
  24 #include "llvm/Support/CommandLine.h"
  25 #include "llvm/Support/raw_ostream.h"
  26 using namespace llvm;
  27
  28 namespace llvm {
  29   bool EnableFastISel;
  30 }
  31
  32 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
  33     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
  34 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
  35     cl::desc("Print LLVM IR input to isel pass"));
  36 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
  37     cl::desc("Dump emitter generated instructions as assembly"));
  38 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
  39     cl::desc("Dump garbage collector data"));
  40
  41 // Hidden options to help debugging
  42 static cl::opt<bool>
  43 EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
  44               cl::desc("Perform sinking on machine code"));
  45 static cl::opt<bool>
  46 EnableLICM("machine-licm",
  47            cl::init(false), cl::Hidden,
  48            cl::desc("Perform loop-invariant code motion on machine code"));
  49
  50 // When this works it will be on by default.
  51 static cl::opt<bool>
  52 DisablePostRAScheduler("disable-post-RA-scheduler",
  53                        cl::desc("Disable scheduling after register allocation"),
  54                        cl::init(true));
  55
  56 // Enable or disable FastISel. Both options are needed, because
  57 // FastISel is enabled by default with -fast, and we wish to be
  58 // able to enable or disable fast-isel independently from -fast.
  59 static cl::opt<cl::boolOrDefault>
  60 EnableFastISelOption("fast-isel", cl::Hidden,
  61   cl::desc("Enable the experimental \"fast\" instruction selector"));
  62
  63 // Enable stack protectors.
  64 static cl::opt<SSP::StackProtectorLevel>
  65 EnableStackProtector("enable-stack-protector",
  66                      cl::desc("Stack canary protection level: (default: off)"),
  67                      cl::init(SSP::OFF),
  68                      cl::values(clEnumValN(SSP::ALL,  "all",
  69                                          "All functions get stack protectors."),
  70                                 clEnumValN(SSP::SOME, "some",
  71                          "Only functions requiring stack protectors get them."),
  72                                 clEnumValN(SSP::OFF,  "off",
  73                                           "No functions get stack protectors."),
  74                                 clEnumValEnd));
  75
  76 FileModel::Model
  77 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
  78                                        raw_ostream &Out,
  79                                        CodeGenFileType FileType,
  80                                        bool Fast) {
  81   // Add common CodeGen passes.
  82   if (addCommonCodeGenPasses(PM, Fast))
  83     return FileModel::Error;
  84
  85   // Fold redundant debug labels.
  86   PM.add(createDebugLabelFoldingPass());
  87
  88   if (PrintMachineCode)
  89     PM.add(createMachineFunctionPrinterPass(cerr));
  90
  91   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
  92     PM.add(createMachineFunctionPrinterPass(cerr));
  93
  94   if (!Fast)
  95     PM.add(createLoopAlignerPass());
  96
  97   switch (FileType) {
  98   default:
  99     break;
 100   case TargetMachine::AssemblyFile:
 101     if (addAssemblyEmitter(PM, Fast, Out))
 102       return FileModel::Error;
 103     return FileModel::AsmFile;
 104   case TargetMachine::ObjectFile:
 105     if (getMachOWriterInfo())
 106       return FileModel::MachOFile;
 107     else if (getELFWriterInfo())
 108       return FileModel::ElfFile;
 109   }
 110
 111   return FileModel::Error;
 112 }
 113
 114 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
 115 /// be split up (e.g., to add an object writer pass), this method can be used to
 116 /// finish up adding passes to emit the file, if necessary.
 117 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
 118                                                   MachineCodeEmitter *MCE,
 119                                                   bool Fast) {
 120   if (MCE)
 121     addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
 122
 123   PM.add(createGCInfoDeleter());
 124
 125   // Delete machine code for this function
 126   PM.add(createMachineCodeDeleter());
 127
 128   return false; // success!
 129 }
 130
 131 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
 132 /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
 133 /// actually outputting the machine code and resolving things like the address
 134 /// of functions.  This method should returns true if machine code emission is
 135 /// not supported.
 136 ///
 137 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
 138                                                    MachineCodeEmitter &MCE,
 139                                                    bool Fast) {
 140   // Add common CodeGen passes.
 141   if (addCommonCodeGenPasses(PM, Fast))
 142     return true;
 143
 144   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
 145     PM.add(createMachineFunctionPrinterPass(cerr));
 146
 147   addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
 148
 149   PM.add(createGCInfoDeleter());
 150
 151   // Delete machine code for this function
 152   PM.add(createMachineCodeDeleter());
 153
 154   return false; // success!
 155 }
 156
 157 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
 158 /// both emitting to assembly files or machine code output.
 159 ///
 160 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
 161   // Standard LLVM-Level Passes.
 162
 163   // Run loop strength reduction before anything else.
 164   if (!Fast) {
 165     PM.add(createLoopStrengthReducePass(getTargetLowering()));
 166     if (PrintLSR)
 167       PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
 168   }
 169
 170   PM.add(createGCLoweringPass());
 171
 172   if (!getTargetAsmInfo()->doesSupportExceptionHandling())
 173     PM.add(createLowerInvokePass(getTargetLowering()));
 174
 175   // Make sure that no unreachable blocks are instruction selected.
 176   PM.add(createUnreachableBlockEliminationPass());
 177
 178   if (!Fast)
 179     PM.add(createCodeGenPreparePass(getTargetLowering()));
 180
 181   if (EnableStackProtector != SSP::OFF)
 182     PM.add(createStackProtectorPass(EnableStackProtector, getTargetLowering()));
 183
 184   if (PrintISelInput)
 185     PM.add(createPrintFunctionPass("\n\n"
 186                                    "*** Final LLVM Code input to ISel ***\n",
 187                                    &errs()));
 188
 189   // Standard Lower-Level Passes.
 190
 191   // Enable FastISel with -fast, but allow that to be overridden.
 192   if (EnableFastISelOption == cl::BOU_TRUE ||
 193       (Fast && EnableFastISelOption != cl::BOU_FALSE))
 194     EnableFastISel = true;
 195
 196   // Ask the target for an isel.
 197   if (addInstSelector(PM, Fast))
 198     return true;
 199
 200   // Print the instruction selected machine code...
 201   if (PrintMachineCode)
 202     PM.add(createMachineFunctionPrinterPass(cerr));
 203
 204   if (EnableLICM)
 205     PM.add(createMachineLICMPass());
 206
 207   if (EnableSinking)
 208     PM.add(createMachineSinkingPass());
 209
 210   // Run pre-ra passes.
 211   if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
 212     PM.add(createMachineFunctionPrinterPass(cerr));
 213
 214   // Perform register allocation.
 215   PM.add(createRegisterAllocator());
 216
 217   // Perform stack slot coloring.
 218   if (!Fast)
 219     PM.add(createStackSlotColoringPass());
 220
 221   if (PrintMachineCode)  // Print the register-allocated code
 222     PM.add(createMachineFunctionPrinterPass(cerr));
 223
 224   // Run post-ra passes.
 225   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
 226     PM.add(createMachineFunctionPrinterPass(cerr));
 227
 228   if (PrintMachineCode)
 229     PM.add(createMachineFunctionPrinterPass(cerr));
 230
 231   PM.add(createLowerSubregsPass());
 232
 233   if (PrintMachineCode)  // Print the subreg lowered code
 234     PM.add(createMachineFunctionPrinterPass(cerr));
 235
 236   // Insert prolog/epilog code.  Eliminate abstract frame index references...
 237   PM.add(createPrologEpilogCodeInserter());
 238
 239   if (PrintMachineCode)
 240     PM.add(createMachineFunctionPrinterPass(cerr));
 241
 242   // Second pass scheduler.
 243   if (!Fast && !DisablePostRAScheduler)
 244     PM.add(createPostRAScheduler());
 245
 246   // Branch folding must be run after regalloc and prolog/epilog insertion.
 247   if (!Fast)
 248     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 249
 250   PM.add(createGCMachineCodeAnalysisPass());
 251
 252   if (PrintMachineCode)
 253     PM.add(createMachineFunctionPrinterPass(cerr));
 254
 255   if (PrintGCInfo)
 256     PM.add(createGCInfoPrinter(*cerr));
 257
 258   return false;
 259 }