lib/CodeGen/LLVMTargetMachine.cpp

   1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the LLVMTargetMachine class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/Target/TargetMachine.h"
  15 #include "llvm/PassManager.h"
  16 #include "llvm/Pass.h"
  17 #include "llvm/Assembly/PrintModulePass.h"
  18 #include "llvm/Analysis/LoopPass.h"
  19 #include "llvm/CodeGen/Passes.h"
  20 #include "llvm/CodeGen/Collector.h"
  21 #include "llvm/Target/TargetOptions.h"
  22 #include "llvm/Target/TargetAsmInfo.h"
  23 #include "llvm/Transforms/Scalar.h"
  24 #include "llvm/Support/CommandLine.h"
  25 using namespace llvm;
  26
  27 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
  28     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
  29 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
  30     cl::desc("Print LLVM IR input to isel pass"));
  31 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
  32     cl::desc("Dump emitter generated instructions as assembly"));
  33 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
  34     cl::desc("Dump garbage collector data"));
  35
  36 // Hidden options to help debugging
  37 static cl::opt<bool>
  38 EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
  39               cl::desc("Perform sinking on machine code"));
  40 static cl::opt<bool>
  41 EnableStackColoring("stack-coloring",
  42             cl::init(true), cl::Hidden,
  43             cl::desc("Perform stack slot coloring"));
  44 static cl::opt<bool>
  45 EnableLICM("machine-licm",
  46            cl::init(false), cl::Hidden,
  47            cl::desc("Perform loop-invariant code motion on machine code"));
  48
  49 // When this works it will be on by default.
  50 static cl::opt<bool>
  51 DisablePostRAScheduler("disable-post-RA-scheduler",
  52                        cl::desc("Disable scheduling after register allocation"),
  53                        cl::init(true));
  54
  55 FileModel::Model
  56 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
  57                                        std::ostream &Out,
  58                                        CodeGenFileType FileType,
  59                                        bool Fast) {
  60   // Standard LLVM-Level Passes.
  61
  62   // Run loop strength reduction before anything else.
  63   if (!Fast) {
  64     PM.add(createLoopStrengthReducePass(getTargetLowering()));
  65     if (PrintLSR)
  66       PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
  67   }
  68
  69   PM.add(createGCLoweringPass());
  70
  71   if (!getTargetAsmInfo()->doesSupportExceptionHandling())
  72     PM.add(createLowerInvokePass(getTargetLowering()));
  73
  74   // Make sure that no unreachable blocks are instruction selected.
  75   PM.add(createUnreachableBlockEliminationPass());
  76
  77   if (!Fast)
  78     PM.add(createCodeGenPreparePass(getTargetLowering()));
  79
  80   if (PrintISelInput)
  81     PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
  82                                  &cerr));
  83
  84   // Ask the target for an isel.
  85   if (addInstSelector(PM, Fast))
  86     return FileModel::Error;
  87
  88   // Print the instruction selected machine code...
  89   if (PrintMachineCode)
  90     PM.add(createMachineFunctionPrinterPass(cerr));
  91
  92   if (EnableLICM)
  93     PM.add(createMachineLICMPass());
  94
  95   if (EnableSinking)
  96     PM.add(createMachineSinkingPass());
  97
  98   // Run pre-ra passes.
  99   if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
 100     PM.add(createMachineFunctionPrinterPass(cerr));
 101
 102   // Perform register allocation to convert to a concrete x86 representation
 103   PM.add(createRegisterAllocator());
 104
 105   // Perform stack slot coloring.
 106   if (EnableStackColoring)
 107     PM.add(createStackSlotColoringPass());
 108
 109   if (PrintMachineCode)  // Print the register-allocated code
 110     PM.add(createMachineFunctionPrinterPass(cerr));
 111
 112   // Run post-ra passes.
 113   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
 114     PM.add(createMachineFunctionPrinterPass(cerr));
 115
 116   PM.add(createLowerSubregsPass());
 117
 118   if (PrintMachineCode)  // Print the subreg lowered code
 119     PM.add(createMachineFunctionPrinterPass(cerr));
 120
 121   // Insert prolog/epilog code.  Eliminate abstract frame index references...
 122   PM.add(createPrologEpilogCodeInserter());
 123
 124   if (PrintMachineCode)
 125     PM.add(createMachineFunctionPrinterPass(cerr));
 126
 127   // Second pass scheduler.
 128   if (!Fast && !DisablePostRAScheduler)
 129     PM.add(createPostRAScheduler());
 130
 131   // Branch folding must be run after regalloc and prolog/epilog insertion.
 132   if (!Fast)
 133     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 134
 135   PM.add(createGCMachineCodeAnalysisPass());
 136   if (PrintMachineCode)
 137     PM.add(createMachineFunctionPrinterPass(cerr));
 138
 139   if (PrintGCInfo)
 140     PM.add(createCollectorMetadataPrinter(*cerr));
 141
 142   // Fold redundant debug labels.
 143   PM.add(createDebugLabelFoldingPass());
 144
 145   if (PrintMachineCode)  // Print the register-allocated code
 146     PM.add(createMachineFunctionPrinterPass(cerr));
 147
 148   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
 149     PM.add(createMachineFunctionPrinterPass(cerr));
 150
 151   if (!Fast && !OptimizeForSize)
 152     PM.add(createLoopAlignerPass());
 153
 154   switch (FileType) {
 155   default:
 156     break;
 157   case TargetMachine::AssemblyFile:
 158     if (addAssemblyEmitter(PM, Fast, Out))
 159       return FileModel::Error;
 160     return FileModel::AsmFile;
 161   case TargetMachine::ObjectFile:
 162     if (getMachOWriterInfo())
 163       return FileModel::MachOFile;
 164     else if (getELFWriterInfo())
 165       return FileModel::ElfFile;
 166   }
 167
 168   return FileModel::Error;
 169 }
 170
 171 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
 172 /// be split up (e.g., to add an object writer pass), this method can be used to
 173 /// finish up adding passes to emit the file, if necessary.
 174 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
 175                                                   MachineCodeEmitter *MCE,
 176                                                   bool Fast) {
 177   if (MCE)
 178     addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
 179
 180   PM.add(createCollectorMetadataDeleter());
 181
 182   // Delete machine code for this function
 183   PM.add(createMachineCodeDeleter());
 184
 185   return false; // success!
 186 }
 187
 188 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
 189 /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
 190 /// actually outputting the machine code and resolving things like the address
 191 /// of functions.  This method should returns true if machine code emission is
 192 /// not supported.
 193 ///
 194 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
 195                                                    MachineCodeEmitter &MCE,
 196                                                    bool Fast) {
 197   // Standard LLVM-Level Passes.
 198
 199   // Run loop strength reduction before anything else.
 200   if (!Fast) {
 201     PM.add(createLoopStrengthReducePass(getTargetLowering()));
 202     if (PrintLSR)
 203       PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
 204   }
 205
 206   PM.add(createGCLoweringPass());
 207
 208   if (!getTargetAsmInfo()->doesSupportExceptionHandling())
 209     PM.add(createLowerInvokePass(getTargetLowering()));
 210
 211   // Make sure that no unreachable blocks are instruction selected.
 212   PM.add(createUnreachableBlockEliminationPass());
 213
 214   if (!Fast)
 215     PM.add(createCodeGenPreparePass(getTargetLowering()));
 216
 217   if (PrintISelInput)
 218     PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
 219                                  &cerr));
 220
 221   // Ask the target for an isel.
 222   if (addInstSelector(PM, Fast))
 223     return true;
 224
 225   // Print the instruction selected machine code...
 226   if (PrintMachineCode)
 227     PM.add(createMachineFunctionPrinterPass(cerr));
 228
 229   if (EnableLICM)
 230     PM.add(createMachineLICMPass());
 231
 232   if (EnableSinking)
 233     PM.add(createMachineSinkingPass());
 234
 235   // Run pre-ra passes.
 236   if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
 237     PM.add(createMachineFunctionPrinterPass(cerr));
 238
 239   // Perform register allocation.
 240   PM.add(createRegisterAllocator());
 241
 242   // Perform stack slot coloring.
 243   if (EnableStackColoring)
 244     PM.add(createStackSlotColoringPass());
 245
 246   if (PrintMachineCode)
 247     PM.add(createMachineFunctionPrinterPass(cerr));
 248
 249   // Run post-ra passes.
 250   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
 251     PM.add(createMachineFunctionPrinterPass(cerr));
 252
 253   if (PrintMachineCode)  // Print the register-allocated code
 254     PM.add(createMachineFunctionPrinterPass(cerr));
 255
 256   PM.add(createLowerSubregsPass());
 257
 258   if (PrintMachineCode)  // Print the subreg lowered code
 259     PM.add(createMachineFunctionPrinterPass(cerr));
 260
 261   // Insert prolog/epilog code.  Eliminate abstract frame index references...
 262   PM.add(createPrologEpilogCodeInserter());
 263
 264   if (PrintMachineCode)
 265     PM.add(createMachineFunctionPrinterPass(cerr));
 266
 267   // Second pass scheduler.
 268   if (!Fast)
 269     PM.add(createPostRAScheduler());
 270
 271   // Branch folding must be run after regalloc and prolog/epilog insertion.
 272   if (!Fast)
 273     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 274
 275   PM.add(createGCMachineCodeAnalysisPass());
 276
 277   if (PrintMachineCode)
 278     PM.add(createMachineFunctionPrinterPass(cerr));
 279
 280   if (PrintGCInfo)
 281     PM.add(createCollectorMetadataPrinter(*cerr));
 282
 283   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
 284     PM.add(createMachineFunctionPrinterPass(cerr));
 285
 286   addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
 287
 288   PM.add(createCollectorMetadataDeleter());
 289
 290   // Delete machine code for this function
 291   PM.add(createMachineCodeDeleter());
 292
 293   return false; // success!
 294 }